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[/] [tinyvliw8/] [trunk/] [src/] [vhdl/] [proc/] [jmpExec.vhd] - Blame information for rev 2

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-----------------------------------------------------------------
-- Project: Aeternitas
-- Author:  Oliver Stecklina <stecklina@ihp-microelectronics.com
-- Date:    24.10.2013 
-- File:    jmpExec.vhd
-- Design:  AeternitasSWUR
-----------------------------------------------------------------
-- Description : This unit is the jump execution unit of the
--               embedded 8-bit VLIW processor.
-----------------------------------------------------------------
-- $Log$
-----------------------------------------------------------------
 
library ieee;
 
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity vliwProc_jmpExec is
        port (
                en_n      : in std_logic;
 
                esb       : in std_logic_vector(3 downto 0);
 
                dst       : in std_logic_vector(10 downto 0);
                as        : in std_logic_vector(1 downto 0);
 
                jmpDst    : out std_logic_vector(10 downto 0);
                jmpEn_n   : out std_logic;
 
                cz        : in std_logic_vector(1 downto 0);     -- carry and zero bit from status byte
 
                rst_n     : in std_logic
        );
end vliwProc_jmpExec;
 
architecture behavior of vliwProc_jmpExec is
 
        signal en_n_s    : std_logic;
        signal jmpEn_n_s : std_logic;
        signal dst_s     : std_logic_vector(10 downto 0);
 
begin
 
        jmpDst <= dst_s when rst_n = '1' else
                  (others => '0');
 
        jmpEn_n <= jmpEn_n_s;
 
        enable_p : process(rst_n, esb(2))
        begin
                if (rst_n = '0') then
                        jmpEn_n_s <= '1';
                else
                        if (esb(2)'event and esb(2) = '1') then
                                if (en_n = '0' and en_n_s = '0') then
                                        jmpEn_n_s <= '0';
                                else
                                        jmpEn_n_s <= '1';
                                end if;
                        end if;
                end if;
        end process;
 
        -- take data from the inputs, is available during state1 only 
        -------------------------------------------------------------
        dst_p : process(rst_n, en_n)
        begin
                if (rst_n = '0') then
                        dst_s <= (others => '0');
                        en_n_s <= '1';
                else
                        if (en_n'event and en_n = '0') then
                                dst_s <= dst;
 
                                if (as = "00") then
                                        en_n_s <= '0';
                                elsif (as = "01" and cz(0) = '1') then
                                        en_n_s <= '0';
                                elsif (as = "10" and cz(1) = '1') then
                                        en_n_s <= '0';
                                elsif (as = "11" and cz(0) = '0') then
                                        en_n_s <= '0';
                                else
                                        en_n_s <= '1';
                                end if;
                        end if;
                end if;
        end process;
 
end behavior;

Line No.	Rev	Author	Line
1	2	steckol	`-----------------------------------------------------------------`
2			`-- Project: Aeternitas`
3			`-- Author: Oliver Stecklina <stecklina@ihp-microelectronics.com`
4			`-- Date: 24.10.2013`
5			`-- File: jmpExec.vhd`
6			`-- Design: AeternitasSWUR`
7			`-----------------------------------------------------------------`
8			`-- Description : This unit is the jump execution unit of the`
9			`-- embedded 8-bit VLIW processor.`
10			`-----------------------------------------------------------------`
11			`-- $Log$`
12			`-----------------------------------------------------------------`
13
14			`library ieee;`
15
16			`use ieee.std_logic_1164.all;`
17			`use ieee.std_logic_arith.all;`
18
19			`entity vliwProc_jmpExec is`
20			`port (`
21			`en_n : in std_logic;`
22
23			`esb : in std_logic_vector(3 downto 0);`
24
25			`dst : in std_logic_vector(10 downto 0);`
26			`as : in std_logic_vector(1 downto 0);`
27
28			`jmpDst : out std_logic_vector(10 downto 0);`
29			`jmpEn_n : out std_logic;`
30
31			`cz : in std_logic_vector(1 downto 0); -- carry and zero bit from status byte`
32
33			`rst_n : in std_logic`
34			`);`
35			`end vliwProc_jmpExec;`
36
37			`architecture behavior of vliwProc_jmpExec is`
38
39			`signal en_n_s : std_logic;`
40			`signal jmpEn_n_s : std_logic;`
41			`signal dst_s : std_logic_vector(10 downto 0);`
42
43			`begin`
44
45			`jmpDst <= dst_s when rst_n = '1' else`
46			`(others => '0');`
47
48			`jmpEn_n <= jmpEn_n_s;`
49
50			`enable_p : process(rst_n, esb(2))`
51			`begin`
52			`if (rst_n = '0') then`
53			`jmpEn_n_s <= '1';`
54			`else`
55			`if (esb(2)'event and esb(2) = '1') then`
56			`if (en_n = '0' and en_n_s = '0') then`
57			`jmpEn_n_s <= '0';`
58			`else`
59			`jmpEn_n_s <= '1';`
60			`end if;`
61			`end if;`
62			`end if;`
63			`end process;`
64
65			`-- take data from the inputs, is available during state1 only`
66			`-------------------------------------------------------------`
67			`dst_p : process(rst_n, en_n)`
68			`begin`
69			`if (rst_n = '0') then`
70			`dst_s <= (others => '0');`
71			`en_n_s <= '1';`
72			`else`
73			`if (en_n'event and en_n = '0') then`
74			`dst_s <= dst;`
75
76			`if (as = "00") then`
77			`en_n_s <= '0';`
78			`elsif (as = "01" and cz(0) = '1') then`
79			`en_n_s <= '0';`
80			`elsif (as = "10" and cz(1) = '1') then`
81			`en_n_s <= '0';`
82			`elsif (as = "11" and cz(0) = '0') then`
83			`en_n_s <= '0';`
84			`else`
85			`en_n_s <= '1';`
86			`end if;`
87			`end if;`
88			`end if;`
89			`end process;`
90
91			`end behavior;`

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[/] [tinyvliw8/] [trunk/] [src/] [vhdl/] [proc/] [jmpExec.vhd] - Blame information for rev 2