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[/] [tinyvliw8/] [trunk/] [src/] [vhdl/] [proc/] [loadStore.vhd] - Blame information for rev 2

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1 2 steckol 
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity vliwProc_loadStore is
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        port (
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                addr     : out std_logic_vector(7 downto 0);
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                dataOut  : out std_logic_vector(7 downto 0);
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                ioWr_n   : out std_logic;
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                ioEn_n   : out std_logic;
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                dataWr_n : out std_logic;
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                dataEn_n : out std_logic;
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                dataIn   : in std_logic_vector(7 downto 0);
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                ioIn     : in std_logic_vector(7 downto 0);
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                opCode   : in std_logic;
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                as       : in std_logic_vector(1 downto 0);
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                dstReg   : in std_logic_vector(2 downto 0);
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                src      : in std_logic_vector(7 downto 0);
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                cs_n     : in std_logic;
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                state    : in std_logic_vector(3 downto 0);
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                regOut   : out std_logic_vector(7 downto 0);
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                reg0     : in std_logic_vector(7 downto 0);
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                reg1     : in std_logic_vector(7 downto 0);
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                reg2     : in std_logic_vector(7 downto 0);
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                reg3     : in std_logic_vector(7 downto 0);
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                reg4     : in std_logic_vector(7 downto 0);
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                reg5     : in std_logic_vector(7 downto 0);
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                reg6     : in std_logic_vector(7 downto 0);
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                reg7     : in std_logic_vector(7 downto 0);
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                regSel   : out std_logic_vector(2 downto 0);
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                regEn_n  : out std_logic;
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                rst_n       : in std_logic
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        );
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end vliwProc_loadStore;
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architecture behavior of vliwProc_loadStore is
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        signal cntClk_s  : std_logic;
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        signal state23_s : std_logic;
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        signal as_s      : std_logic_vector(1 downto 0);
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        signal opcode_s  : std_logic;
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        signal dstReg_s  : std_logic_vector(2 downto 0);
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        signal src_s     : std_logic_vector(7 downto 0);
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        signal enable_s  : std_logic;
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        signal enable_evt_s  : std_logic;
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begin
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        reg_update: process(rst_n, cs_n)
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        begin
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                if (rst_n = '0') then
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                        as_s <= (others => '0');
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                        opcode_s <= '0';
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                        dstReg_s <= (others => '0');
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                        src_s <= (others => '0');
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                else
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                        if (cs_n'event and cs_n = '0') then
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                                as_s <= as;
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                                opcode_s <= opcode;
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                                dstReg_s <= dstReg;
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                                src_s <= src;
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                        end if;
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                end if;
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        end process;
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        addr <= src_s when enable_s = '1' and as_s(0) = '0' else
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                reg0  when enable_s = '1' and as_s(0) = '1' and src_s(2 downto 0) = "000" else
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                reg1  when enable_s = '1' and as_s(0) = '1' and src_s(2 downto 0) = "001" else
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                reg2  when enable_s = '1' and as_s(0) = '1' and src_s(2 downto 0) = "010" else
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                reg3  when enable_s = '1' and as_s(0) = '1' and src_s(2 downto 0) = "011" else
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                reg4  when enable_s = '1' and as_s(0) = '1' and src_s(2 downto 0) = "100" else
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                reg5  when enable_s = '1' and as_s(0) = '1' and src_s(2 downto 0) = "101" else
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                reg6  when enable_s = '1' and as_s(0) = '1' and src_s(2 downto 0) = "110" else
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                reg7  when enable_s = '1' and as_s(0) = '1' and src_s(2 downto 0) = "111" else
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                        (others => '0');
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        dataOut <= reg0 when enable_s = '1' and opCode_s = '1' and dstReg_s(2 downto 0) = "000" else
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                   reg1 when enable_s = '1' and opCode_s = '1' and dstReg_s(2 downto 0) = "001" else
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                   reg2 when enable_s = '1' and opCode_s = '1' and dstReg_s(2 downto 0) = "010" else
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                   reg3 when enable_s = '1' and opCode_s = '1' and dstReg_s(2 downto 0) = "011" else
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                   reg4 when enable_s = '1' and opCode_s = '1' and dstReg_s(2 downto 0) = "100" else
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                   reg5 when enable_s = '1' and opCode_s = '1' and dstReg_s(2 downto 0) = "101" else
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                   reg6 when enable_s = '1' and opCode_s = '1' and dstReg_s(2 downto 0) = "110" else
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                   reg7 when enable_s = '1' and opCode_s = '1' and dstReg_s(2 downto 0) = "111" else
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                   (others => '0');
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        cntClk_s <= '1' when state(0) = '1' or state(2) = '1' else
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                    '0';
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        stateGen_proc : process(rst_n, cntClk_s)
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        begin
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                if (rst_n = '0') then
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                        state23_s <= '1';
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                else
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                        if (cntClk_s'event and cntClk_s = '1') then
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                                state23_s <= not(state23_s);
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                        end if;
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                end if;
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        end process;
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        -- enable_evt_s <= state(2) and not(stalled_n_s);
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        enable_evt_s <= state(2);
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        enable_proc : process(rst_n, enable_evt_s)
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        begin
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                if (rst_n = '0') then
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                        enable_s <= '0';
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                else
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                        if (enable_evt_s'event and enable_evt_s = '1') then
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                                if (cs_n = '0') then
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                                        enable_s <= '1';
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                                else
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                                        enable_s <= '0';
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                                end if;
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                        end if;
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                end if;
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        end process;
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        -- store operation
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        ioEn_n   <= '0' when enable_s = '1' and as_s(1) = '1' and state23_s = '1' else
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                    '1';
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        dataEn_n <= '0' when enable_s = '1' and as_s(1) = '0' and state23_s = '1' else
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                    '1';
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        ioWr_n   <= '0' when enable_s = '1' and opCode_s = '1' and as_s(1) = '1' else
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               '1';
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        dataWr_n <= '0' when enable_s = '1' and opCode_s = '1' and as_s(1) = '0' else
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               '1';
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        regSel  <= dstReg_s when enable_s = '1' and opCode_s = '0' else
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                   (others => '0');
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        regOut  <= ioIn   when enable_s = '1' and opCode_s = '0' and as_s(1) = '1' else
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                   dataIn when enable_s = '1' and opCode_s = '0' and as_s(1) = '0' else
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                   (others => '0');
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        regEn_n <= '0'    when enable_s = '1' and opCode_s = '0' else
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                   '1';
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end behavior;

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