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[/] [tinyvliw8/] [trunk/] [src/] [vhdl/] [proc/] [pcReg.vhd] - Blame information for rev 2

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-----------------------------------------------------------------
-- Project: Aeternitas
-- Author:  Oliver Stecklina <stecklina@ihp-microelectronics.com
-- Date:    18.07.2013 
-- File:    pcReg.vhd
-- Design:  AeternitasSWUR
-----------------------------------------------------------------
-- Description : Program counter register.
-----------------------------------------------------------------
-- $Log$
-----------------------------------------------------------------
 
library ieee;
-- library lib;
 
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
-- use lib.defines.all;
 
entity vliwProc_pcReg is
        port (
           addrOut    : out std_logic_vector(10 downto 0);
           -- addrOut    : out std_logic_addr;
 
                state      : in std_logic_vector(3 downto 0);
                stalled_n  : in std_logic;
 
                ioAddr     : in std_logic_vector(1 downto 0);
                ioIn       : in std_logic_vector(7 downto 0);
                ioOut      : out std_logic_vector(7 downto 0);
                ioInEn_n   : in std_logic;
                ioInWr_n   : in std_logic;
 
                pcLoad_n   : out std_logic;
 
                jmpIn      : in std_logic_vector(10 downto 0);
                jmpInEn_n  : in std_logic;
 
                irq        : in std_logic;
                irqAddr    : in std_logic_vector(1 downto 0);
 
                rst_n      : in std_logic
        );
end vliwProc_pcReg;
 
architecture behavior of vliwProc_pcReg is
 
component gendelay
        generic (n: integer := 1);
        port (
                a_in    : in    std_logic;
                a_out   : out   std_logic
        );
end component;
 
        signal pcReg_s : std_logic_vector(10 downto 0);
        signal pcIrq_s : std_logic_vector(10 downto 0);
        signal pcInt_s : std_logic_vector(10 downto 0);
        signal pcUp_s  : std_logic_vector(2 downto 0);
 
        signal pcRegUpd_s : std_logic;
        signal pcLoad_n_s : std_logic;
 
        signal state0_s  : std_logic;
        -- signal state1_s  : std_logic;
        signal state3_s  : std_logic;
 
        signal delayedState3_s : std_logic;
 
begin
 
        state3Delay_i: gendelay
                generic map (n => 4)
                port map (
                        a_in    => state(3),
                        a_out   => delayedState3_s
                );
 
        state0_s <= state(0);
        -- state1_s <= state(1);
        state3_s <= state(3);
 
        update_pcInt: process(rst_n, state0_s)
                variable cnt_v : unsigned (10 downto 0);
        begin
                if (rst_n = '0') then
                        cnt_v := (others => '0');
                else
                        if (state0_s'event and state0_s = '1') then
                                cnt_v := unsigned(pcReg_s) + 1;
                        end if;
                end if;
 
                pcInt_s <= std_logic_vector(cnt_v);
        end process;
 
--      update_pcOut: process(rst_n, state1_s)
--      begin
--              if (rst_n = '0') then
--                      pcOut_s <= (others => '0');
--              else
--                      if (state1_s'event and state1_s = '1') then
--                              pcOut_s <= pcInt_s;
--                      end if;
--              end if;
--      end process;
--      
        update_pcUp: process(rst_n, state3_s)
        begin
                if (rst_n = '0') then
                        pcUp_s <= (others => '0');
                else
                        if (state3_s'event and state3_s = '1') then
                                if (ioInWr_n = '0' and ioAddr = "01") then
                                        pcUp_s <= ioIn(2 downto 0);
                                end if;
                        end if;
                end if;
        end process;
 
        update_pcReg: process(rst_n, pcRegUpd_s)
                variable pcReg_v : std_logic_vector(10 downto 0);
        begin
                if (rst_n = '0') then
                        pcReg_s <= (others => '0');
                        pcReg_v := (others => '0');
 
                        pcLoad_n_s <= '1';
                else
                        if (pcRegUpd_s'event and pcRegUpd_s = '1') then
                                pcLoad_n_s <= '1';
 
                                if (stalled_n = '1') then
                                        if (ioInWr_n = '0' and ioAddr = "00") then
                                                pcReg_v := pcUp_s & ioIn;
                                                pcLoad_n_s <= '0';
                                        elsif (jmpInEn_n = '0') then
                                                pcReg_v := jmpIn;
                                        else
                                                pcReg_v := pcInt_s;
                                        end if;
                                end if;
 
                                if (irq = '1') then
                                        pcIrq_s <= pcReg_v;
                                        pcReg_s <= "111111111" & irqAddr;
                                else
                                        pcReg_s <= pcReg_v;
                                end if;
                        end if;
                end if;
        end process;
 
        pcLoad_n   <= pcLoad_n_s when rst_n = '1' and delayedState3_s = '1' else
                      '1';
        pcRegUpd_s <= state3_s when rst_n = '1' and stalled_n = '1' else
                      '1' when rst_n = '1' and irq = '1' else
                                  '0';
 
        addrOut <= pcReg_s;
 
        ioOut <= pcInt_s(7 downto 0)            when (rst_n = '1' and ioInEn_n = '0' and ioAddr = "00") else
                 "00000" & pcInt_s(10 downto 8) when (rst_n = '1' and ioInEn_n = '0' and ioAddr = "01") else
                         pcIrq_s(7 downto 0)            when (rst_n = '1' and ioInEn_n = '0' and ioAddr = "10") else
                 "00000" & pcIrq_s(10 downto 8) when (rst_n = '1' and ioInEn_n = '0' and ioAddr = "11") else
                                (others => '0');
 
end behavior;

Line No.	Rev	Author	Line
1	2	steckol	`-----------------------------------------------------------------`
2			`-- Project: Aeternitas`
3			`-- Author: Oliver Stecklina <stecklina@ihp-microelectronics.com`
4			`-- Date: 18.07.2013`
5			`-- File: pcReg.vhd`
6			`-- Design: AeternitasSWUR`
7			`-----------------------------------------------------------------`
8			`-- Description : Program counter register.`
9			`-----------------------------------------------------------------`
10			`-- $Log$`
11			`-----------------------------------------------------------------`
12
13			`library ieee;`
14			`-- library lib;`
15
16			`use ieee.std_logic_1164.all;`
17			`use ieee.std_logic_arith.all;`
18
19			`-- use lib.defines.all;`
20
21			`entity vliwProc_pcReg is`
22			`port (`
23			`addrOut : out std_logic_vector(10 downto 0);`
24			`-- addrOut : out std_logic_addr;`
25
26			`state : in std_logic_vector(3 downto 0);`
27			`stalled_n : in std_logic;`
28
29			`ioAddr : in std_logic_vector(1 downto 0);`
30			`ioIn : in std_logic_vector(7 downto 0);`
31			`ioOut : out std_logic_vector(7 downto 0);`
32			`ioInEn_n : in std_logic;`
33			`ioInWr_n : in std_logic;`
34
35			`pcLoad_n : out std_logic;`
36
37			`jmpIn : in std_logic_vector(10 downto 0);`
38			`jmpInEn_n : in std_logic;`
39
40			`irq : in std_logic;`
41			`irqAddr : in std_logic_vector(1 downto 0);`
42
43			`rst_n : in std_logic`
44			`);`
45			`end vliwProc_pcReg;`
46
47			`architecture behavior of vliwProc_pcReg is`
48
49			`component gendelay`
50			`generic (n: integer := 1);`
51			`port (`
52			`a_in : in std_logic;`
53			`a_out : out std_logic`
54			`);`
55			`end component;`
56
57			`signal pcReg_s : std_logic_vector(10 downto 0);`
58			`signal pcIrq_s : std_logic_vector(10 downto 0);`
59			`signal pcInt_s : std_logic_vector(10 downto 0);`
60			`signal pcUp_s : std_logic_vector(2 downto 0);`
61
62			`signal pcRegUpd_s : std_logic;`
63			`signal pcLoad_n_s : std_logic;`
64
65			`signal state0_s : std_logic;`
66			`-- signal state1_s : std_logic;`
67			`signal state3_s : std_logic;`
68
69			`signal delayedState3_s : std_logic;`
70
71			`begin`
72
73			`state3Delay_i: gendelay`
74			`generic map (n => 4)`
75			`port map (`
76			`a_in => state(3),`
77			`a_out => delayedState3_s`
78			`);`
79
80			`state0_s <= state(0);`
81			`-- state1_s <= state(1);`
82			`state3_s <= state(3);`
83
84			`update_pcInt: process(rst_n, state0_s)`
85			`variable cnt_v : unsigned (10 downto 0);`
86			`begin`
87			`if (rst_n = '0') then`
88			`cnt_v := (others => '0');`
89			`else`
90			`if (state0_s'event and state0_s = '1') then`
91			`cnt_v := unsigned(pcReg_s) + 1;`
92			`end if;`
93			`end if;`
94
95			`pcInt_s <= std_logic_vector(cnt_v);`
96			`end process;`
97
98			`-- update_pcOut: process(rst_n, state1_s)`
99			`-- begin`
100			`-- if (rst_n = '0') then`
101			`-- pcOut_s <= (others => '0');`
102			`-- else`
103			`-- if (state1_s'event and state1_s = '1') then`
104			`-- pcOut_s <= pcInt_s;`
105			`-- end if;`
106			`-- end if;`
107			`-- end process;`
108			`--`
109			`update_pcUp: process(rst_n, state3_s)`
110			`begin`
111			`if (rst_n = '0') then`
112			`pcUp_s <= (others => '0');`
113			`else`
114			`if (state3_s'event and state3_s = '1') then`
115			`if (ioInWr_n = '0' and ioAddr = "01") then`
116			`pcUp_s <= ioIn(2 downto 0);`
117			`end if;`
118			`end if;`
119			`end if;`
120			`end process;`
121
122			`update_pcReg: process(rst_n, pcRegUpd_s)`
123			`variable pcReg_v : std_logic_vector(10 downto 0);`
124			`begin`
125			`if (rst_n = '0') then`
126			`pcReg_s <= (others => '0');`
127			`pcReg_v := (others => '0');`
128
129			`pcLoad_n_s <= '1';`
130			`else`
131			`if (pcRegUpd_s'event and pcRegUpd_s = '1') then`
132			`pcLoad_n_s <= '1';`
133
134			`if (stalled_n = '1') then`
135			`if (ioInWr_n = '0' and ioAddr = "00") then`
136			`pcReg_v := pcUp_s & ioIn;`
137			`pcLoad_n_s <= '0';`
138			`elsif (jmpInEn_n = '0') then`
139			`pcReg_v := jmpIn;`
140			`else`
141			`pcReg_v := pcInt_s;`
142			`end if;`
143			`end if;`
144
145			`if (irq = '1') then`
146			`pcIrq_s <= pcReg_v;`
147			`pcReg_s <= "111111111" & irqAddr;`
148			`else`
149			`pcReg_s <= pcReg_v;`
150			`end if;`
151			`end if;`
152			`end if;`
153			`end process;`
154
155			`pcLoad_n <= pcLoad_n_s when rst_n = '1' and delayedState3_s = '1' else`
156			`'1';`
157			`pcRegUpd_s <= state3_s when rst_n = '1' and stalled_n = '1' else`
158			`'1' when rst_n = '1' and irq = '1' else`
159			`'0';`
160
161			`addrOut <= pcReg_s;`
162
163			`ioOut <= pcInt_s(7 downto 0) when (rst_n = '1' and ioInEn_n = '0' and ioAddr = "00") else`
164			`"00000" & pcInt_s(10 downto 8) when (rst_n = '1' and ioInEn_n = '0' and ioAddr = "01") else`
165			`pcIrq_s(7 downto 0) when (rst_n = '1' and ioInEn_n = '0' and ioAddr = "10") else`
166			`"00000" & pcIrq_s(10 downto 8) when (rst_n = '1' and ioInEn_n = '0' and ioAddr = "11") else`
167			`(others => '0');`
168
169			`end behavior;`

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[/] [tinyvliw8/] [trunk/] [src/] [vhdl/] [proc/] [pcReg.vhd] - Blame information for rev 2