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steckol |
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity vliwProc_regSet is
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port (
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state : in std_logic_vector(3 downto 0);
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reg0 : out std_logic_vector(7 downto 0);
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reg1 : out std_logic_vector(7 downto 0);
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reg2 : out std_logic_vector(7 downto 0);
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reg3 : out std_logic_vector(7 downto 0);
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reg4 : out std_logic_vector(7 downto 0);
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reg5 : out std_logic_vector(7 downto 0);
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reg6 : out std_logic_vector(7 downto 0);
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reg7 : out std_logic_vector(7 downto 0);
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irqEn : in std_logic;
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aluDataIn : in std_logic_vector(7 downto 0);
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aluRegSel : in std_logic_vector(2 downto 0);
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aluRegEn_n : in std_logic;
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ldstDataIn : in std_logic_vector(7 downto 0);
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ldstRegSel : in std_logic_vector(2 downto 0);
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ldstRegEn_n : in std_logic;
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rst_n : in std_logic
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);
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end vliwProc_regSet;
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architecture behavior of vliwProc_regSet is
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signal irqReg0_s : std_logic_vector(7 downto 0);
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signal irqReg1_s : std_logic_vector(7 downto 0);
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signal irqReg2_s : std_logic_vector(7 downto 0);
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signal irqReg3_s : std_logic_vector(7 downto 0);
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signal reg0_s : std_logic_vector(7 downto 0);
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signal reg1_s : std_logic_vector(7 downto 0);
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signal reg2_s : std_logic_vector(7 downto 0);
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signal reg3_s : std_logic_vector(7 downto 0);
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signal reg4_s : std_logic_vector(7 downto 0);
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signal reg5_s : std_logic_vector(7 downto 0);
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signal reg6_s : std_logic_vector(7 downto 0);
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signal reg7_s : std_logic_vector(7 downto 0);
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signal aluRegData_s : std_logic_vector(7 downto 0);
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signal aluRegSel_s : std_logic_vector(2 downto 0);
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signal aluCommit_s : std_logic;
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signal ldstRegData_s : std_logic_vector(7 downto 0);
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signal ldstRegSel_s : std_logic_vector(2 downto 0);
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signal ldstCommit_s : std_logic;
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signal irqEn_s : std_logic;
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BEGIN
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alu_commit_p : process(rst_n, state(2))
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begin
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if (rst_n = '0') then
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aluRegData_s <= (others => '0');
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aluRegSel_s <= (others => '0');
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aluCommit_s <= '0';
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else
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if (state(3)'event and state(3) = '1') then
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if (aluRegEn_n <= '0') then
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aluRegSel_s <= aluRegSel;
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aluRegData_s <= aluDataIn;
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aluCommit_s <= '1';
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else
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aluCommit_s <= '0';
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end if;
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end if;
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end if;
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end process;
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ldst_commit_p : process(rst_n, state(3))
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begin
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if (rst_n = '0') then
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ldstRegData_s <= (others => '0');
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ldstRegSel_s <= (others => '0');
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ldstCommit_s <= '0';
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else
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if (state(3)'event and state(3) = '1') then
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if (ldstRegEn_n = '0') then
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ldstRegSel_s <= ldstRegSel;
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ldstRegData_s <= ldstDataIn;
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ldstCommit_s <= '1';
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else
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ldstCommit_s <= '0';
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end if;
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end if;
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end if;
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end process;
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commit_p: process(rst_n, state(3))
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begin
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if (rst_n = '0') then
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irqReg0_s <= (others => '0');
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irqReg1_s <= (others => '0');
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irqReg2_s <= (others => '0');
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irqReg3_s <= (others => '0');
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reg0_s <= (others => '0');
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reg1_s <= (others => '0');
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reg2_s <= (others => '0');
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reg3_s <= (others => '0');
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reg4_s <= (others => '0');
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reg5_s <= (others => '0');
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reg6_s <= (others => '0');
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reg7_s <= (others => '0');
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elsif (state(3)'event and state(3) = '0') then
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if (aluCommit_s = '1') then
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if (aluRegSel_s = "000") then
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if (irqEn_s = '1') then
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irqReg0_s <= aluRegData_s;
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else
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reg0_s <= aluRegData_s;
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end if;
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elsif (aluRegSel_s = "001") then
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if (irqEn_s = '1') then
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irqReg1_s <= aluRegData_s;
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else
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reg1_s <= aluRegData_s;
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end if;
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elsif (aluRegSel_s = "010") then
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if (irqEn_s = '1') then
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irqReg2_s <= aluRegData_s;
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else
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reg2_s <= aluRegData_s;
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end if;
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elsif (aluRegSel_s = "011") then
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if (irqEn_s = '1') then
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irqReg3_s <= aluRegData_s;
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else
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reg3_s <= aluRegData_s;
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end if;
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elsif (aluRegSel_s = "100") then
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reg4_s <= aluRegData_s;
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elsif (aluRegSel_s = "101") then
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reg5_s <= aluRegData_s;
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elsif (aluRegSel_s = "110") then
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reg6_s <= aluRegData_s;
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elsif (aluRegSel_s = "111") then
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reg7_s <= aluRegData_s;
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end if;
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end if;
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if (ldstCommit_s = '1') then
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if (ldstRegSel_s = "000") then
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if (irqEn_s = '1') then
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irqReg0_s <= ldstRegData_s;
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else
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reg0_s <= ldstRegData_s;
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end if;
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elsif (ldstRegSel_s = "001") then
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if (irqEn_s = '1') then
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irqReg1_s <= ldstRegData_s;
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else
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reg1_s <= ldstRegData_s;
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end if;
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elsif (ldstRegSel_s = "010") then
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if (irqEn_s = '1') then
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irqReg2_s <= ldstRegData_s;
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else
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reg2_s <= ldstRegData_s;
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end if;
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elsif (ldstRegSel_s = "011") then
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if (irqEn_s = '1') then
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irqReg3_s <= ldstRegData_s;
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else
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reg3_s <= ldstRegData_s;
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end if;
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elsif (ldstRegSel_s = "100") then
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reg4_s <= ldstRegData_s;
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elsif (ldstRegSel_s = "101") then
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reg5_s <= ldstRegData_s;
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elsif (ldstRegSel_s = "110") then
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reg6_s <= ldstRegData_s;
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elsif (ldstRegSel_s = "111") then
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reg7_s <= ldstRegData_s;
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end if;
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end if;
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end if;
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end process;
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-- commit interrupt signal after commit of registers, but before access of
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-- functional units
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irqEn_proc: process(rst_n, state(1))
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begin
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if (rst_n = '0') then
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irqEn_s <= '0';
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else
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if (state(1)'event and state(1) = '0') then
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irqEn_s <= irqEn;
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end if;
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end if;
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end process;
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-- output including alu fast forward
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reg0 <= irqReg0_s when irqEn_s = '1' else
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reg0_s;
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reg1 <= irqReg1_s when irqEn_s = '1' else
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reg1_s;
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reg2 <= irqReg2_s when irqEn_s = '1' else
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reg2_s;
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reg3 <= irqReg3_s when irqEn_s = '1' else
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reg3_s;
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reg4 <= reg4_s;
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reg5 <= reg5_s;
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reg6 <= reg6_s;
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reg7 <= reg7_s;
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END behavior;
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