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1 2 steckol 
-----------------------------------------------------------------
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-- Project: Aeternitas
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-- Author:  Oliver Stecklina <stecklina@ihp-microelectronics.com
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-- Date:    11.11.2013
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-- File:    statusReg.vhd
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-- Design:  AeternitasSWUR
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-----------------------------------------------------------------
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-- Description : Status register.
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-----------------------------------------------------------------
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-- $Log$
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-----------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity vliwProc_statusReg is
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        port (
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                state      : in std_logic_vector(3 downto 0);
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                iretEn_n   : in std_logic;
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                ioEn_n     : in std_logic;
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                irqEn      : in std_logic;
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                flagsEn_n  : in std_logic;
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                flagsIn    : in std_logic_vector(1 downto 0);       -- carry | zero
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                dataIn     : in  std_logic_vector(7 downto 0);
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                dataOut    : out std_logic_vector(7 downto 0);
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                rst_n      : in std_logic
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        );
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end vliwProc_statusReg;
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architecture behavior of vliwProc_statusReg is
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        signal rst_n_s      : std_logic;
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        -- signal statusReg_s  : std_logic_vector(2 downto 0);
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        signal stallEn_s    : std_logic;
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        signal stallEvt_s   : std_logic;
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        signal irqEn_s      : std_logic;
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        signal irqEvt_s     : std_logic;
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        signal ieEn_s       : std_logic;
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        signal flags_s      : std_logic_vector(1 downto 0);
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        signal flagsIInt_s  : std_logic_vector(1 downto 0);
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        signal state2_s     : std_logic;
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begin
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        rst_n_s <= rst_n;
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        state2_s <= state(2);
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   -----------------------------------------------------------------------------
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        --
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        -- setting in-interrupt flag, switches to
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        --      '1', when an irq ack occures - falling edge on irqEn_n
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        --      '0', when pc is loaded by load/store unit - falling edge on iretEn_n
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        --
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   -----------------------------------------------------------------------------
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        irqEn_proc : process(rst_n_s, irqEvt_s)
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        begin
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                if (rst_n_s = '0') then
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                        irqEn_s <= '0';
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                else
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                        if (irqEvt_s'event and irqEvt_s = '1') then
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                                if (irqEn = '1') then
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                                        irqEn_s <= '1';
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                                elsif (iretEn_n = '0') then
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                                        irqEn_s <= '0';
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                                end if;
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                        end if;
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                end if;
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        end process;
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        irqEvt_s <= irqEn xor not(iretEn_n);
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   -----------------------------------------------------------------------------
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        --
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        -- setting processor stall, switches to
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        --      '1', when a '1' is loaded via dataIn(7) - falling edge on ioEn_n
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        --      '0', when an interrupt occures - falling edge on irqEn_n
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        --
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   -----------------------------------------------------------------------------
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        stallEn_proc : process(rst_n_s, stallEvt_s)
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        begin
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                if (rst_n_s = '0') then
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                        stallEn_s <= '0';
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                else
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                        if (stallEvt_s'event and stallEvt_s = '1') then
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                                if (irqEn = '1') then
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                                        stallEn_s <= '0';
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                                elsif (ioEn_n = '0') then
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                                        stallEn_s <= dataIn(7);
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                                end if;
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                        end if;
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                end if;
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        end process;
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        stallEvt_s <= (not(ioEn_n) and not(state2_s)) xor irqEn;
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        ieEn_proc : process(rst_n_s, ioEn_n)
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        begin
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                if (rst_n_s = '0') then
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                        ieEn_s <= '0';
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                else
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                        if (ioEn_n'event and ioEn_n = '0') then
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                                ieEn_s <= dataIn(3);
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                        end if;
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                end if;
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        end process;
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        flagsEn_proc : process(rst_n_s, state(3))
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        begin
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                if (rst_n_s = '0') then
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                        flags_s     <= (others => '0');
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                        flagsIInt_s <= (others => '0');
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                else
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                        if (state(3)'event and state(3) = '1') then
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                                if (irqEn_s = '0') then
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                                        if (flagsEn_n = '0') then
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                                                flags_s <= flagsIn;
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                                        else
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                                                flags_s <= (others => '0');
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                                        end if;
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                                else
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                                        if (flagsEn_n = '0') then
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                                                flagsIInt_s <= flagsIn;
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                                        else
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                                                flagsIInt_s <= (others => '0');
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                                        end if;
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                                end if;
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                        end if;
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                end if;
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        end process;
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   -----------------------------------------------------------------------------
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        --
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        -- Status register
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        --   stall | 0 | carry | zero | ie | 0 | 0 | iint
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        --
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   -----------------------------------------------------------------------------
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        dataOut <= stallEn_s & "0" & flags_s & ieEn_s & "00" & '0'     when rst_n_s = '1' and irqEn_s = '0' else
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                   stallEn_s & "0" & flagsIInt_s & ieEn_s & "00" & '1' when rst_n_s = '1' and irqEn_s = '1' else
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                                  (others => '0');
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end behavior;

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