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-----------------------------------------------------------------

-- Project: Aeternitas

-- Author:  Oliver Stecklina <stecklina@ihp-microelectronics.com>

-- Date:    10.03.2015 

-- File:    rstCtrl.vhd

-- Design:  AeternitasSWUR

-----------------------------------------------------------------

-- Description : This unit is a reset control to synchronize

--               reset and clock signal.

--

--     Copyright (c) 2015 IHP Microelectronics GmbH

--     All rights reserved

-----------------------------------------------------------------

-- $Log$

-----------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

entity rstCtrl is

        port (

                rstIn_n  : in std_logic;

                clk      : in std_logic;

                pol      : in std_logic;  -- polarity of 1st clock edge (0 => falling)

                rstOut_n : out std_logic

        );

end rstCtrl;

architecture behav of rstCtrl is

component gendelay

        generic (n: integer := 1);

        port (

                a_in    : in    std_logic;

                a_out   : out   std_logic

        );

end component;

        signal rst_n_s : std_logic;

        signal clk_s   : std_logic;

begin

        sync_clkRst: process(clk_s)

        begin

                if clk_s'event and clk_s = '1' then

                        rst_n_s <= rstIn_n;

                end if;

        end process;

        clk_s <= clk      when pol = '0' else

                 not(clk);

        rst_delay_i: gendelay

        generic map (n => 1)

        port map (

                a_in    => rst_n_s,

                a_out   => rstOut_n

        );

end behav;