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[/] [tinyvliw8/] [trunk/] [src/] [vhdl/] [spiSlave.vhd] - Blame information for rev 2

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--
--      SPI slave module
 
LIBRARY IEEE;
USE     IEEE.STD_LOGIC_1164.ALL;
 
ENTITY spiSlave IS
        PORT (
                rst_n    : IN  STD_LOGIC;       -- asynchr. reset, low active
 
  -- SPI bus lines              
                sclk      : IN  STD_LOGIC;      -- clock signal
                cs        : IN  STD_LOGIC;      -- chip select, low active
                mosi      : IN  STD_LOGIC;      -- data in (from SPI master)
                miso      : OUT STD_LOGIC;      -- data out (to SPI master)
 
  -- connection to SPI_registers                
                addr      : OUT std_logic_vector(10 downto 0);   -- register address
                memSel    : out std_logic_vector(1 downto 0);   -- memory selection
 
                writeEn_n : OUT STD_LOGIC;                           -- write enable, low active
                readEn_n  : OUT STD_LOGIC;                      -- read enable, low active
                dataOut   : OUT std_logic_vector(31 downto 0);   -- data bus for writing register
                dataIn    : IN std_logic_vector(31 downto 0)    -- data bus for reading register
        );
END spiSlave;
 
ARCHITECTURE behav OF spiSlave IS
 
        signal count    : INTEGER RANGE 0 TO 32 + 16;       -- state counter
        signal size     : INTEGER RANGE 0 TO 1;             -- data size flag
 
        signal miso_s   : std_logic;
 
        signal rdEn_s   : std_logic;
        signal wrEn_s   : std_logic;
 
        signal wr_s     : std_logic;
        signal memSel_s : std_logic_vector(1 downto 0);
        signal addr_s    : std_logic_vector(10 downto 0);
        signal addrOut_s : std_logic_vector(10 downto 0);
 
        signal data_s   : std_logic_vector(31 downto 0);
 
BEGIN
 
        PROCESS (sclk, rst_n, cs)                       -- state counter
        BEGIN
                IF (rst_n = '0') THEN
                        count <= 0;
                        wr_s <= '0';
 
                        memSel_s  <= (others => '0');
                        addr_s    <= (others => '0');
                        addrOut_s <= (others => '0');
 
                        data_s   <= (others => '0');
                ELSE
                if (cs = '0') then
                                if (sclk'EVENT AND sclk='1') THEN       -- rising SCKL edge
                                        IF (size = 0 and count = (16 + 7)) or (size = 1 and count = (16 + 31)) THEN
                                                count <= 0;
                                        ELSE
                                                count <= count + 1;
                                        END IF;
 
                                        IF count < 8 then
                                                addr_s(7 downto 0) <= addr_s(6 downto 0) & mosi;
                                        elsif count > 7 and count < 11 THEN
                                                addr_s(10 downto 8) <= addr_s(9 downto 8) & mosi;
                                        elsif count = 12 THEN
                                                addrOut_s <= addr_s;
                                                memSel_s(1) <= mosi;
                                        elsif count = 13 THEN
                                                memSel_s(0) <= mosi;
                                        elsif count = 15 THEN
                                                wr_s <= mosi;
                                        elsif ((count > 15) and ((size = 0 and (count < (16 + 8))) or (size = 1 and (count < (16 + 32))))) then
                                                data_s <= data_s(30 downto 0) & mosi;
                                        END if;
                                END if;
                        else
                                count <= 0;
                        end if;
                END IF;
        END PROCESS;
 
        PROCESS (sclk, rst_n, cs)                       -- input SPI shift register
        BEGIN
                if (rst_n = '0' or cs = '1') then
                        size <= 0;
 
                        wrEn_s <= '0';
                        rdEn_s <= '0';
 
                        miso_s <= '0';
                else
                        IF sclk'EVENT AND sclk='0' THEN          -- falling SCKL edge
                                if (count = 0) then
                                        wrEn_s <= wr_s;                 -- generate write enable signal
                                elsif (count = 1) then
                                        wrEn_s <= '0';
                                        rdEn_s <= '0';
                                elsif (count = 15) then
                                        rdEn_s <= '1';
                                        if (memSel_s = "00") then
                                                size <= 1;
                                        end if;
                                elsif ((count > 15) and ((size = 0 and (count < (16 + 7))) or (size = 1 and (count < (16 + 31))))) then
                                        if (memSel_s = "00") then
                                                miso_s <= dataIn(47 - count);
                                        else
                                                miso_s <= dataIn(23 - count);
                                        end if;
                                END IF;
                        END IF;
                END IF;
        END PROCESS;
 
        miso      <= miso_s;
 
        readEn_n  <= not(rdEn_s) when cs = '0' else
                     '1';
        writeEn_n <= not(wrEn_s) when cs = '0' else
                     '1';
 
        memSel    <= memSel_s;
        addr      <= addrOut_s;
        dataOut   <= data_s;
 
END behav;

Line No.	Rev	Author	Line
1	2	steckol	`--`
2			`-- SPI slave module`
3
4			`LIBRARY IEEE;`
5			`USE IEEE.STD_LOGIC_1164.ALL;`
6
7			`ENTITY spiSlave IS`
8			`PORT (`
9			`rst_n : IN STD_LOGIC; -- asynchr. reset, low active`
10
11			`-- SPI bus lines`
12			`sclk : IN STD_LOGIC; -- clock signal`
13			`cs : IN STD_LOGIC; -- chip select, low active`
14			`mosi : IN STD_LOGIC; -- data in (from SPI master)`
15			`miso : OUT STD_LOGIC; -- data out (to SPI master)`
16
17			`-- connection to SPI_registers`
18			`addr : OUT std_logic_vector(10 downto 0); -- register address`
19			`memSel : out std_logic_vector(1 downto 0); -- memory selection`
20
21			`writeEn_n : OUT STD_LOGIC; -- write enable, low active`
22			`readEn_n : OUT STD_LOGIC; -- read enable, low active`
23			`dataOut : OUT std_logic_vector(31 downto 0); -- data bus for writing register`
24			`dataIn : IN std_logic_vector(31 downto 0) -- data bus for reading register`
25			`);`
26			`END spiSlave;`
27
28			`ARCHITECTURE behav OF spiSlave IS`
29
30			`signal count : INTEGER RANGE 0 TO 32 + 16; -- state counter`
31			`signal size : INTEGER RANGE 0 TO 1; -- data size flag`
32
33			`signal miso_s : std_logic;`
34
35			`signal rdEn_s : std_logic;`
36			`signal wrEn_s : std_logic;`
37
38			`signal wr_s : std_logic;`
39			`signal memSel_s : std_logic_vector(1 downto 0);`
40			`signal addr_s : std_logic_vector(10 downto 0);`
41			`signal addrOut_s : std_logic_vector(10 downto 0);`
42
43			`signal data_s : std_logic_vector(31 downto 0);`
44
45			`BEGIN`
46
47			`PROCESS (sclk, rst_n, cs) -- state counter`
48			`BEGIN`
49			`IF (rst_n = '0') THEN`
50			`count <= 0;`
51			`wr_s <= '0';`
52
53			`memSel_s <= (others => '0');`
54			`addr_s <= (others => '0');`
55			`addrOut_s <= (others => '0');`
56
57			`data_s <= (others => '0');`
58			`ELSE`
59			`if (cs = '0') then`
60			`if (sclk'EVENT AND sclk='1') THEN -- rising SCKL edge`
61			`IF (size = 0 and count = (16 + 7)) or (size = 1 and count = (16 + 31)) THEN`
62			`count <= 0;`
63			`ELSE`
64			`count <= count + 1;`
65			`END IF;`
66
67			`IF count < 8 then`
68			`addr_s(7 downto 0) <= addr_s(6 downto 0) & mosi;`
69			`elsif count > 7 and count < 11 THEN`
70			`addr_s(10 downto 8) <= addr_s(9 downto 8) & mosi;`
71			`elsif count = 12 THEN`
72			`addrOut_s <= addr_s;`
73			`memSel_s(1) <= mosi;`
74			`elsif count = 13 THEN`
75			`memSel_s(0) <= mosi;`
76			`elsif count = 15 THEN`
77			`wr_s <= mosi;`
78			`elsif ((count > 15) and ((size = 0 and (count < (16 + 8))) or (size = 1 and (count < (16 + 32))))) then`
79			`data_s <= data_s(30 downto 0) & mosi;`
80			`END if;`
81			`END if;`
82			`else`
83			`count <= 0;`
84			`end if;`
85			`END IF;`
86			`END PROCESS;`
87
88			`PROCESS (sclk, rst_n, cs) -- input SPI shift register`
89			`BEGIN`
90			`if (rst_n = '0' or cs = '1') then`
91			`size <= 0;`
92
93			`wrEn_s <= '0';`
94			`rdEn_s <= '0';`
95
96			`miso_s <= '0';`
97			`else`
98			`IF sclk'EVENT AND sclk='0' THEN -- falling SCKL edge`
99			`if (count = 0) then`
100			`wrEn_s <= wr_s; -- generate write enable signal`
101			`elsif (count = 1) then`
102			`wrEn_s <= '0';`
103			`rdEn_s <= '0';`
104			`elsif (count = 15) then`
105			`rdEn_s <= '1';`
106			`if (memSel_s = "00") then`
107			`size <= 1;`
108			`end if;`
109			`elsif ((count > 15) and ((size = 0 and (count < (16 + 7))) or (size = 1 and (count < (16 + 31))))) then`
110			`if (memSel_s = "00") then`
111			`miso_s <= dataIn(47 - count);`
112			`else`
113			`miso_s <= dataIn(23 - count);`
114			`end if;`
115			`END IF;`
116			`END IF;`
117			`END IF;`
118			`END PROCESS;`
119
120			`miso <= miso_s;`
121
122			`readEn_n <= not(rdEn_s) when cs = '0' else`
123			`'1';`
124			`writeEn_n <= not(wrEn_s) when cs = '0' else`
125			`'1';`
126
127			`memSel <= memSel_s;`
128			`addr <= addrOut_s;`
129			`dataOut <= data_s;`
130
131			`END behav;`

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[/] [tinyvliw8/] [trunk/] [src/] [vhdl/] [spiSlave.vhd] - Blame information for rev 2