Subversion Repositories tinyvliw8

-------------------------------------------------------------------------------

--

-- Design:  tinyVLIW8 soft-core processor

-- Author:  Oliver Stecklina <stecklina@ihp-microelectronics.com>

-- Date:    24.10.2013 

-- File:    sysArch.vhd

--

-------------------------------------------------------------------------------

--

-- Description : TinyVLIW8 system architecture includes processor core and

--               GPIO, timer, and SPI periperals

--

-------------------------------------------------------------------------------

--

--    Copyright (C) 2015 IHP GmbH, Frankfurt (Oder), Germany

--

-- This code is free software. It is licensed under the EUPL, Version 1.1

-- or - as soon they will be approved by the European Commission - subsequent

-- versions of the EUPL (the "License").

-- You may redistribute this code and/or modify it under the terms of this

-- License.

-- You may not use this work except in compliance with the License.

-- You may obtain a copy of the License at:

--

-- http://joinup.ec.europa.eu/software/page/eupl/licence-eupl

--

-- Unless required by applicable law or agreed to in writing, software

-- distributed under the License is distributed on an "AS IS" basis,

-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

-- See the License for the specific language governing permissions and

-- limitations under the License.

--

-------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

entity sysArch is

        port (

                -- clock input

                clk           : in std_logic;

                -- instruction bus

                instMemAddr   : out std_logic_vector(10 downto 0);

                instMemDataIn : in  std_logic_vector(31 downto 0);

                instMemEn_n   : out std_logic;

                -- data bus

                dataMemAddr    : out std_logic_vector(7 downto 0);

                dataMemDataIn  : in  std_logic_vector(7 downto 0);

                dataMemDataOut : out std_logic_vector(7 downto 0);

                dataMemEn_n    : out std_logic;

                dataMemWr_n    : out std_logic;

                ioAddr    : out std_logic_vector(7 downto 0);

                ioDataIn  : in  std_logic_vector(7 downto 0);

                ioDataOut : out std_logic_vector(7 downto 0);

                ioWrEn_n  : out std_logic;

                ioRdEn_n  : out std_logic;

                -- external interrupt handling

                irqLine        : in  std_logic;

                irqLineAck     : out std_logic;

                -- general purpose IO

                gpio_in  : in  std_logic_vector(7 downto 0);

                gpio_out : out  std_logic_vector(7 downto 0);

                gpio_dir : out  std_logic_vector(7 downto 0);

                spi_clk  : OUT STD_LOGIC;       -- SPI clock

                spi_cs   : OUT STD_LOGIC;       -- SPI slave select, active level configurable

                spi_mosi : OUT STD_LOGIC;       -- SPI master output, slave input

                spi_miso : IN  STD_LOGIC;       -- SPI master input, slave output

                stall_n      : in std_logic;

                stalled_n    : out std_logic;

                -- reset input

                rst_n        : in std_logic

        );

end sysArch;

architecture behavior of sysArch is

component SPImaster IS

        PORT (

                inclk : IN  STD_LOGIC;  -- system clock

                rst_n : IN  STD_LOGIC;  -- synchr. system reset, high active

                -- processor interface

                we_n : IN  STD_LOGIC;   -- write enable, high active

                re_n : IN  STD_LOGIC;   -- read  enable, high active

                addr : IN  STD_LOGIC_VECTOR(1 DOWNTO 0); -- address from processor

                din  : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);-- data from processor

                dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-- async. data to processor

                intr : OUT STD_LOGIC;   -- interrupt to processor, high active

                intra : IN STD_LOGIC;   -- interrupt to processor, high active

                -- SPI interface

                SCK  : OUT STD_LOGIC;   -- SPI clock

                SS   : OUT STD_LOGIC;   -- SPI slave select, active level configurable

                MOSI : OUT STD_LOGIC;   -- SPI master output, slave input

                MISO : IN  STD_LOGIC    -- SPI master input, slave output

        );

END component;

component vliwProc

        port (

                clk            : in  std_logic;

                instMemAddr    : out std_logic_vector(10 downto 0);

                instMemDataIn  : in  std_logic_vector(31 downto 0);

                instMemEn_n    : out std_logic;

                ioMemAddr    : out std_logic_vector(7 downto 0);

                ioMemDataOut : out std_logic_vector(7 downto 0);

                ioMemDataIn  : in  std_logic_vector(7 downto 0);

                ioMemWr_n    : out std_logic;

                ioMemEn_n    : out std_logic;

                -- IO bus

                dataMemAddr    : out std_logic_vector(7 downto 0);

                dataMemDataOut : out std_logic_vector(7 downto 0);

                dataMemDataIn  : in  std_logic_vector(7 downto 0);

                dataMemWr_n    : out std_logic;

                dataMemEn_n    : out std_logic;

                irqLine        : in  std_logic_vector(4 downto 0);

                irqLineAck     : out std_logic_vector(4 downto 0);

                stall_n      : in std_logic;

                stalled_n    : out std_logic;

                rst_n        : in std_logic

        );

end component;

component ioport

        port (

                cs_n    : IN  STD_LOGIC;                        -- chip select signal

                clk     : IN  STD_LOGIC;

                -- memory interface

                mdbwr_n : IN  STD_LOGIC;                    -- write enable signal    

                mdb_i   : IN  STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from data bus

                mdb_o   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to data bus    

                mab     : IN  STD_LOGIC_VECTOR(2 downto 0);      -- address registers 

                irq     : out std_logic;

                irqAck  : in std_logic;

                -- port interface

                PnIN    : IN  STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from pad (gpio in)

                PnOUT   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to pad (gpio out)

                PnOEN   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- port direction (low active)

                rst_n   : IN STD_LOGIC

        );

end component;

component timer

        PORT (

                clk       : in std_logic;

                addr      : in std_logic_vector(2 downto 0);        -- register address

                writeEn_n : in  STD_LOGIC;                           -- write enable, low active

                readEn_n  : in  STD_LOGIC;                      -- read enable, low active

                dataOut   : OUT std_logic_vector(7 downto 0);    -- data bus for writing register

                dataIn    : IN std_logic_vector(7 downto 0);    -- data bus for reading register

                irq       : out std_logic;

                irq_ack   : in  std_logic;

                rst_n     : IN  STD_LOGIC                        -- asynchr. reset, low active

        );

end component;

        signal clk_s   : std_logic;

        signal instAddr_s    : std_logic_vector(10 downto 0);

        signal instDataIn_s  : std_logic_vector(31 downto 0);

        signal instEn_n_s    : std_logic;

        -- IO bus

        signal ioAddr_s    : std_logic_vector(7 downto 0);

        signal ioDataOut_s : std_logic_vector(7 downto 0);

        signal ioDataIn_s  : std_logic_vector(7 downto 0);

        signal ioEn_n_s    : std_logic;

        signal ioWr_n_s    : std_logic;

        -- GPIO signals

        signal ioDataGpio_s : std_logic_vector(7 downto 0);

        signal ioPortEn_n_s : std_logic;

        signal ioPortIrq_s  : std_logic;

        --Fir Data bus

        signal dataAddr_s   : std_logic_vector(7 downto 0);

        signal dataOut_s    : std_logic_vector(7 downto 0);

        signal dataIn_s     : std_logic_vector(7 downto 0);

        signal dataWr_n_s   : std_logic;

        signal dataEn_n_s   : std_logic;

        signal rst_n_s     : std_logic;

        signal stall_n_s   : std_logic;

        signal stalled_n_s : std_logic;

        signal irqLine_s        : std_logic_vector(4 downto 0);

        signal irqLineAck_s     : std_logic_vector(4 downto 0);

        -- timer signals 

        signal timer_irq_s      : std_logic;

        signal ioTimerEn_n_s    : std_logic;

        signal ioTimerDataOut_s : std_logic_vector(7 downto 0);

        -- spi master signals

        signal ioSpiEn_n_s : std_logic;

        signal spiIrq_s    : std_logic;

        signal ioDataSpi_s : std_logic_vector(7 downto 0);

        -- external io interface

        signal ioDataExt_s : std_logic_vector(7 downto 0);

        signal ioExtEn_n_s : std_logic;

begin

        clk_s <= clk;

        rst_n_s <= rst_n;

        stall_n_s <= stall_n;

        stalled_n <= stalled_n_s;

        irqLineAck <= irqLineAck_s(0);   -- export IRQ 0

        irqLine_s <= ioPortIrq_s & timer_irq_s & '0' & spiIrq_s & irqLine;

        instMemAddr  <= instAddr_s;

        instDataIn_s <= instMemDataIn;

        instMemEn_n  <= instEn_n_s;

        dataMemAddr    <= dataAddr_s;

        dataIn_s       <= dataMemDataIn;

        dataMemDataOut <= dataOut_s;

        dataMemEn_n    <= dataEn_n_s;

        dataMemWr_n    <= dataWr_n_s;

        ioDataIn_s <= ioDataGpio_s     when ioPortEn_n_s = '0' else

                      ioTimerDataOut_s when ioTimerEn_n_s = '0' else

                                  ioDataSpi_s      when ioSpiEn_n_s = '0' else

                                  ioDataExt_s;

        vliwProc_i : vliwProc

        port map (

                clk            => clk_s,

                instMemAddr    => instAddr_s,

                instMemDataIn  => instDataIn_s,

                instMemEn_n    => instEn_n_s,

                ioMemAddr      => ioAddr_s,

                ioMemDataOut   => ioDataOut_s,

                ioMemDataIn    => ioDataIn_s,

                ioMemEn_n      => ioEn_n_s,

                ioMemWr_n      => ioWr_n_s,

                dataMemAddr    => dataAddr_s,

                dataMemDataOut => dataOut_s,

                dataMemDataIn  => dataIn_s,

                dataMemEn_n    => dataEn_n_s,

                dataMemWr_n    => dataWr_n_s,

                irqLine        => irqLine_s,

                irqLineAck     => irqLineAck_s,

                stall_n        => stall_n_s,

                stalled_n      => stalled_n_s,

                rst_n          => rst_n_s

        );

        ioSpiEn_n_s <= ioEn_n_s when ioAddr_s(7 downto 2) = "000101" else

                       '1';

        spiMaster_i : SPImaster

        port map (

                inclk => clk_s,

                rst_n => rst_n_s,

                we_n => ioWr_n_s,

                re_n => ioSpiEn_n_s,

                addr => ioAddr_s(1 downto 0),

                din  => ioDataOut_s,

                dout => ioDataSpi_s,

                intr  => spiIrq_s,

                intra => irqLineAck_s(1),

                SCK  => spi_clk,

                SS   => spi_cs,

                MOSI => spi_mosi,

                MISO => spi_miso

        );

        ioPortEn_n_s <= ioEn_n_s when ioAddr_s(7 downto 3) = "00100" else

                        '1';

        ioport_i : ioport

        port map (

                cs_n => ioPortEn_n_s,

                clk  => clk_s,

                mdbwr_n => ioWr_n_s,

                mdb_i   => ioDataOut_s,

                mdb_o   => ioDataGpio_s,

                mab     => ioAddr_s(2 downto 0),

                irq    => ioPortIrq_s,

                irqAck => irqLineAck_s(4),

                -- port interface

                PnIN  => gpio_in,

                PnOUT => gpio_out,

                PnOEN => gpio_dir,

                rst_n => rst_n_s

        );

        ioTimerEn_n_s <= ioEn_n_s when ioAddr_s(7 downto 3) = "00101" else

                         '1';

        timer_i : timer

        port map (

                clk       => clk_s,

                addr      => ioAddr_s(2 downto 0),

                writeEn_n => ioWr_n_s,

                readEn_n  => ioTimerEn_n_s,

                dataOut   => ioTimerDataOut_s,

                dataIn    => ioDataOut_s,

                irq       => timer_irq_s,

                irq_ack   => irqLineAck_s(3),

                rst_n     => rst_n_s

        );

        -- external io interface

        ioAddr      <= ioAddr_s;

        ioDataOut   <= ioDataOut_s;

        ioDataExt_s <= ioDataIn;

        ioRdEn_n    <= ioEn_n_s;

        ioWrEn_n    <= ioWr_n_s;

end behavior;