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-----------------------------------------------------------------
--
-- Design:  tinyVLIW8 soft-core processor
-- Author:  Oliver Stecklina <stecklina@ihp-microelectronics.com>
-- Date:    27.05.2015 
-- File:    timer.vhd
--
-----------------------------------------------------------------
--
-- Description : 16-bit timer module. The timer provides two
--      internal timer modules.
--
-----------------------------------------------------------------
--
--    Copyright (C) 2015 IHP GmbH, Frankfurt (Oder), Germany
--
-- This code is free software. It is licensed under the EUPL, Version 1.1
-- or - as soon they will be approved by the European Commission - subsequent
-- versions of the EUPL (the "License").
-- You may redistribute this code and/or modify it under the terms of this
-- License.
-- You may not use this work except in compliance with the License.
-- You may obtain a copy of the License at:
--
-- http://joinup.ec.europa.eu/software/page/eupl/licence-eupl
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" basis,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-----------------------------------------------------------------
 
LIBRARY IEEE;
 
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
 
ENTITY timer IS
        PORT (
                clk       : in std_logic;
 
                addr      : in std_logic_vector(2 downto 0);      -- register address
 
                writeEn_n : in  STD_LOGIC;                         -- write enable, low active
                readEn_n  : in  STD_LOGIC;                    -- read enable, low active
 
                dataOut   : OUT std_logic_vector(7 downto 0); -- data bus for writing register
                dataIn    : IN std_logic_vector(7 downto 0);  -- data bus for reading register
 
                irq       : out std_logic;
                irq_ack   : in  std_logic;
 
                rst_n     : IN  STD_LOGIC                -- asynchr. reset, low active
        );
END timer;
 
ARCHITECTURE behav OF timer IS
 
component clock_divider
        generic (n: integer := 2);
        PORT (
                inclk     : in  std_logic;
                outclk    : out std_logic;
 
                div       : in std_logic_vector((n - 1) downto 0);
                en        : IN std_logic
        );
END component;
 
component gendelay
        generic (n: integer := 1);
        port (
                a_in    : in    std_logic;
                a_out   : out   std_logic
        );
end component;
 
        signal clk_s      : std_logic;
        signal rst_n_s    : std_logic;
 
        signal cnt_reg    : std_logic_vector(15 downto 0);       -- state counter
        signal ifg_reg    : std_logic_vector(1 downto 0);
 
        signal ccr0       : std_logic_vector(15 downto 0);
        signal ccr1       : std_logic_vector(15 downto 0);
 
        -- | clr(7) | mode(6) | ie1(5) | ie0(4) | .. | div(2 .. 1) | en(0) |
        signal ctl_reg    : std_logic_vector(6 downto 0);
 
        signal irq_s      : std_logic;
        signal ifgEn_s    : std_logic;
        signal divclk_s   : std_logic;
 
        signal clrBit_s      : std_logic;
        signal clr_s      : std_logic;
 
BEGIN
 
        delay_i: gendelay
                generic map (n => 2)
                port map (
                        a_in    => clrBit_s,
                        a_out   => clr_s
                );
 
        rst_n_s <= rst_n;
        clk_s <= clk;
 
        clk_div_i : clock_divider
        generic map (n => 2)
        port map (
                inclk  => clk_s,
                outclk => divclk_s,
 
                div    => ctl_reg(2 downto 1),
                en     => ctl_reg(0)
        );
 
        tar_cnt : process (divclk_s, rst_n_s, clr_s)                    -- state counter
                variable cnt: unsigned (15 downto 0);
        BEGIN
                IF (rst_n_s = '0' or clr_s = '1') THEN
                         cnt := (others => '0');
                ELSE
                        if (divclk_s'EVENT AND divclk_s = '1') THEN     -- rising SCKL edge                             
                                IF (ctl_reg(6) = '0' and cnt = cnt'high) or (ctl_reg(6) = '1' and cnt = unsigned(ccr0)) THEN
                                        cnt := (others => '0');
                                ELSE
                                        cnt := cnt + 1;
                                END IF;
                        END if;
                END IF;
 
                cnt_reg <= std_logic_vector(cnt);
        END PROCESS;
 
        irq_en : process(rst_n_s, clk_s)
        begin
                IF (rst_n_s = '0') THEN
                         irq_s <= '0';
                ELSE
                        if (clk_s'EVENT AND clk_s = '0') THEN    -- falling SCKL edge
                                if (irq_ack = '1') then
                                        irq_s <= '0';
                                else
                                        if ((ctl_reg(4) = '1' and cnt_reg = ccr0 and ifg_reg(0) = '0') or (ctl_reg(5) = '1' and cnt_reg = ccr1 and ifg_reg(1) = '0')) then
                                                irq_s <= '1';
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
 
        ifgEn_s <= irq_s or not(writeEn_n);
 
        ifg : process(rst_n_s, ifgEn_s)
        BEGIN
                IF (rst_n_s = '0') THEN
                         ifg_reg <= (others => '0');
                ELSE
                        if (ifgEn_s'event and ifgEn_s = '1') then
                                if (irq_s = '1') then
                                        if (ctl_reg(4) = '1' and cnt_reg = ccr0) then
                                                ifg_reg(0) <= '1';
                                        end if;
 
                                        if (ctl_reg(5) = '1' and cnt_reg = ccr1) then
                                                ifg_reg(1) <= '1';
                                        end if;
                                else
                                        if (readEn_n = '0' and writeEn_n = '0' and addr = "001") then
                                                ifg_reg <= ifg_reg and not(dataIn(1 downto 0));
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
 
        wr_reg : process(rst_n_s, readEn_n, writeEn_n)                  -- state counter
        BEGIN
                IF (rst_n_s = '0') THEN
                         ctl_reg <= (others => '0');
 
                         ccr0    <= (others => '0');
                         ccr1    <= (others => '0');
                ELSE
                        if (readEn_n = '0') then
                                if (writeEn_n'event and writeEn_n = '0') then
                                        CASE addr IS
                                                when "000" => ctl_reg           <= dataIn(6 downto 0);
                                                when "100" => ccr0(7 downto 0)  <= dataIn;
                                                when "101" => ccr0(15 downto 8) <= dataIn;
                                                when "110" => ccr1(7 downto 0)  <= dataIn;
                                                when "111" => ccr1(15 downto 8) <= dataIn;
                                                WHEN others => null;
                                        END CASE;
                                end if;
                        end if;
                end if;
        END PROCESS;
 
        clrBit_s <= '1' when dataIn(7) = '1' and readEn_n = '0' and addr = "000" and writeEn_n = '0' else
                    '0';
 
        dataOut <= '0' & ctl_reg                   when rst_n_s = '1' and readEn_n = '0' and addr = "000" else
                   "000000" & ifg_reg(1 downto 0)  when rst_n_s = '1' and readEn_n = '0' and addr = "001" else
                   cnt_reg(7 downto 0)             when rst_n_s = '1' and readEn_n = '0' and addr = "010" else
                   cnt_reg(15 downto 8)            when rst_n_s = '1' and readEn_n = '0' and addr = "011" else
                   ccr0(7 downto 0)                when rst_n_s = '1' and readEn_n = '0' and addr = "100" else
                   ccr0(15 downto 8)               when rst_n_s = '1' and readEn_n = '0' and addr = "101" else
                   ccr1(7 downto 0)                when rst_n_s = '1' and readEn_n = '0' and addr = "110" else
                   ccr1(15 downto 8)               when rst_n_s = '1' and readEn_n = '0' and addr = "111" else
                   (others => '0');
 
        irq <= irq_s when rst_n_s = '1' else
               '0';
 
END behav;
 

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[/] [tinyvliw8/] [trunk/] [src/] [vhdl/] [timer.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	steckol	`-----------------------------------------------------------------`
2			`--`
3			`-- Design: tinyVLIW8 soft-core processor`
4			`-- Author: Oliver Stecklina <stecklina@ihp-microelectronics.com>`
5			`-- Date: 27.05.2015`
6			`-- File: timer.vhd`
7			`--`
8			`-----------------------------------------------------------------`
9			`--`
10			`-- Description : 16-bit timer module. The timer provides two`
11			`-- internal timer modules.`
12			`--`
13			`-----------------------------------------------------------------`
14			`--`
15			`-- Copyright (C) 2015 IHP GmbH, Frankfurt (Oder), Germany`
16			`--`
17			`-- This code is free software. It is licensed under the EUPL, Version 1.1`
18			`-- or - as soon they will be approved by the European Commission - subsequent`
19			`-- versions of the EUPL (the "License").`
20			`-- You may redistribute this code and/or modify it under the terms of this`
21			`-- License.`
22			`-- You may not use this work except in compliance with the License.`
23			`-- You may obtain a copy of the License at:`
24			`--`
25			`-- http://joinup.ec.europa.eu/software/page/eupl/licence-eupl`
26			`--`
27			`-- Unless required by applicable law or agreed to in writing, software`
28			`-- distributed under the License is distributed on an "AS IS" basis,`
29			`-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.`
30			`-- See the License for the specific language governing permissions and`
31			`-- limitations under the License.`
32			`--`
33			`-----------------------------------------------------------------`
34
35			`LIBRARY IEEE;`
36
37			`USE IEEE.STD_LOGIC_1164.ALL;`
38			`use ieee.std_logic_arith.all;`
39
40			`ENTITY timer IS`
41			`PORT (`
42			`clk : in std_logic;`
43
44			`addr : in std_logic_vector(2 downto 0); -- register address`
45
46			`writeEn_n : in STD_LOGIC; -- write enable, low active`
47			`readEn_n : in STD_LOGIC; -- read enable, low active`
48
49			`dataOut : OUT std_logic_vector(7 downto 0); -- data bus for writing register`
50			`dataIn : IN std_logic_vector(7 downto 0); -- data bus for reading register`
51
52			`irq : out std_logic;`
53			`irq_ack : in std_logic;`
54
55			`rst_n : IN STD_LOGIC -- asynchr. reset, low active`
56			`);`
57			`END timer;`
58
59			`ARCHITECTURE behav OF timer IS`
60
61			`component clock_divider`
62			`generic (n: integer := 2);`
63			`PORT (`
64			`inclk : in std_logic;`
65			`outclk : out std_logic;`
66
67			`div : in std_logic_vector((n - 1) downto 0);`
68			`en : IN std_logic`
69			`);`
70			`END component;`
71
72			`component gendelay`
73			`generic (n: integer := 1);`
74			`port (`
75			`a_in : in std_logic;`
76			`a_out : out std_logic`
77			`);`
78			`end component;`
79
80			`signal clk_s : std_logic;`
81			`signal rst_n_s : std_logic;`
82
83			`signal cnt_reg : std_logic_vector(15 downto 0); -- state counter`
84			`signal ifg_reg : std_logic_vector(1 downto 0);`
85
86			`signal ccr0 : std_logic_vector(15 downto 0);`
87			`signal ccr1 : std_logic_vector(15 downto 0);`
88
89			`-- \| clr(7) \| mode(6) \| ie1(5) \| ie0(4) \| .. \| div(2 .. 1) \| en(0) \|`
90			`signal ctl_reg : std_logic_vector(6 downto 0);`
91
92			`signal irq_s : std_logic;`
93			`signal ifgEn_s : std_logic;`
94			`signal divclk_s : std_logic;`
95
96			`signal clrBit_s : std_logic;`
97			`signal clr_s : std_logic;`
98
99			`BEGIN`
100
101			`delay_i: gendelay`
102			`generic map (n => 2)`
103			`port map (`
104			`a_in => clrBit_s,`
105			`a_out => clr_s`
106			`);`
107
108			`rst_n_s <= rst_n;`
109			`clk_s <= clk;`
110
111			`clk_div_i : clock_divider`
112			`generic map (n => 2)`
113			`port map (`
114			`inclk => clk_s,`
115			`outclk => divclk_s,`
116
117			`div => ctl_reg(2 downto 1),`
118			`en => ctl_reg(0)`
119			`);`
120
121			`tar_cnt : process (divclk_s, rst_n_s, clr_s) -- state counter`
122			`variable cnt: unsigned (15 downto 0);`
123			`BEGIN`
124			`IF (rst_n_s = '0' or clr_s = '1') THEN`
125			`cnt := (others => '0');`
126			`ELSE`
127			`if (divclk_s'EVENT AND divclk_s = '1') THEN -- rising SCKL edge`
128			`IF (ctl_reg(6) = '0' and cnt = cnt'high) or (ctl_reg(6) = '1' and cnt = unsigned(ccr0)) THEN`
129			`cnt := (others => '0');`
130			`ELSE`
131			`cnt := cnt + 1;`
132			`END IF;`
133			`END if;`
134			`END IF;`
135
136			`cnt_reg <= std_logic_vector(cnt);`
137			`END PROCESS;`
138
139			`irq_en : process(rst_n_s, clk_s)`
140			`begin`
141			`IF (rst_n_s = '0') THEN`
142			`irq_s <= '0';`
143			`ELSE`
144			`if (clk_s'EVENT AND clk_s = '0') THEN -- falling SCKL edge`
145			`if (irq_ack = '1') then`
146			`irq_s <= '0';`
147			`else`
148			`if ((ctl_reg(4) = '1' and cnt_reg = ccr0 and ifg_reg(0) = '0') or (ctl_reg(5) = '1' and cnt_reg = ccr1 and ifg_reg(1) = '0')) then`
149			`irq_s <= '1';`
150			`end if;`
151			`end if;`
152			`end if;`
153			`end if;`
154			`end process;`
155
156			`ifgEn_s <= irq_s or not(writeEn_n);`
157
158			`ifg : process(rst_n_s, ifgEn_s)`
159			`BEGIN`
160			`IF (rst_n_s = '0') THEN`
161			`ifg_reg <= (others => '0');`
162			`ELSE`
163			`if (ifgEn_s'event and ifgEn_s = '1') then`
164			`if (irq_s = '1') then`
165			`if (ctl_reg(4) = '1' and cnt_reg = ccr0) then`
166			`ifg_reg(0) <= '1';`
167			`end if;`
168
169			`if (ctl_reg(5) = '1' and cnt_reg = ccr1) then`
170			`ifg_reg(1) <= '1';`
171			`end if;`
172			`else`
173			`if (readEn_n = '0' and writeEn_n = '0' and addr = "001") then`
174			`ifg_reg <= ifg_reg and not(dataIn(1 downto 0));`
175			`end if;`
176			`end if;`
177			`end if;`
178			`end if;`
179			`end process;`
180
181			`wr_reg : process(rst_n_s, readEn_n, writeEn_n) -- state counter`
182			`BEGIN`
183			`IF (rst_n_s = '0') THEN`
184			`ctl_reg <= (others => '0');`
185
186			`ccr0 <= (others => '0');`
187			`ccr1 <= (others => '0');`
188			`ELSE`
189			`if (readEn_n = '0') then`
190			`if (writeEn_n'event and writeEn_n = '0') then`
191			`CASE addr IS`
192			`when "000" => ctl_reg <= dataIn(6 downto 0);`
193			`when "100" => ccr0(7 downto 0) <= dataIn;`
194			`when "101" => ccr0(15 downto 8) <= dataIn;`
195			`when "110" => ccr1(7 downto 0) <= dataIn;`
196			`when "111" => ccr1(15 downto 8) <= dataIn;`
197			`WHEN others => null;`
198			`END CASE;`
199			`end if;`
200			`end if;`
201			`end if;`
202			`END PROCESS;`
203
204			`clrBit_s <= '1' when dataIn(7) = '1' and readEn_n = '0' and addr = "000" and writeEn_n = '0' else`
205			`'0';`
206
207			`dataOut <= '0' & ctl_reg when rst_n_s = '1' and readEn_n = '0' and addr = "000" else`
208			`"000000" & ifg_reg(1 downto 0) when rst_n_s = '1' and readEn_n = '0' and addr = "001" else`
209			`cnt_reg(7 downto 0) when rst_n_s = '1' and readEn_n = '0' and addr = "010" else`
210			`cnt_reg(15 downto 8) when rst_n_s = '1' and readEn_n = '0' and addr = "011" else`
211			`ccr0(7 downto 0) when rst_n_s = '1' and readEn_n = '0' and addr = "100" else`
212			`ccr0(15 downto 8) when rst_n_s = '1' and readEn_n = '0' and addr = "101" else`
213			`ccr1(7 downto 0) when rst_n_s = '1' and readEn_n = '0' and addr = "110" else`
214			`ccr1(15 downto 8) when rst_n_s = '1' and readEn_n = '0' and addr = "111" else`
215			`(others => '0');`
216
217			`irq <= irq_s when rst_n_s = '1' else`
218			`'0';`
219
220			`END behav;`
221