URL https://opencores.org/ocsvn/tinyvliw8/tinyvliw8/trunk

Subversion Repositories tinyvliw8

[/] [tinyvliw8/] [trunk/] [testbench/] [sysArch_tb.vhd] - Blame information for rev 4

Go to most recent revision | Details | Compare with Previous | View Log


library IEEE;
use IEEE.std_logic_1164.all;
 
entity sysArch_tb is
end sysArch_tb;
 
architecture beh of sysArch_tb is
 
component sysArch
        port (
                -- clock input
                clk           : in std_logic;
 
                -- instruction bus
                instMemAddr   : out std_logic_vector(10 downto 0);
                instMemDataIn : in  std_logic_vector(31 downto 0);
                instMemEn_n   : out std_logic;
 
                -- data bus
                dataMemAddr    : out std_logic_vector(7 downto 0);
                dataMemDataIn  : in  std_logic_vector(7 downto 0);
                dataMemDataOut : out std_logic_vector(7 downto 0);
                dataMemEn_n    : out std_logic;
                dataMemWr_n    : out std_logic;
 
                ioAddr    : out std_logic_vector(7 downto 0);
                ioDataIn  : in  std_logic_vector(7 downto 0);
                ioDataOut : out std_logic_vector(7 downto 0);
                ioWrEn_n  : out std_logic;
                ioRdEn_n  : out std_logic;
 
                -- interrupt handling
                irqLine        : in  std_logic;
                irqLineAck     : out std_logic;
 
                -- general purpose IO
                gpio_in  : in  std_logic_vector(7 downto 0);
                gpio_out : out  std_logic_vector(7 downto 0);
                gpio_dir : out  std_logic_vector(7 downto 0);
 
                spi_clk  : OUT STD_LOGIC;       -- SPI clock
                spi_cs   : OUT STD_LOGIC;       -- SPI slave select, active level configurable
                spi_mosi : OUT STD_LOGIC;       -- SPI master output, slave input
                spi_miso : IN  STD_LOGIC;       -- SPI master input, slave output
 
                stall_n      : in std_logic;
                stalled_n    : out std_logic;
 
                -- reset input
                rst_n        : in std_logic
        );
end component;
 
component symDecoder
        port (
                clk          : in std_logic;
 
                codeA        : in std_logic;
                codeB        : in std_logic;
 
                ioAddr       : in std_logic_vector(3 downto 0);   -- register address
                ioWriteEn_n  : in std_logic;                     -- write enable, low active
                ioReadEn_n   : in std_logic;                     -- read enable, low active
 
                ioDataOut    : out std_logic_vector(7 downto 0); -- data bus for writing register
                ioDataIn     : in std_logic_vector(7 downto 0);  -- data bus for reading register
 
                irq          : out std_logic;
                irq_ack      : in  std_logic;
 
                rst_n        : in std_logic
        );
end component;
 
component lib_tb_clock32kHz is
        port (
                signal clk   : out std_logic;
                signal rst_n : out std_logic
        );
end component;
 
component dataMem
        PORT (
                address         : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                data            : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                inclock         : IN STD_LOGIC;
                outclock                : IN STD_LOGIC;
                wren            : IN STD_LOGIC;
                q                       : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
        );
end component dataMem;
 
component lib_tb_rom32bit is
        generic ( fileName : string );
        port (
                signal addr    : in std_logic_vector(10 downto 0);
                signal dataOut : out std_logic_vector(31 downto 0);
                signal en_n    : in std_logic
        );
end component;
 
component wurCodeGen_tb is
        port (
                clk     : in std_logic;
 
                pattern : in std_logic_vector(31 downto 0);
                mask    : in std_logic_vector(31 downto 0);
 
                codeA   : out std_logic;
                codeB   : out std_logic;
 
                finished : out std_logic;
 
                rst_n   : in std_logic
        );
end component;
 
component gendelay
        generic (n: integer := 1);
        port (
                a_in    : in    std_logic;
                a_out   : out   std_logic
        );
end component;
 
        signal clk_s       : std_logic;
 
        signal dataAddr_s  : std_logic_vector(7 downto 0);
        signal dataIn_s    : std_logic_vector(7 downto 0);
        signal dataOut_s   : std_logic_vector(7 downto 0);
        signal dataEn_n_s  : std_logic;
        signal dataEnDly_n_s  : std_logic;
        signal dataWr_n_s  : std_logic;
        signal dataWr_s  : std_logic;
 
        signal instAddr_s  : std_logic_vector(10 downto 0);
        signal instData_s  : std_logic_vector(31 downto 0);
        signal instEn_n_s  : std_logic;
 
        signal gpio_in_s   : std_logic_vector(7 downto 0);
        signal gpio_out_s  : std_logic_vector(7 downto 0);
        signal gpio_dir_s  : std_logic_vector(7 downto 0);
 
        signal stall_n_s   : std_logic := '1';
        signal stalled_n_s : std_logic;
 
        signal ioAddr_s     : std_logic_vector(7 downto 0) := (others => '0');
        signal ioDataIn_s   : std_logic_vector(7 downto 0) := (others => '0');
        signal ioDataOut_s  : std_logic_vector(7 downto 0);
        signal ioWrEn_n_s   : std_logic                    := '1';
        signal ioRdEn_n_s   : std_logic                    := '1';
 
        signal irqLine_s    : std_logic;
        signal irqLineAck_s : std_logic                    := '0';
 
        signal spiClk_s  : std_logic;
        signal spiCs_s   : std_logic;
        signal spiMosi_s : std_logic;
        signal spiMiso_s : std_logic := '0';
 
        signal dataInClk_s   : std_logic;
        signal dataOutClk_s  : std_logic;
 
        signal ioSymRdEn_n_s : std_logic;
 
        signal wurPattern_s  : std_Logic_vector(31 downto 0);
        signal wurMsk_s      : std_Logic_vector(31 downto 0);
        signal codeA_s       : std_logic;
        signal codeB_s       : std_logic;
 
        signal wurCodeEn_n_s : std_logic;
        signal wurCodeFin_s  : std_logic;
 
        signal rst_n_s     : std_logic                     := '1';
 
begin
 
        sysArch_i : sysArch
        port map(
                clk           => clk_s,
 
                -- instruction bus
                instMemAddr   => instAddr_s,
                instMemDataIn => instData_s,
                instMemEn_n   => instEn_n_s,
 
                -- data bus
                dataMemAddr    => dataAddr_s,
                dataMemDataIn  => dataIn_s,
                dataMemDataOut => dataOut_s,
                dataMemEn_n    => dataEn_n_s,
                dataMemWr_n    => dataWr_n_s,
 
                ioAddr         => ioAddr_s,
                ioDataIn       => ioDataIn_s,
                ioDataOut      => ioDataOut_s,
                ioWrEn_n       => ioWrEn_n_s,
                ioRdEn_n       => ioRdEn_n_s,
 
                irqLine        => irqLine_s,
                irqLineAck     => irqLineAck_s,
 
                -- general purpose IO
                gpio_in  => gpio_in_s,
                gpio_out => gpio_out_s,
                gpio_dir => gpio_dir_s,
 
                spi_clk  => spiClk_s,
                spi_cs   => spiCs_s,
                spi_mosi => spiMosi_s,
                spi_miso => spiMiso_s,
 
                stall_n        => stall_n_s,
                stalled_n      => stalled_n_s,
 
                rst_n         => rst_n_s
        );
 
        symDecoder_i: symDecoder
        port map (
                clk          => clk_s,
 
                codeA        => codeA_s,
                codeB        => codeB_s,
 
                ioAddr       => ioAddr_s(3 downto 0),
                ioWriteEn_n  => ioWrEn_n_s,
                ioReadEn_n   => ioSymRdEn_n_s,
 
                ioDataOut    => ioDataIn_s,
                ioDataIn     => ioDataOut_s,
 
                irq          => irqLine_s,
                irq_ack      => irqLineAck_s,
 
                rst_n        => rst_n_s
        );
 
        ioSymRdEn_n_s <= ioRdEn_n_s when ioAddr_s(7 downto 4) = "0100" else
                                   '1';
 
        tb_wurCodeGen_i: wurCodeGen_tb
        port map (
                clk      => clk_s,
                pattern  => wurPattern_s,
                mask     => wurMsk_s,
                codeA    => codeA_s,
                codeB    => codeB_s,
                finished => wurCodeFin_s,
                rst_n    => wurCodeEn_n_s
        );
 
        tb_clock32kHz_i: lib_tb_clock32kHz
        port map (
                clk     => clk_s,
                rst_n   => rst_n_s
        );
 
        tb_rom32bit_i: lib_tb_rom32bit
        generic map ( fileName => "../programs/sha1Test.ihex" )
        port map (
                addr    => instAddr_s,
                dataOut => instData_s,
                en_n    => instEn_n_s
        );
 
        dataMem_i : dataMem
        port map (
                address   => dataAddr_s,
                data      => dataOut_s,
                inclock   => dataInClk_s,
                outclock  => dataOutClk_s,
                wren      => dataWr_s,
                q         => dataIn_s
        );
 
        dataWr_s <= not(dataWr_n_s);
 
        dataMemOutClk_delay_i: gendelay
                generic map (n => 5)
                port map (
                        a_in    => dataEn_n_s,
                        a_out   => dataEnDly_n_s
                );
 
        dataInClk_s <= '1' when (dataEn_n_s = '0' and dataEnDly_n_s = '1' and dataWr_n_s = '1') or
                                (dataEn_n_s = '0' and dataEnDly_n_s = '0' and dataWr_n_s = '0') else
                       '0';
        dataOutClk_s <= not(dataInClk_s);
 
 
        wurGen_p : process
        begin
                wurMsk_s     <= x"ffffffff";
                wurPattern_s <= x"abababab";
                wurCodeEn_n_s <= '0';
 
                loop
                        wait on rst_n_s;
                        exit when rst_n_s = '1';
                end loop;
 
                loop
                        wait for 100 ms;
 
                        wurCodeEn_n_s <= '1';
 
                        loop
                                wait on wurCodeFin_s;
                                exit when wurCodeFin_s = '1';
                        end loop;
 
                        wurCodeEn_n_s <= '0';
                end loop;
        end process;
 
end beh;
 

Browse

Tools

Subversion Repositories tinyvliw8

[/] [tinyvliw8/] [trunk/] [testbench/] [sysArch_tb.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	3	steckol	`library IEEE;`
2			`use IEEE.std_logic_1164.all;`
3
4			`entity sysArch_tb is`
5			`end sysArch_tb;`
6
7			`architecture beh of sysArch_tb is`
8
9			`component sysArch`
10			`port (`
11			`-- clock input`
12			`clk : in std_logic;`
13
14			`-- instruction bus`
15			`instMemAddr : out std_logic_vector(10 downto 0);`
16			`instMemDataIn : in std_logic_vector(31 downto 0);`
17			`instMemEn_n : out std_logic;`
18
19			`-- data bus`
20			`dataMemAddr : out std_logic_vector(7 downto 0);`
21			`dataMemDataIn : in std_logic_vector(7 downto 0);`
22			`dataMemDataOut : out std_logic_vector(7 downto 0);`
23			`dataMemEn_n : out std_logic;`
24			`dataMemWr_n : out std_logic;`
25
26			`ioAddr : out std_logic_vector(7 downto 0);`
27			`ioDataIn : in std_logic_vector(7 downto 0);`
28			`ioDataOut : out std_logic_vector(7 downto 0);`
29			`ioWrEn_n : out std_logic;`
30			`ioRdEn_n : out std_logic;`
31
32			`-- interrupt handling`
33			`irqLine : in std_logic;`
34			`irqLineAck : out std_logic;`
35
36			`-- general purpose IO`
37			`gpio_in : in std_logic_vector(7 downto 0);`
38			`gpio_out : out std_logic_vector(7 downto 0);`
39			`gpio_dir : out std_logic_vector(7 downto 0);`
40
41			`spi_clk : OUT STD_LOGIC; -- SPI clock`
42			`spi_cs : OUT STD_LOGIC; -- SPI slave select, active level configurable`
43			`spi_mosi : OUT STD_LOGIC; -- SPI master output, slave input`
44			`spi_miso : IN STD_LOGIC; -- SPI master input, slave output`
45
46			`stall_n : in std_logic;`
47			`stalled_n : out std_logic;`
48
49			`-- reset input`
50			`rst_n : in std_logic`
51			`);`
52			`end component;`
53
54			`component symDecoder`
55			`port (`
56			`clk : in std_logic;`
57
58			`codeA : in std_logic;`
59			`codeB : in std_logic;`
60
61			`ioAddr : in std_logic_vector(3 downto 0); -- register address`
62			`ioWriteEn_n : in std_logic; -- write enable, low active`
63			`ioReadEn_n : in std_logic; -- read enable, low active`
64
65			`ioDataOut : out std_logic_vector(7 downto 0); -- data bus for writing register`
66			`ioDataIn : in std_logic_vector(7 downto 0); -- data bus for reading register`
67
68			`irq : out std_logic;`
69			`irq_ack : in std_logic;`
70
71			`rst_n : in std_logic`
72			`);`
73			`end component;`
74
75			`component lib_tb_clock32kHz is`
76			`port (`
77			`signal clk : out std_logic;`
78			`signal rst_n : out std_logic`
79			`);`
80			`end component;`
81
82			`component dataMem`
83			`PORT (`
84			`address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);`
85			`data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);`
86			`inclock : IN STD_LOGIC;`
87			`outclock : IN STD_LOGIC;`
88			`wren : IN STD_LOGIC;`
89			`q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)`
90			`);`
91			`end component dataMem;`
92
93			`component lib_tb_rom32bit is`
94			`generic ( fileName : string );`
95			`port (`
96			`signal addr : in std_logic_vector(10 downto 0);`
97			`signal dataOut : out std_logic_vector(31 downto 0);`
98			`signal en_n : in std_logic`
99			`);`
100			`end component;`
101
102			`component wurCodeGen_tb is`
103			`port (`
104			`clk : in std_logic;`
105
106			`pattern : in std_logic_vector(31 downto 0);`
107			`mask : in std_logic_vector(31 downto 0);`
108
109			`codeA : out std_logic;`
110			`codeB : out std_logic;`
111
112			`finished : out std_logic;`
113
114			`rst_n : in std_logic`
115			`);`
116			`end component;`
117
118			`component gendelay`
119			`generic (n: integer := 1);`
120			`port (`
121			`a_in : in std_logic;`
122			`a_out : out std_logic`
123			`);`
124			`end component;`
125
126			`signal clk_s : std_logic;`
127
128			`signal dataAddr_s : std_logic_vector(7 downto 0);`
129			`signal dataIn_s : std_logic_vector(7 downto 0);`
130			`signal dataOut_s : std_logic_vector(7 downto 0);`
131			`signal dataEn_n_s : std_logic;`
132			`signal dataEnDly_n_s : std_logic;`
133			`signal dataWr_n_s : std_logic;`
134			`signal dataWr_s : std_logic;`
135
136			`signal instAddr_s : std_logic_vector(10 downto 0);`
137			`signal instData_s : std_logic_vector(31 downto 0);`
138			`signal instEn_n_s : std_logic;`
139
140			`signal gpio_in_s : std_logic_vector(7 downto 0);`
141			`signal gpio_out_s : std_logic_vector(7 downto 0);`
142			`signal gpio_dir_s : std_logic_vector(7 downto 0);`
143
144			`signal stall_n_s : std_logic := '1';`
145			`signal stalled_n_s : std_logic;`
146
147			`signal ioAddr_s : std_logic_vector(7 downto 0) := (others => '0');`
148			`signal ioDataIn_s : std_logic_vector(7 downto 0) := (others => '0');`
149			`signal ioDataOut_s : std_logic_vector(7 downto 0);`
150			`signal ioWrEn_n_s : std_logic := '1';`
151			`signal ioRdEn_n_s : std_logic := '1';`
152
153			`signal irqLine_s : std_logic;`
154			`signal irqLineAck_s : std_logic := '0';`
155
156			`signal spiClk_s : std_logic;`
157			`signal spiCs_s : std_logic;`
158			`signal spiMosi_s : std_logic;`
159			`signal spiMiso_s : std_logic := '0';`
160
161			`signal dataInClk_s : std_logic;`
162			`signal dataOutClk_s : std_logic;`
163
164			`signal ioSymRdEn_n_s : std_logic;`
165
166			`signal wurPattern_s : std_Logic_vector(31 downto 0);`
167			`signal wurMsk_s : std_Logic_vector(31 downto 0);`
168			`signal codeA_s : std_logic;`
169			`signal codeB_s : std_logic;`
170
171			`signal wurCodeEn_n_s : std_logic;`
172			`signal wurCodeFin_s : std_logic;`
173
174			`signal rst_n_s : std_logic := '1';`
175
176			`begin`
177
178			`sysArch_i : sysArch`
179			`port map(`
180			`clk => clk_s,`
181
182			`-- instruction bus`
183			`instMemAddr => instAddr_s,`
184			`instMemDataIn => instData_s,`
185			`instMemEn_n => instEn_n_s,`
186
187			`-- data bus`
188			`dataMemAddr => dataAddr_s,`
189			`dataMemDataIn => dataIn_s,`
190			`dataMemDataOut => dataOut_s,`
191			`dataMemEn_n => dataEn_n_s,`
192			`dataMemWr_n => dataWr_n_s,`
193
194			`ioAddr => ioAddr_s,`
195			`ioDataIn => ioDataIn_s,`
196			`ioDataOut => ioDataOut_s,`
197			`ioWrEn_n => ioWrEn_n_s,`
198			`ioRdEn_n => ioRdEn_n_s,`
199
200			`irqLine => irqLine_s,`
201			`irqLineAck => irqLineAck_s,`
202
203			`-- general purpose IO`
204			`gpio_in => gpio_in_s,`
205			`gpio_out => gpio_out_s,`
206			`gpio_dir => gpio_dir_s,`
207
208			`spi_clk => spiClk_s,`
209			`spi_cs => spiCs_s,`
210			`spi_mosi => spiMosi_s,`
211			`spi_miso => spiMiso_s,`
212
213			`stall_n => stall_n_s,`
214			`stalled_n => stalled_n_s,`
215
216			`rst_n => rst_n_s`
217			`);`
218
219			`symDecoder_i: symDecoder`
220			`port map (`
221			`clk => clk_s,`
222
223			`codeA => codeA_s,`
224			`codeB => codeB_s,`
225
226			`ioAddr => ioAddr_s(3 downto 0),`
227			`ioWriteEn_n => ioWrEn_n_s,`
228			`ioReadEn_n => ioSymRdEn_n_s,`
229
230			`ioDataOut => ioDataIn_s,`
231			`ioDataIn => ioDataOut_s,`
232
233			`irq => irqLine_s,`
234			`irq_ack => irqLineAck_s,`
235
236			`rst_n => rst_n_s`
237			`);`
238
239			`ioSymRdEn_n_s <= ioRdEn_n_s when ioAddr_s(7 downto 4) = "0100" else`
240			`'1';`
241
242			`tb_wurCodeGen_i: wurCodeGen_tb`
243			`port map (`
244			`clk => clk_s,`
245			`pattern => wurPattern_s,`
246			`mask => wurMsk_s,`
247			`codeA => codeA_s,`
248			`codeB => codeB_s,`
249			`finished => wurCodeFin_s,`
250			`rst_n => wurCodeEn_n_s`
251			`);`
252
253			`tb_clock32kHz_i: lib_tb_clock32kHz`
254			`port map (`
255			`clk => clk_s,`
256			`rst_n => rst_n_s`
257			`);`
258
259			`tb_rom32bit_i: lib_tb_rom32bit`
260			`generic map ( fileName => "../programs/sha1Test.ihex" )`
261			`port map (`
262			`addr => instAddr_s,`
263			`dataOut => instData_s,`
264			`en_n => instEn_n_s`
265			`);`
266
267			`dataMem_i : dataMem`
268			`port map (`
269			`address => dataAddr_s,`
270			`data => dataOut_s,`
271			`inclock => dataInClk_s,`
272			`outclock => dataOutClk_s,`
273			`wren => dataWr_s,`
274			`q => dataIn_s`
275			`);`
276
277			`dataWr_s <= not(dataWr_n_s);`
278
279			`dataMemOutClk_delay_i: gendelay`
280			`generic map (n => 5)`
281			`port map (`
282			`a_in => dataEn_n_s,`
283			`a_out => dataEnDly_n_s`
284			`);`
285
286			`dataInClk_s <= '1' when (dataEn_n_s = '0' and dataEnDly_n_s = '1' and dataWr_n_s = '1') or`
287			`(dataEn_n_s = '0' and dataEnDly_n_s = '0' and dataWr_n_s = '0') else`
288			`'0';`
289			`dataOutClk_s <= not(dataInClk_s);`
290
291
292			`wurGen_p : process`
293			`begin`
294			`wurMsk_s <= x"ffffffff";`
295			`wurPattern_s <= x"abababab";`
296			`wurCodeEn_n_s <= '0';`
297
298			`loop`
299			`wait on rst_n_s;`
300			`exit when rst_n_s = '1';`
301			`end loop;`
302
303			`loop`
304			`wait for 100 ms;`
305
306			`wurCodeEn_n_s <= '1';`
307
308			`loop`
309			`wait on wurCodeFin_s;`
310			`exit when wurCodeFin_s = '1';`
311			`end loop;`
312
313			`wurCodeEn_n_s <= '0';`
314			`end loop;`
315			`end process;`
316
317			`end beh;`
318