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Subversion Repositories tlc2

[/] [tlc2/] [trunk/] [src/] [tlc2.vhd] - Blame information for rev 2

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity tlc2 is
  generic( freq : integer := 1e8; -- 100 MHz, use 100 Hz (1e2) for simulation and run 5 ms
           max_period_factor : INTEGER := 45;  --the period of the longest signal (green)
           idle_period_factor : integer := 1;  -- 1 sec blinking interval
           green_period_factor : integer := 45; -- 45 sec green interval
           orange_period_factor : integer := 5; -- 5 sec orange interval 
           red_period_factor : integer := 30; -- 30 sec red interval
           red_orange_period_factor : integer := 5); -- 5 sec red_orange interval
  port( clk, rst : in std_logic;        -- low - active reset
        j_left, j_right : IN std_logic; -- j_right turns normal mode, j_left turns test mode, both signals are low active
        led : out std_logic_vector (2 downto 0) ); -- {RED|ORANGE|GREEN}, RED is MSB
end tlc2;
 
architecture behavioral of tlc2 is
  type state is (idle0, idle1, green, orange, red, red_orange, rst_before_idle1, rst_before_idle0, rst_before_green, rst_before_orange, rst_before_red, rst_before_red_orange);
  signal pr_state, nxt_state : state;
  signal pr_state_mode, nxt_state_mode : std_logic :='0';  -- state signals for the joystick encoder
  signal led_int : std_logic_vector (2 downto 0); -- internal led signal used to invert the output if neccessary 
  SIGNAL one_sec : std_logic := '0'; -- signal with 1s period used as time basis
  SIGNAL mode : std_logic := '0'; -- changes between test end normal mode, triggered by the joystick decoder
  SIGNAL rst_int : STD_LOGIC := '1';  --used to reset the period-signals after state transition
  SIGNAL counter : INTEGER RANGE 0 TO max_period_factor := 0;
  constant one_sec_factor : integer := freq-1;
begin
 
-------------------------------------------------------------------------------
-- Simple FSM for the joystick encoder. Generats the mode - signal.
-------------------------------------------------------------------------------
mode_s_p: process(clk)
begin
  if clk'event and clk='1' then
    IF rst='0' THEN
      pr_state_mode <= '0';
    else
      pr_state_mode <= nxt_state_mode;
    END if;
  end if;
end process;
 
mode_c_p: process(pr_state_mode,j_right,j_left)
begin
  CASE pr_state_mode IS
    WHEN '0' => IF j_right='0' and j_left='1' THEN
                  nxt_state_mode <= '1';
                ELSE
                  nxt_state_mode <= '0';
                END if;
                mode <= '0';
    WHEN OTHERS => IF j_left='0' THEN
                     nxt_state_mode <= '0';
                   ELSE
                     nxt_state_mode <= '1';
                   END if;
                   mode <= '1';
  END CASE;
END process;
 
-------------------------------------------------------------------------------
-- period-signal generator
-------------------------------------------------------------------------------
time_p: process(clk)
  variable temp0 : integer RANGE 0 TO max_period_factor;
  VARIABLE flag : STD_LOGIC := '0';
BEGIN
  IF clk'EVENT AND clk='1' THEN
    IF rst_int='0' THEN -- a 0 level signal is needed by the current state of the main fsm
      temp0 := 0;
    else
      IF one_sec='0' THEN
        flag := '0';
      END IF;
      IF one_sec='1' AND  flag='0' THEN  --this part is executed only on a
--positive transition of the one_sec signal. The counter factors multiply the
--period of the one_sec signal. If you need to speed up the execution change
--the on_sec_factor to a lower value. This us usefull for simulation purposes
        flag := '1';
        IF
          temp0=max_period_factor THEN
          temp0 := 0;
        ELSE
          temp0 := temp0 + 1;
        end if;
      END if;
    END if;
  END if;
  counter <= temp0;
END process;
 
-------------------------------------------------------------------------------
-- 1 sec time basis signal generator. Generate a signal with 2 sec period.
-------------------------------------------------------------------------------
one_sec_p: process(clk)
  VARIABLE temp : integer RANGE 0 TO one_sec_factor;
begin
  IF clk'event AND clk='1' THEN
    IF rst_int='0' THEN
      temp := 0;
      one_sec <= '0';
    else
      iF temp>=one_sec_factor THEN
        temp := 0;
        one_sec <= '1';
      else
        temp := temp + 1;
        one_sec <= '0';
      END if;
    END if;
  END IF;
END process;
 
-------------------------------------------------------------------------------
-- main FSM
-------------------------------------------------------------------------------
main_s_p: process(clk)
  begin
    if clk'event and clk='1' then
      IF rst='0' THEN
        pr_state <= idle0;
      else
        pr_state <= nxt_state;
      end if;
    END if;
  end process;
 
main_c_p: process(pr_state,mode,counter)
begin
    case pr_state is
      WHEN idle0 =>             IF mode='0' then
                                  IF counter>=idle_period_factor THEN
                                    nxt_state <= rst_before_idle1;
                                  ELSE
                                    nxt_state <= idle0;
                                  END IF;
                                ELSE
                                  nxt_state <= rst_before_green;
                                END if;
                                led_int <= "010";
                                rst_int <= '1';
      when idle1 =>             if mode='0' then
                                  IF counter>=idle_period_factor THEN
                                    nxt_state <= rst_before_idle0;
                                  ELSE
                                    nxt_state <= idle1;
                                  END IF;
                                ELSE
                                  nxt_state <= rst_before_green;
                                END if;
                                led_int <= "000";
                                rst_int <= '1';
      when green =>             if mode='1' then
                                  if counter>=green_period_factor THEN
                                    nxt_state <= rst_before_orange;
                                  ELSE
                                    nxt_state <= green;
                                  END if;
                                ELSE
                                  nxt_state <= rst_before_idle0;
                                end if;
                                led_int <= "001";
                                rst_int <= '1';
      WHEN orange =>            if mode='1'then
                                  if counter>=orange_period_factor THEN
                                    nxt_state <= rst_before_red;
                                  ELSE
                                    nxt_state <= orange;
                                  END if;
                                ELSE
                                  nxt_state <= rst_before_idle0;
                                END if;
                                led_int <= "010";
                                rst_int <= '1';
      WHEN red =>               if mode='1' THEN
                                  if counter>=red_period_factor THEN
                                    nxt_state <= rst_before_red_orange;
                                  ELSE
                                    nxt_state <= red;
                                  END if;
                                ELSE
                                  nxt_state <= rst_before_idle0;
                                END if;
                                led_int <= "100";
                                rst_int <= '1';
      WHEN red_orange =>        if mode='1' THEN
                                  if counter>=red_orange_period_factor THEN
                                    nxt_state <= rst_before_green;
                                  ELSE
                                    nxt_state <= red_orange;
                                  END if;
                                ELSE
                                  nxt_state <= rst_before_idle0;
                                END if;
                                led_int <= "110";
                                rst_int <= '1';
      WHEN rst_before_idle1 =>  nxt_state <= idle1;
                                led_int <= "000";
                                rst_int <= '0';
      WHEN rst_before_green =>  nxt_state <= green;
                                led_int <= "001";
                                rst_int <= '0';
      WHEN rst_before_orange => nxt_state <= orange;
                                led_int <= "010";
                                rst_int <= '0';
      WHEN rst_before_red =>    nxt_state <= red;
                                led_int <= "100";
                                rst_int <= '0';
      WHEN rst_before_red_orange => nxt_state <= red_orange;
                                    led_int <= "110";
                                    rst_int <= '0';
      WHEN OTHERS =>            nxt_state <= idle0;
                                led_int <= "010";
                                rst_int <= '0';
    END case;
  END process;
  led <= led_int;
END behavioral;

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Subversion Repositories tlc2

[/] [tlc2/] [trunk/] [src/] [tlc2.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dimo	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3			`use ieee.numeric_std.all;`
4
5			`entity tlc2 is`
6			`generic( freq : integer := 1e8; -- 100 MHz, use 100 Hz (1e2) for simulation and run 5 ms`
7			`max_period_factor : INTEGER := 45; --the period of the longest signal (green)`
8			`idle_period_factor : integer := 1; -- 1 sec blinking interval`
9			`green_period_factor : integer := 45; -- 45 sec green interval`
10			`orange_period_factor : integer := 5; -- 5 sec orange interval`
11			`red_period_factor : integer := 30; -- 30 sec red interval`
12			`red_orange_period_factor : integer := 5); -- 5 sec red_orange interval`
13			`port( clk, rst : in std_logic; -- low - active reset`
14			`j_left, j_right : IN std_logic; -- j_right turns normal mode, j_left turns test mode, both signals are low active`
15			`led : out std_logic_vector (2 downto 0) ); -- {RED\|ORANGE\|GREEN}, RED is MSB`
16			`end tlc2;`
17
18			`architecture behavioral of tlc2 is`
19			`type state is (idle0, idle1, green, orange, red, red_orange, rst_before_idle1, rst_before_idle0, rst_before_green, rst_before_orange, rst_before_red, rst_before_red_orange);`
20			`signal pr_state, nxt_state : state;`
21			`signal pr_state_mode, nxt_state_mode : std_logic :='0'; -- state signals for the joystick encoder`
22			`signal led_int : std_logic_vector (2 downto 0); -- internal led signal used to invert the output if neccessary`
23			`SIGNAL one_sec : std_logic := '0'; -- signal with 1s period used as time basis`
24			`SIGNAL mode : std_logic := '0'; -- changes between test end normal mode, triggered by the joystick decoder`
25			`SIGNAL rst_int : STD_LOGIC := '1'; --used to reset the period-signals after state transition`
26			`SIGNAL counter : INTEGER RANGE 0 TO max_period_factor := 0;`
27			`constant one_sec_factor : integer := freq-1;`
28			`begin`
29
30			`-------------------------------------------------------------------------------`
31			`-- Simple FSM for the joystick encoder. Generats the mode - signal.`
32			`-------------------------------------------------------------------------------`
33			`mode_s_p: process(clk)`
34			`begin`
35			`if clk'event and clk='1' then`
36			`IF rst='0' THEN`
37			`pr_state_mode <= '0';`
38			`else`
39			`pr_state_mode <= nxt_state_mode;`
40			`END if;`
41			`end if;`
42			`end process;`
43
44			`mode_c_p: process(pr_state_mode,j_right,j_left)`
45			`begin`
46			`CASE pr_state_mode IS`
47			`WHEN '0' => IF j_right='0' and j_left='1' THEN`
48			`nxt_state_mode <= '1';`
49			`ELSE`
50			`nxt_state_mode <= '0';`
51			`END if;`
52			`mode <= '0';`
53			`WHEN OTHERS => IF j_left='0' THEN`
54			`nxt_state_mode <= '0';`
55			`ELSE`
56			`nxt_state_mode <= '1';`
57			`END if;`
58			`mode <= '1';`
59			`END CASE;`
60			`END process;`
61
62			`-------------------------------------------------------------------------------`
63			`-- period-signal generator`
64			`-------------------------------------------------------------------------------`
65			`time_p: process(clk)`
66			`variable temp0 : integer RANGE 0 TO max_period_factor;`
67			`VARIABLE flag : STD_LOGIC := '0';`
68			`BEGIN`
69			`IF clk'EVENT AND clk='1' THEN`
70			`IF rst_int='0' THEN -- a 0 level signal is needed by the current state of the main fsm`
71			`temp0 := 0;`
72			`else`
73			`IF one_sec='0' THEN`
74			`flag := '0';`
75			`END IF;`
76			`IF one_sec='1' AND flag='0' THEN --this part is executed only on a`
77			`--positive transition of the one_sec signal. The counter factors multiply the`
78			`--period of the one_sec signal. If you need to speed up the execution change`
79			`--the on_sec_factor to a lower value. This us usefull for simulation purposes`
80			`flag := '1';`
81			`IF`
82			`temp0=max_period_factor THEN`
83			`temp0 := 0;`
84			`ELSE`
85			`temp0 := temp0 + 1;`
86			`end if;`
87			`END if;`
88			`END if;`
89			`END if;`
90			`counter <= temp0;`
91			`END process;`
92
93			`-------------------------------------------------------------------------------`
94			`-- 1 sec time basis signal generator. Generate a signal with 2 sec period.`
95			`-------------------------------------------------------------------------------`
96			`one_sec_p: process(clk)`
97			`VARIABLE temp : integer RANGE 0 TO one_sec_factor;`
98			`begin`
99			`IF clk'event AND clk='1' THEN`
100			`IF rst_int='0' THEN`
101			`temp := 0;`
102			`one_sec <= '0';`
103			`else`
104			`iF temp>=one_sec_factor THEN`
105			`temp := 0;`
106			`one_sec <= '1';`
107			`else`
108			`temp := temp + 1;`
109			`one_sec <= '0';`
110			`END if;`
111			`END if;`
112			`END IF;`
113			`END process;`
114
115			`-------------------------------------------------------------------------------`
116			`-- main FSM`
117			`-------------------------------------------------------------------------------`
118			`main_s_p: process(clk)`
119			`begin`
120			`if clk'event and clk='1' then`
121			`IF rst='0' THEN`
122			`pr_state <= idle0;`
123			`else`
124			`pr_state <= nxt_state;`
125			`end if;`
126			`END if;`
127			`end process;`
128
129			`main_c_p: process(pr_state,mode,counter)`
130			`begin`
131			`case pr_state is`
132			`WHEN idle0 => IF mode='0' then`
133			`IF counter>=idle_period_factor THEN`
134			`nxt_state <= rst_before_idle1;`
135			`ELSE`
136			`nxt_state <= idle0;`
137			`END IF;`
138			`ELSE`
139			`nxt_state <= rst_before_green;`
140			`END if;`
141			`led_int <= "010";`
142			`rst_int <= '1';`
143			`when idle1 => if mode='0' then`
144			`IF counter>=idle_period_factor THEN`
145			`nxt_state <= rst_before_idle0;`
146			`ELSE`
147			`nxt_state <= idle1;`
148			`END IF;`
149			`ELSE`
150			`nxt_state <= rst_before_green;`
151			`END if;`
152			`led_int <= "000";`
153			`rst_int <= '1';`
154			`when green => if mode='1' then`
155			`if counter>=green_period_factor THEN`
156			`nxt_state <= rst_before_orange;`
157			`ELSE`
158			`nxt_state <= green;`
159			`END if;`
160			`ELSE`
161			`nxt_state <= rst_before_idle0;`
162			`end if;`
163			`led_int <= "001";`
164			`rst_int <= '1';`
165			`WHEN orange => if mode='1'then`
166			`if counter>=orange_period_factor THEN`
167			`nxt_state <= rst_before_red;`
168			`ELSE`
169			`nxt_state <= orange;`
170			`END if;`
171			`ELSE`
172			`nxt_state <= rst_before_idle0;`
173			`END if;`
174			`led_int <= "010";`
175			`rst_int <= '1';`
176			`WHEN red => if mode='1' THEN`
177			`if counter>=red_period_factor THEN`
178			`nxt_state <= rst_before_red_orange;`
179			`ELSE`
180			`nxt_state <= red;`
181			`END if;`
182			`ELSE`
183			`nxt_state <= rst_before_idle0;`
184			`END if;`
185			`led_int <= "100";`
186			`rst_int <= '1';`
187			`WHEN red_orange => if mode='1' THEN`
188			`if counter>=red_orange_period_factor THEN`
189			`nxt_state <= rst_before_green;`
190			`ELSE`
191			`nxt_state <= red_orange;`
192			`END if;`
193			`ELSE`
194			`nxt_state <= rst_before_idle0;`
195			`END if;`
196			`led_int <= "110";`
197			`rst_int <= '1';`
198			`WHEN rst_before_idle1 => nxt_state <= idle1;`
199			`led_int <= "000";`
200			`rst_int <= '0';`
201			`WHEN rst_before_green => nxt_state <= green;`
202			`led_int <= "001";`
203			`rst_int <= '0';`
204			`WHEN rst_before_orange => nxt_state <= orange;`
205			`led_int <= "010";`
206			`rst_int <= '0';`
207			`WHEN rst_before_red => nxt_state <= red;`
208			`led_int <= "100";`
209			`rst_int <= '0';`
210			`WHEN rst_before_red_orange => nxt_state <= red_orange;`
211			`led_int <= "110";`
212			`rst_int <= '0';`
213			`WHEN OTHERS => nxt_state <= idle0;`
214			`led_int <= "010";`
215			`rst_int <= '0';`
216			`END case;`
217			`END process;`
218			`led <= led_int;`
219			`END behavioral;`