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mongoq |
EDA Netlist Writer report for tm1637
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Sat Mar 13 16:24:06 2021
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Quartus Prime Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. EDA Netlist Writer Summary
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3. Simulation Settings
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4. Simulation Generated Files
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5. EDA Netlist Writer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2020 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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+-------------------------------------------------------------------+
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; EDA Netlist Writer Summary ;
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+---------------------------+---------------------------------------+
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; EDA Netlist Writer Status ; Successful - Sat Mar 13 16:24:06 2021 ;
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; Revision Name ; tm1637 ;
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; Top-level Entity Name ; tm1637_toplevel ;
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; Family ; Cyclone IV E ;
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; Simulation Files Creation ; Successful ;
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+---------------------------+---------------------------------------+
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+----------------------------------------------------------------------------------------------------------------------------+
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; Simulation Settings ;
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+---------------------------------------------------------------------------------------------------+------------------------+
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; Option ; Setting ;
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+---------------------------------------------------------------------------------------------------+------------------------+
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; Tool Name ; ModelSim-Altera (VHDL) ;
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; Generate functional simulation netlist ; Off ;
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; Time scale ; 1 ps ;
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; Truncate long hierarchy paths ; Off ;
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; Map illegal HDL characters ; Off ;
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; Flatten buses into individual nodes ; Off ;
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; Maintain hierarchy ; Off ;
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; Bring out device-wide set/reset signals as ports ; Off ;
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; Enable glitch filtering ; Off ;
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; Do not write top level VHDL entity ; Off ;
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; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
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; Architecture name in VHDL output netlist ; structure ;
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; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
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; Generate third-party EDA tool command script for gate-level simulation ; Off ;
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+---------------------------------------------------------------------------------------------------+------------------------+
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+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Simulation Generated Files ;
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+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Generated Files ;
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+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/tm1637_8_1200mv_85c_slow.vho ;
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; /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/tm1637_8_1200mv_0c_slow.vho ;
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; /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/tm1637_min_1200mv_0c_fast.vho ;
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; /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/tm1637.vho ;
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; /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/tm1637_8_1200mv_85c_vhd_slow.sdo ;
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; /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/tm1637_8_1200mv_0c_vhd_slow.sdo ;
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; /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/tm1637_min_1200mv_0c_vhd_fast.sdo ;
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; /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/tm1637_vhd.sdo ;
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+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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+-----------------------------+
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; EDA Netlist Writer Messages ;
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+-----------------------------+
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Info: *******************************************************************
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Info: Running Quartus Prime EDA Netlist Writer
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Info: Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
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Info: Processing started: Sat Mar 13 16:24:05 2021
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Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off tm1637 -c tm1637
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Info (204019): Generated file tm1637_8_1200mv_85c_slow.vho in folder "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file tm1637_8_1200mv_0c_slow.vho in folder "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file tm1637_min_1200mv_0c_fast.vho in folder "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file tm1637.vho in folder "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file tm1637_8_1200mv_85c_vhd_slow.sdo in folder "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file tm1637_8_1200mv_0c_vhd_slow.sdo in folder "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file tm1637_min_1200mv_0c_vhd_fast.sdo in folder "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file tm1637_vhd.sdo in folder "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/" for EDA simulation tool
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Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 0 warnings
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Info: Peak virtual memory: 807 megabytes
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Info: Processing ended: Sat Mar 13 16:24:06 2021
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Info: Elapsed time: 00:00:01
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Info: Total CPU time (on all processors): 00:00:01
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