1 |
3 |
mongoq |
# do tm1637_run_msim_rtl_vhdl.do
|
2 |
|
|
# if {[file exists rtl_work]} {
|
3 |
|
|
# vdel -lib rtl_work -all
|
4 |
|
|
# }
|
5 |
|
|
# vlib rtl_work
|
6 |
|
|
# vmap work rtl_work
|
7 |
|
|
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
|
8 |
|
|
# vmap work rtl_work
|
9 |
|
|
# Copying /home/mongoq/projects/fpga/intelFPGA_lite/20.1/modelsim_ase/linuxaloem/../modelsim.ini to modelsim.ini
|
10 |
|
|
# Modifying modelsim.ini
|
11 |
|
|
#
|
12 |
|
|
# vcom -93 -work work {/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/tm1637_external_connect.vhd}
|
13 |
|
|
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
|
14 |
|
|
# Start time: 20:07:47 on Feb 24,2021
|
15 |
|
|
# vcom -reportprogress 300 -93 -work work /home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/tm1637_external_connect.vhd
|
16 |
|
|
# -- Loading package STANDARD
|
17 |
|
|
# -- Loading package TEXTIO
|
18 |
|
|
# -- Loading package std_logic_1164
|
19 |
|
|
# -- Loading package NUMERIC_STD
|
20 |
|
|
# -- Loading package std_logic_arith
|
21 |
|
|
# -- Loading package STD_LOGIC_UNSIGNED
|
22 |
|
|
# -- Compiling entity tm1637_external_connect
|
23 |
|
|
# -- Compiling architecture Behavioral of tm1637_external_connect
|
24 |
|
|
# End time: 20:07:47 on Feb 24,2021, Elapsed time: 0:00:00
|
25 |
|
|
# Errors: 0, Warnings: 0
|
26 |
|
|
# vcom -93 -work work {/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/tm1637_toplevel.vhd}
|
27 |
|
|
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
|
28 |
|
|
# Start time: 20:07:48 on Feb 24,2021
|
29 |
|
|
# vcom -reportprogress 300 -93 -work work /home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/tm1637_toplevel.vhd
|
30 |
|
|
# -- Loading package STANDARD
|
31 |
|
|
# -- Loading package TEXTIO
|
32 |
|
|
# -- Loading package std_logic_1164
|
33 |
|
|
# -- Loading package NUMERIC_STD
|
34 |
|
|
# -- Loading package std_logic_arith
|
35 |
|
|
# -- Loading package STD_LOGIC_UNSIGNED
|
36 |
|
|
# -- Compiling entity tm1637_toplevel
|
37 |
|
|
# -- Compiling architecture Behavioral of tm1637_toplevel
|
38 |
|
|
# End time: 20:07:48 on Feb 24,2021, Elapsed time: 0:00:00
|
39 |
|
|
# Errors: 0, Warnings: 0
|
40 |
|
|
# vcom -93 -work work {/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/tm1637_decimal_count.vhd}
|
41 |
|
|
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
|
42 |
|
|
# Start time: 20:07:48 on Feb 24,2021
|
43 |
|
|
# vcom -reportprogress 300 -93 -work work /home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/tm1637_decimal_count.vhd
|
44 |
|
|
# -- Loading package STANDARD
|
45 |
|
|
# -- Loading package TEXTIO
|
46 |
|
|
# -- Loading package std_logic_1164
|
47 |
|
|
# -- Loading package NUMERIC_STD
|
48 |
|
|
# -- Compiling entity tm1637_decimal_count
|
49 |
|
|
# -- Compiling architecture behavioral of tm1637_decimal_count
|
50 |
|
|
# End time: 20:07:48 on Feb 24,2021, Elapsed time: 0:00:00
|
51 |
|
|
# Errors: 0, Warnings: 0
|
52 |
|
|
#
|
53 |
|
|
#
|
54 |
|
|
# stdin:
|