URL https://opencores.org/ocsvn/tm1637/tm1637/trunk

Subversion Repositories tm1637

[/] [tm1637/] [trunk/] [hdl/] [intel_qp/] [dec_counter/] [simulation/] [modelsim/] [tm1637.sft] - Blame information for rev 3

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set tool_name "ModelSim-Altera (VHDL)"
set corner_file_list {
    {{"Slow -8 1.2V 85 Model"} {tm1637_8_1200mv_85c_slow.vho tm1637_8_1200mv_85c_vhd_slow.sdo}}
    {{"Slow -8 1.2V 0 Model"} {tm1637_8_1200mv_0c_slow.vho tm1637_8_1200mv_0c_vhd_slow.sdo}}
    {{"Fast -M 1.2V 0 Model"} {tm1637_min_1200mv_0c_fast.vho tm1637_min_1200mv_0c_vhd_fast.sdo}}
}

Line No.	Rev	Author	Line
1	3	mongoq	`set tool_name "ModelSim-Altera (VHDL)"`
2			`set corner_file_list {`
3			`{{"Slow -8 1.2V 85 Model"} {tm1637_8_1200mv_85c_slow.vho tm1637_8_1200mv_85c_vhd_slow.sdo}}`
4			`{{"Slow -8 1.2V 0 Model"} {tm1637_8_1200mv_0c_slow.vho tm1637_8_1200mv_0c_vhd_slow.sdo}}`
5			`{{"Fast -M 1.2V 0 Model"} {tm1637_min_1200mv_0c_fast.vho tm1637_min_1200mv_0c_vhd_fast.sdo}}`
6			`}`

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[/] [tm1637/] [trunk/] [hdl/] [intel_qp/] [dec_counter/] [simulation/] [modelsim/] [tm1637.sft] - Blame information for rev 3