Subversion Repositories tm1637

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#

# Copyright (C) 2018  Intel Corporation. All rights reserved.

# Your use of Intel Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Intel Program License

# Subscription Agreement, the Intel Quartus Prime License Agreement,

# the Intel FPGA IP License Agreement, or other applicable license

# agreement, including, without limitation, that your use is for

# the sole purpose of programming logic devices manufactured by

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#

# Quartus Prime

# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition

# Date created = 19:00:19  February 10, 2021

#

# -------------------------------------------------------------------------- #

#

# Notes:

#

# 1) The default values for assignments are stored in the file:

#               tm1637_assignment_defaults.qdf

#    If this file doesn't exist, see file:

#               assignment_defaults.qdf

#

# 2) Altera recommends that you do not modify this file. This

#    file is updated automatically by the Quartus Prime software

#    and any changes you make may be lost or overwritten.

#

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set_global_assignment -name FAMILY "Cyclone IV E"

set_global_assignment -name DEVICE EP4CE6E22C8

set_global_assignment -name TOP_LEVEL_ENTITY tm1637_toplevel

set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0

set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:00:19  FEBRUARY 10, 2021"

set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition"

set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V

set_location_assignment PIN_25 -to clk25

set_global_assignment -name VHDL_FILE tm1637_external_connect.vhd

set_global_assignment -name VHDL_FILE tm1637_toplevel.vhd

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

set_global_assignment -name VHDL_FILE tm1637_decimal_count.vhd

set_location_assignment PIN_128 -to dio

set_location_assignment PIN_132 -to clk

set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"

set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation

set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top