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[/] [tm1637/] [trunk/] [hdl/] [intel_qp/] [dec_counter/] [tm1637_decimal_count.vhd] - Blame information for rev 3

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1 3 mongoq 
-- https://www.engineersgarage.com/vhdl/decimal-counter-in-vhdl/
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-- https://www.edaboard.com/threads/counting-pulses-in-one-second-with-vhdl.341476/
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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entity tm1637_decimal_count is
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  generic (divider : integer);
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  port (clk25, en: IN std_logic;
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        out3, out2, out1, out0: OUT std_logic_vector(3 DOWNTO 0));
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end tm1637_decimal_count;
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architecture behavioral OF tm1637_decimal_count IS
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  signal d1000Curr, d100Curr, d1000Next, d100Next, d10Curr, d10Next, d1Curr, d1Next: unsigned(3 DOWNTO 0) := (OTHERS =>'0');
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  signal clkdiv : integer range 0 to divider-1 := 0;
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  signal ce: std_logic := '0';
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begin
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process (clk25) begin
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 if rising_edge(clk25) then
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  if (clkdiv < divider-1) then
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    clkdiv <= clkdiv + 1;
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    ce <= '0';
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   else
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    clkdiv <= 0;
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    ce <= '1';
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   end if;
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  end if;
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end process;
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process(clk25)
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begin
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 if (rising_edge(clk25)) then
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  if (ce='1') then
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   if (d1000Curr=9 AND d100Curr=9 AND d10Curr=9 AND d1Curr=9) then
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    d1000Next <= "0000";
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   elsif (d100Curr=9 AND d10Curr=9 AND d1Curr=9) then
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    d1000Next <= d1000Curr+1;
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   else
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    d1000Next <= d1000Curr;
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   end if;
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   if (d100Curr=9 AND d10Curr=9 AND d1Curr=9) then
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    d100Next <= "0000";
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   elsif (d10Curr=9 AND d1Curr=9) then
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    d100Next <= d100Curr+1;
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   else
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    d100Next <= d100Curr;
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   end if;
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   if (d10Curr=9 AND d1Curr=9) then
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    d10Next  <= "0000";
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   elsif (d1Curr=9) then
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    d10Next <= d10Curr+1;
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   else
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    d10Next <= d10Curr;
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  end if;
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  if (d1Curr=9) then
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   d1Next   <= "0000";
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  else
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   d1Next <= d1Curr+1;
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  end if;
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  end if;
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 d1000Curr <= d1000Next;
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 d100Curr <= d100Next;
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 d10Curr  <= d10Next;
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 d1Curr   <= d1Next;
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end if;
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end process;
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 out0 <= std_logic_vector(d1000Curr);
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 out1 <= std_logic_vector(d100Curr);
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 out2 <= std_logic_vector(d10Curr);
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 out3 <= std_logic_vector(d1Curr);
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end behavioral;

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