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[/] [tm1637/] [trunk/] [hdl/] [intel_qp/] [dec_counter/] [tm1637_external_connect.vhd] - Blame information for rev 3

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1 3 mongoq 
-- synthesis VHDL_INPUT_VERSION VHDL_2008
2 
-- ^^ keep this to avoid "Error (10887): VHDL error at tm1637_external_connect.vhd(112): simplified sensitivity list is not supported in VHDL_1993, and is only supported for VHDL 2008"
3 
-- https://staging.doulos.com/knowhow/vhdl/vhdl-2008-easier-to-use/
4 
-- https://community.intel.com/t5/Programmable-Devices/VHDL-2008-DSP-Builder-and-Quartus-10/td-p/16379
5 
 
6 
library IEEE;
7 
use IEEE.STD_LOGIC_1164.ALL;
8 
use IEEE.NUMERIC_STD.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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12 
entity tm1637_external_connect is
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    generic (divider  : integer);
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    Port (   clk25       : in  std_logic;
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                                 data    : in std_logic_vector(15 downto 0);
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                            clk      : out std_logic;
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                            dio      : out std_logic;
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                                 En       : in std_logic
19 
          );
20 
 
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end tm1637_external_connect;
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architecture Behavioral of tm1637_external_connect is
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25 
impure function int_to_seg7(zahl : in integer; stelle : in integer; nrbit : in integer; in_digit0 : in std_logic_vector(3 downto 0);  in_digit1 : in std_logic_vector(3 downto 0);  in_digit2 : in std_logic_vector(3 downto 0);  in_digit3 : in std_logic_vector(3 downto 0)) return std_logic is
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variable counter : integer := 0;
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variable bcd : integer := 0;
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variable seg7 : std_logic_vector(7 downto 0);
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variable dig : std_logic_vector(3 downto 0);
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-- Werte hier !!! umziehen nach display aufdröselei
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variable digit0 : std_logic_vector(3 downto 0) := "0001";
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variable digit1 : std_logic_vector(3 downto 0) := "0001";
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variable digit2 : std_logic_vector(3 downto 0) := "0001";
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variable digit3 : std_logic_vector(3 downto 0) := "0001";
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begin
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  digit0 :=  in_digit0;
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  digit1 :=  in_digit1;
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  digit2 :=  in_digit2;
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  digit3 :=  in_digit3;
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46 
 case stelle is
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  when 1 => dig := digit0;
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  when 2 => dig := digit1;
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  when 3 => dig := digit2;
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  when 4 => dig := digit3;
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  when others => null;
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 end case;
53 
 
54 
 
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 case dig is
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  when "0000"=> seg7 :=  "00111111";    -- 0
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  when "0001"=> seg7 :=  "00000110";    -- 1
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  when "0010"=> seg7 :=  "01011011";    -- 2
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  when "0011"=> seg7 :=  "01001111";    -- 3
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  when "0100"=> seg7 :=  "01100110";    -- 4
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  when "0101"=> seg7 :=  "01101101";    -- 5
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  when "0110"=> seg7 :=  "01111101";    -- 6
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  when "0111"=> seg7 :=  "00000111";    -- 7
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  when "1000"=> seg7 :=  "01111111";    -- 8
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  when "1001"=> seg7 :=  "01101111";    -- 9
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  when "1010"=> seg7 :=  "01110111";    -- A
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  when "1011"=> seg7 :=  "01111100";    -- b
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  when "1100"=> seg7 :=  "00111001";    -- C
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  when "1101"=> seg7 :=  "01011110";    -- d
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  when "1110"=> seg7 :=  "01111001";    -- E
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  when "1111"=> seg7 :=  "01110001";    -- F
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  when others=> seg7 :=  "00000000";    -- 8:
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 end case;
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 if En='0' then
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  seg7 :=  "00000000";   -- empty:
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 end if;
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 return seg7(nrbit);
78 
 
79 
end int_to_seg7;
80 
 
81 
------------------------------------------------------------------------------------------------------------------------------------
82 
 
83 
signal clkdiv : integer range 0 to divider-1 := 0;
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signal ce: std_logic := '0';
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signal sm_counter : integer := 0;
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signal clk_250k : std_logic := '0';
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signal rdy : std_logic := '0';
88 
 
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signal reg_digit0 : std_logic_vector(3 downto 0) := "0000";
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signal reg_digit1 : std_logic_vector(3 downto 0) := "0000";
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signal reg_digit2 : std_logic_vector(3 downto 0) := "0000";
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signal reg_digit3 : std_logic_vector(3 downto 0) := "0000";
93 
 
94 
signal cnt_rdy :  std_logic_vector(1 downto 0);
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signal display : integer := 0;
96 
 
97 
begin
98 
 
99 
display <= 0;
100 
 
101 
process (clk25) begin
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 if rising_edge(clk25) then
103 
  if (clkdiv < divider-1) then
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    clkdiv <= clkdiv + 1;
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    ce <= '0';
106 
   else
107 
    clkdiv <= 0;
108 
    ce <= '1';
109 
   end if;
110 
  end if;
111 
 end process;
112 
 
113 
 process(clk25)
114 
  begin
115 
 
116 
  if rising_edge(clk25) then
117 
   if (ce='1') then
118 
        case sm_counter is
119 
     when 0 => clk <= '1'; dio <= '1';
120 
     when 1 => clk <= '1'; dio <= '1';
121 
          when 2 =>             dio <= '0';
122 
          when 3 => clk <= '0';
123 
          when 4 => clk <= '1';
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          when 5 => clk <= '0'; dio <= '0';
125 
          when 6 => clk <= '1';
126 
          when 7 => clk <= '0';
127 
          when 8 => clk <= '1';
128 
          when 9 => clk <= '0';
129 
          when 10 => clk <= '1';
130 
          when 11 => clk <= '0';
131 
          when 12 => clk <= '1';
132 
          when 13 => clk <= '0';
133 
          when 14 => clk <= '1';
134 
          when 15 => clk <= '0';  dio <= '1';
135 
          when 16 => clk <= '1';
136 
          when 17 => clk <= '0';  dio <= '0';
137 
          when 18 => clk <= '1';
138 
          when 19 => clk <= '0'; dio <= 'Z';
139 
          when 20 => clk <= '1';
140 
          when 21 => clk <= '0'; dio <= '0';
141 
          when 22 => clk <= '1';
142 
     when 23 =>             dio <= '1';
143 
          when 24 => clk <= '1'; dio <= '0';
144 
          when 25 => clk <= '0'; dio <= '0';
145 
          when 26 => clk <= '1';
146 
          when 27 => clk <= '0';
147 
          when 28 => clk <= '1';
148 
          when 29 => clk <= '0'; dio <= '0';
149 
          when 30 => clk <= '1'; dio <= '0';
150 
          when 31 => clk <= '0'; dio <= '0';
151 
          when 32 => clk <= '1'; dio <= '0';
152 
          when 33 => clk <= '0'; dio <= '0';
153 
          when 34 => clk <= '1'; dio <= '0';
154 
          when 35 => clk <= '0'; dio <= '0';
155 
          when 36 => clk <= '1'; dio <= '0';
156 
          when 37 => clk <= '0'; dio <= '1';
157 
          when 38 => clk <= '1'; dio <= '1';
158 
          when 39 => clk <= '0'; dio <= '1';
159 
          when 40 => clk <= '1'; dio <= '1';
160 
          when 41 => clk <= '0'; dio <= 'Z';
161 
          when 42 => clk <= '1';
162 
          when 43 => clk <= '0'; dio <= int_to_seg7(display, 1, 0, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
163 
          when 44 => clk <= '1';
164 
          when 45 => clk <= '0'; dio <= int_to_seg7(display, 1, 1, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
165 
          when 46 => clk <= '1';
166 
          when 47 => clk <= '0'; dio <= int_to_seg7(display, 1, 2, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
167 
          when 48 => clk <= '1';
168 
          when 49 => clk <= '0'; dio <= int_to_seg7(display, 1, 3, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
169 
          when 50 => clk <= '1';
170 
          when 51 => clk <= '0'; dio <= int_to_seg7(display, 1, 4, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
171 
          when 52 => clk <= '1';
172 
          when 53 => clk <= '0'; dio <= int_to_seg7(display, 1, 5, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
173 
          when 54 => clk <= '1';
174 
          when 55 => clk <= '0'; dio <= int_to_seg7(display, 1, 6, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
175 
          when 56 => clk <= '1';
176 
          when 57 => clk <= '0'; dio <= int_to_seg7(display, 1, 7, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
177 
          when 58 => clk <= '1';
178 
          when 59 => clk <= '0'; dio <= 'Z';
179 
          when 60 => clk <= '1';
180 
          when 61 => clk <= '0'; dio <= int_to_seg7(display, 2, 0, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
181 
          when 62 => clk <= '1';
182 
          when 63 => clk <= '0'; dio <= int_to_seg7(display, 2, 1, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
183 
          when 64 => clk <= '1';
184 
          when 65 => clk <= '0'; dio <= int_to_seg7(display, 2, 2, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
185 
          when 66 => clk <= '1';
186 
          when 67 => clk <= '0'; dio <= int_to_seg7(display, 2, 3, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
187 
          when 68 => clk <= '1';
188 
          when 69 => clk <= '0'; dio <= int_to_seg7(display, 2, 4, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
189 
          when 70 => clk <= '1';
190 
          when 71 => clk <= '0'; dio <= int_to_seg7(display, 2, 5, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
191 
          when 72 => clk <= '1';
192 
          when 73 => clk <= '0'; dio <= int_to_seg7(display, 2, 6, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
193 
          when 74 => clk <= '1';
194 
          when 75 => clk <= '0'; dio <= int_to_seg7(display, 2, 7, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
195 
          when 76 => clk <= '1';
196 
          when 77 => clk <= '0'; dio <= 'Z';
197 
          when 78 => clk <= '1';
198 
          when 79 => clk <= '0'; dio <= int_to_seg7(display, 3, 0, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
199 
          when 80 => clk <= '1';
200 
          when 81 => clk <= '0'; dio <= int_to_seg7(display, 3, 1, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
201 
          when 82 => clk <= '1';
202 
          when 83 => clk <= '0'; dio <= int_to_seg7(display, 3, 2, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
203 
          when 84 => clk <= '1';
204 
          when 85 => clk <= '0'; dio <= int_to_seg7(display, 3, 3, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
205 
          when 86 => clk <= '1';
206 
          when 87 => clk <= '0'; dio <= int_to_seg7(display, 3, 4, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
207 
          when 88 => clk <= '1';
208 
          when 89 => clk <= '0'; dio <= int_to_seg7(display, 3, 5, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
209 
          when 90 => clk <= '1';
210 
          when 91 => clk <= '0'; dio <= int_to_seg7(display, 3, 6, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
211 
          when 92 => clk <= '1';
212 
          when 93 => clk <= '0'; dio <= int_to_seg7(display, 3, 7, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
213 
          when 94 => clk <= '1';
214 
          when 95 => clk <= '0'; dio <= 'Z';
215 
          when 96 => clk <= '1';
216 
          when 97 => clk <= '0'; dio <= int_to_seg7(display, 4, 0, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
217 
          when 98 => clk <= '1';
218 
          when 99 => clk <= '0'; dio <= int_to_seg7(display, 4, 1, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
219 
          when 100 => clk <= '1';
220 
          when 101 => clk <= '0'; dio <= int_to_seg7(display, 4, 2, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
221 
          when 102 => clk <= '1';
222 
          when 103 => clk <= '0'; dio <= int_to_seg7(display, 4, 3, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
223 
          when 104 => clk <= '1';
224 
          when 105 => clk <= '0'; dio <= int_to_seg7(display, 4, 4, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
225 
          when 106 => clk <= '1';
226 
          when 107 => clk <= '0'; dio <= int_to_seg7(display, 4, 5, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
227 
          when 108 => clk <= '1';
228 
          when 109 => clk <= '0'; dio <= int_to_seg7(display, 4, 6, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
229 
          when 110 => clk <= '1';
230 
          when 111 => clk <= '0'; dio <= int_to_seg7(display, 4, 7, reg_digit0, reg_digit1, reg_digit2, reg_digit3);
231 
          when 112 => clk <= '1';
232 
          when 113 => clk <= '0'; dio <= 'Z';
233 
          when 114 => clk <= '1';
234 
          when 115 => clk <= '0'; dio <= '0';
235 
          when 116 => clk <= '1';
236 
          when 117 => clk <= '1'; dio <= '1';
237 
          when 118 => clk <= '1'; dio <= '0';
238 
          when 119 => clk <= '0'; dio <= '1';
239 
          when 120 => clk <= '1';
240 
          when 121 => clk <= '0';
241 
          when 122 => clk <= '1';
242 
          when 123 => clk <= '0';
243 
          when 124 => clk <= '1';
244 
          when 125 => clk <= '0';
245 
          when 126 => clk <= '1';
246 
          when 127 => clk <= '0'; dio <= '0';
247 
          when 128 => clk <= '1';
248 
          when 129 => clk <= '0';
249 
          when 130 => clk <= '1';
250 
          when 131 => clk <= '0';
251 
          when 132 => clk <= '1';
252 
          when 133 => clk <= '0'; dio <= '1';
253 
          when 134 => clk <= '1';
254 
          when 135 => clk <= '0'; dio <= 'Z';
255 
          when 136 => clk <= '1'; dio <= 'Z';
256 
          when 137 => clk <= '0'; dio <= '0';
257 
          when 138 => clk <= '1'; dio <= '0';
258 
          when 139 => clk <= '1'; dio <= '1';
259 
          when 140 => clk <= '1'; dio <= '1';
260 
          when 141 => clk <= '1'; dio <= '1';
261 
          when others => null;
262 
   end case;
263 
 
264 
        if sm_counter = 10000 then
265 
                sm_counter <= 0;
266 
        else
267 
                sm_counter <= sm_counter + 1;
268 
        end if;
269 
 
270 
        if sm_counter = 9999 then
271 
                rdy <= '1';
272 
        else
273 
                rdy <= '0';
274 
        end if;
275 
 
276 
  end if;
277 
  end if;
278 
 end process;
279 
 
280 
 process(clk25)
281 
  begin
282 
  if rising_edge(clk25) then
283 
        if rdy = '1' then
284 
         if (ce ='1') then
285 
                reg_digit0 <= data(3 downto 0);
286 
                reg_digit1 <= data(7 downto 4);
287 
                reg_digit2 <= data(11 downto 8);
288 
                reg_digit3 <= data(15 downto 12);
289 
        end if;
290 
  end if;
291 
  end if;
292 
  end process;
293 
 
294 
end Behavioral;

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