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https://opencores.org/ocsvn/tm1637/tm1637/trunk
[/] [tm1637/] [trunk/] [hdl/] [intel_qp/] [dec_counter/] [tm1637_nativelink_simulation.rpt] - Blame information for rev 3
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Info: Start Nativelink Simulation process
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Info: NativeLink has detected VHDL design -- VHDL simulation models will be used
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========= EDA Simulation Settings =====================
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Sim Mode : RTL
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Family : cycloneive
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Quartus root : /home/mongoq/projects/fpga/intelFPGA_lite/20.1/quartus/linux64/
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Quartus sim root : /home/mongoq/projects/fpga/intelFPGA_lite/20.1/quartus/eda/sim_lib
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Simulation Tool : modelsim-altera
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Simulation Language : vhdl
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Version : 93
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Simulation Mode : GUI
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Sim Output File :
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Sim SDF file :
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Sim dir : simulation/modelsim
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=======================================================
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Info: Starting NativeLink simulation with ModelSim-Altera software
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Sourced NativeLink script /home/mongoq/projects/fpga/intelFPGA_lite/20.1/quartus/common/tcl/internal/nativelink/modelsim.tcl
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Info: Spawning ModelSim-Altera Simulation software
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Info: NativeLink simulation flow was successful
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