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[/] [tms1000/] [trunk/] [rtl/] [tms1000_tb.v] - Blame information for rev 3

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// This file is part of TMS1000 CPU
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// 
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// tms1000_tb.v -  Testbench for the TMS1000 processor
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//
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// Written By -  Nand Gates (2021)
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the
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// Free Software Foundation; either version 2, or (at your option) any
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// later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// In other words, you are welcome to use, share and improve this program.
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// You are forbidden to forbid anyone else to use, share and improve
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// what you give them.   Help stamp out software-hoarding!
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module tms1000_tb();
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   /*AUTOREGINPUT*/
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   // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
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   reg         clk;                    // To tms1000 of tms1000.v
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   tri0 [3:0]  k;                      // To tms1000 of tms1000.v
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   reg         reset_n;                // To tms1000 of tms1000.v
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   // End of automatics
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   /*AUTOWIRE*/
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   // Beginning of automatic wires (for undeclared instantiated-module outputs)
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   wire [7:0]  q;                      // From tms1000 of tms1000.v
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   wire [10:0] r;                      // From tms1000 of tms1000.v
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   // End of automatics
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   parameter key_0 = 5'h00;
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   parameter key_1 = 5'h01;
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   parameter key_2 = 5'h02;
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   parameter key_3 = 5'h03;
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   parameter key_4 = 5'h04;
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   parameter key_5 = 5'h05;
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   parameter key_6 = 5'h06;
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   parameter key_7 = 5'h07;
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   parameter key_8 = 5'h08;
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   parameter key_9 = 5'h09;
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   parameter key_clk   = 5'h0a;
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   parameter key_c     = 5'h0b;
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   parameter key_ent   = 5'h0c;
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   parameter key_plus  = 5'h0d;
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   parameter key_minus = 5'h0e;
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   parameter key_mul   = 5'h0f;
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   parameter key_div   = 5'h10;
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   reg         key0     ;
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   reg         key1     ;
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   reg         key2     ;
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   reg         key3     ;
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   reg         key4     ;
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   reg         key5     ;
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   reg         key6     ;
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   reg         key7     ;
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   reg         key8     ;
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   reg         key9     ;
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   reg         keyclk   ;
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   reg         keyc     ;
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   reg         keyent   ;
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   reg         keyplus  ;
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   reg         keyminus ;
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   reg         keymul   ;
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   reg         keydiv   ;
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   reg         clk_60;
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   integer     count;
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   reg [7:0]   d0, d1, d2, d3, d4, d5, d6, d7, d8;
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   tms1000 tms1000(/*AUTOINST*/
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                   // Outputs
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                   .r           (r[10:0]),
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                   .q           (q[7:0]),
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                   // Inputs
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                   .clk         (clk),
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                   .reset_n     (reset_n),
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                   .k           (k[3:0]));
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   bufif1 buf0 (k[2], key0    , r[0]);
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   bufif1 buf1 (k[2], key1    , r[1]);
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   bufif1 buf2 (k[2], key2    , r[2]);
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   bufif1 buf3 (k[2], key3    , r[3]);
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   bufif1 buf4 (k[2], key4    , r[4]);
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   bufif1 buf5 (k[2], key5    , r[5]);
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   bufif1 buf6 (k[2], key6    , r[6]);
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   bufif1 buf7 (k[1], key7    , r[1]);
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   bufif1 buf8 (k[1], key8    , r[2]);
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   bufif1 buf9 (k[1], key9    , r[3]);
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   bufif1 buf10(k[0], keyclk  , r[0]);
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   bufif1 buf11(k[0], keyc    , r[1]);
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   bufif1 buf12(k[0], keyent  , r[2]);
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   bufif1 buf13(k[0], keyplus , r[3]);
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   bufif1 buf14(k[0], keyminus, r[4]);
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   bufif1 buf15(k[0], keymul  , r[5]);
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   bufif1 buf16(k[0], keydiv  , r[6]);
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   bufif1 bufclk (k[3], clk_60 , 1'b1);
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   task do_key;
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      input [4:0] key;
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      begin
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          case (key)
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              key_0     : begin key0    <= 1'b1 ; #25000; key0    <= 1'b0; end
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              key_1     : begin key1    <= 1'b1 ; #25000; key1    <= 1'b0; end
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              key_2     : begin key2    <= 1'b1 ; #25000; key2    <= 1'b0; end
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              key_3     : begin key3    <= 1'b1 ; #25000; key3    <= 1'b0; end
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              key_4     : begin key4    <= 1'b1 ; #25000; key4    <= 1'b0; end
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              key_5     : begin key5    <= 1'b1 ; #25000; key5    <= 1'b0; end
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              key_6     : begin key6    <= 1'b1 ; #25000; key6    <= 1'b0; end
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              key_7     : begin key7    <= 1'b1 ; #25000; key7    <= 1'b0; end
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              key_8     : begin key8    <= 1'b1 ; #25000; key8    <= 1'b0; end
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              key_9     : begin key9    <= 1'b1 ; #25000; key9    <= 1'b0; end
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              key_clk   : begin keyclk  <= 1'b1 ; #25000; keyclk  <= 1'b0; end
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              key_c     : begin keyc    <= 1'b1 ; #25000; keyc    <= 1'b0; end
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              key_ent   : begin keyent  <= 1'b1 ; #25000; keyent  <= 1'b0; end
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              key_plus  : begin keyplus <= 1'b1 ; #25000; keyplus <= 1'b0; end
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              key_minus : begin keyminus<= 1'b1 ; #25000; keyminus<= 1'b0; end
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              key_mul   : begin keymul  <= 1'b1 ; #25000; keymul  <= 1'b0; end
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              key_div   : begin keydiv  <= 1'b1 ; #25000; keydiv  <= 1'b0; end
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          endcase // case(key)
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      end
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   endtask // do_key
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   initial begin
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      clk = 0;
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      key0     = 0;
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      key1     = 0;
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      key2     = 0;
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      key3     = 0;
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      key4     = 0;
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      key5     = 0;
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      key6     = 0;
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      key7     = 0;
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      key8     = 0;
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      key9     = 0;
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      keyclk   = 0;
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      keyc     = 0;
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      keyent   = 0;
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      keyplus  = 0;
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      keyminus = 0;
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      keymul   = 0;
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      keydiv   = 0;
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      clk_60 = 0;
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      count = 0;
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      d0 = 0;
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      d1 = 0;
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      d2 = 0;
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      d3 = 0;
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      d4 = 0;
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      d5 = 0;
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      d6 = 0;
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      d7 = 0;
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      d8 = 0;
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      reset_n = 0;
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      #33 reset_n = 1;
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/* -----\/----- EXCLUDED -----\/-----
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       #28000;
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       do_key(key_1);
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       #28000;
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       do_key(key_2);
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       #28000;
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       do_key(key_3);
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       #28000;
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       do_key(key_4);
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       #28000;
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       do_key(key_5);
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       #28000;
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       do_key(key_6);
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       #28000;
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       do_key(key_7);
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       #28000;
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       do_key(key_8);
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       #28000;
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       do_key(key_9);
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 -----/\----- EXCLUDED -----/\----- */
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/* -----\/----- EXCLUDED -----\/-----
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         do_key(key_2);
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         #28000;
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         do_key(key_ent);
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         #28000;
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         do_key(key_4);
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         #28000;
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         do_key(/-*key_minus key_plus*-/ key_mul);
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        #80000;
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        $display("Xreg_0 = %h",tms1000_tb.tms1000.ram.Xreg_0[63:0]);
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        $display("Xreg_1 = %h",tms1000_tb.tms1000.ram.Xreg_1[63:0]);
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        $display("Xreg_2 = %h",tms1000_tb.tms1000.ram.Xreg_2[63:0]);
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        $display("Xreg_3 = %h",tms1000_tb.tms1000.ram.Xreg_3[63:0]);
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        $finish;
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 -----/\----- EXCLUDED -----/\----- */
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   end // initial begin
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   always @(r) begin
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      case (1'b1)
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        r[0] : d0 = q;
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        r[1] : d1 = q;
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        r[2] : d2 = q;
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        r[3] : d3 = q;
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        r[4] : d4 = q;
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        r[5] : d5 = q;
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        r[6] : d6 = q;
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        r[7] : d7 = q;
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        r[8] : d8 = q;
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      endcase
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   end
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   always #5 clk = ~clk;
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   always @(posedge clk)
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     if (count == 1000) begin
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        clk_60 <= ~clk_60;
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        count <= 0;
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     end else
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        count <= count + 1;
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endmodule // tms1000_tb

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