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1 3 nand_gates
// This file is part of TMS1000 CPU
2
// 
3
// tms1000.v -  Hadrware description of the TMS1000 processor
4
//              used in SR16 calculator
5
// Written By -  Nand Gates (2021)
6
//
7
// This program is free software; you can redistribute it and/or modify it
8
// under the terms of the GNU General Public License as published by the
9
// Free Software Foundation; either version 2, or (at your option) any
10
// later version.
11
//
12
// This program is distributed in the hope that it will be useful,
13
// but WITHOUT ANY WARRANTY; without even the implied warranty of
14
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
// GNU General Public License for more details.
16
//
17
// In other words, you are welcome to use, share and improve this program.
18
// You are forbidden to forbid anyone else to use, share and improve
19
// what you give them.   Help stamp out software-hoarding!
20
module tms1000(/*AUTOARG*/
21
   // Outputs
22
   r, q,
23
   // Inputs
24
   clk, reset_n, k
25
   );
26
   input clk, reset_n;
27
   output [12:0] r;
28
   input [3:0]   k;
29
   output [7:0]  q;
30
 
31
   reg [7:0]  q;
32
   reg [12:0] r, r_nx;
33
   reg [3:0]  pa, pa_nx; // Page address register
34
   reg [3:0]  pb, pb_nx; // Page buffer register
35
   //reg [5:0]   pc, pc_nx; // Program counter
36
   reg [5:0]  sr, sr_nx; // Subroutine return register
37
   reg        cl, cl_nx; //  Call latch
38
   reg [1:0]  xx, xx_nx; //  
39
   reg [3:0]  y , y_nx ; // pointer/storage register 
40
   reg        s , s_nx ; // Logic status
41
   reg        sl, sl_nx; // Conditional branch status
42
   reg [3:0]  a , a_nx ; // Accumulator
43
   reg [3:0]  k_reg;
44
 
45
   //microinstructions
46
   reg ckp  ;
47
   reg ytp  ;
48
   reg mtp  ;
49
   reg atn  ;
50
   reg natn ;
51
   reg mtn  ;
52
   reg ftn  ;
53
   reg ckn  ;
54
   reg cin  ;
55
   reg ne   ;
56
   reg c8   ;
57
   reg sto  ;
58
   reg ckm  ;
59
   reg auta ;
60
   reg auty ;
61
   reg stsl ;
62
 
63
   reg [3:0] n_mux; // Multiplexer downto adder
64
   reg [3:0] p_mux; // Multiplexer downto adder
65
 
66
   reg       br    ;
67
   reg       call  ;
68
   reg       clo   ;
69
   reg       comx  ;
70
   reg       ldp   ;
71
   reg       ldx   ;
72
   reg       sbit  ;
73
   reg       rbit  ;
74
   reg       retn  ;
75
   reg       rstr  ;
76
   reg       setr  ;
77
   reg       tdo   ;
78
   reg       alec  ;
79
   reg       alem  ;
80
   reg       amaac ;
81
   reg       a6aac ;
82
   reg       a8aac ;
83
   reg       a10aac;
84
   reg       cla   ;
85
   reg       cpaiz ;
86
   reg       dan   ;
87
   reg       dman  ;
88
   reg       dyn   ;
89
   reg       ia    ;
90
   reg       imac  ;
91
   reg       iyc   ;
92
   reg       knez  ;
93
   reg       mnez  ;
94
   reg       saman ;
95
   reg       tam   ;
96
   reg       tamiy ;
97
   reg       tamza ;
98
   reg       tay   ;
99
   reg       tbit1 ;
100
   reg       tcy   ;
101
   reg       tcmiy ;
102
   reg       tka   ;
103
   reg       tma   ;
104
   reg       tmy   ;
105
   reg       tya   ;
106
   reg       xma   ;
107
   reg       ynea  ;
108
   reg       ynec  ;
109
   //T state generator
110
   reg [2:0] count;
111
   wire      t1 = count[0];
112
   wire      t2 = count[1];
113
   wire      t3 = count[2];
114
 
115
   wire [3:0] ram_do;
116
   wire [5:0] pc;
117
 
118
   reg  w2pc  ;
119
   reg  sr2pc ;
120
   reg  ld_sr ;
121
   reg  ld_pa ;
122
   reg  ld_pb ;
123
   reg  cl_set;
124
   reg  cl_reset;
125
   reg  set_s;
126
   reg [4:0] o, o_nx;
127
 
128
   wire      status;
129
   wire [3:0] alu_out;
130
   wire [7:0] i_bus;
131
   reg [3:0]  cki_bus;
132
   reg [3:0]  ram_din;
133
   wire       ram_wr;
134
 
135
   always @(posedge clk or negedge reset_n)
136
     if (!reset_n)
137
       count <= 0;
138
     else
139
       count <= {count[1:0],~|count[1:0]};
140
/* -----\/----- EXCLUDED -----\/-----
141
RETN
142
   pa = pb;
143
   if (cl == 1)
144
      pc = sr;
145
      cl = 0;
146
   else if (cl = 0)
147
      pc = pc + 1;
148
 
149
BR
150
  if (s == 1)
151
     pc = w;
152
     if (cl==0)
153
       pa = pb;
154
  else if (s == 0)
155
     pc = pc+1;
156
     s = 1;
157
 
158
CALL
159
    if (s == 1) & (cl == 0)
160
       sr = pc + 1;
161
       pc = w;
162
       pb = pa;
163
       pa = pb;
164
       cl = 1;
165
     else if (s == 1) & (cl == 1)
166
       pc = w;
167
       pb = pa;
168
     else if (s == 0)
169
       pc = pc + 1;
170
       s = 1;
171
 -----/\----- EXCLUDED -----/\----- */
172
 
173
   always @(/*AS*/br or call or cl or ldx or retn or s) begin
174
      //PC select
175
      w2pc = (br | call) & s;
176
      sr2pc = retn & cl;
177
      //sr select
178
      ld_sr = call & s & ~cl;
179
      //pa select
180
      ld_pa = retn | (((br & ~cl)|call) & s);
181
      //pb select
182
      ld_pb =  (call & s);
183
      //cl select
184
      cl_set   = call & s & ~cl;
185
      cl_reset = retn & cl;
186
      //s
187
      set_s = br | call | ldx | comx |
188
              tam | tamza | tka | tdo | clo |
189
              rstr | setr | ia | retn | ldp |
190
              tamiy | tma | tmy | tya | tay |
191
              xma | cla | sbit | rbit | ldx |
192
              tcy | tcmiy;
193
   end
194
 
195
   // Main registers
196
   always @(posedge clk or negedge reset_n) begin
197
       if (!reset_n) begin
198
          pa <= 4'b1111;
199
          pb <= 4'b1111;
200
          sr <= 6'b00_0000;
201
          r  <= 11'b00000000000;
202
          o  <= 5'b00000;
203
          cl <= 1'b0;
204
          s  <= 1'b1; // s=0 on power on
205
          sl <= 1'b0;
206
          a  <= 4'b0000;
207
          y  <= 4'b0000;
208
          xx <= 2'b00;
209
          k_reg <= 4'b0000;
210
       end else begin // if (!reset_n)
211
          pa <= pa_nx;
212
          pb <= pb_nx;
213
          sr <= sr_nx;
214
          r  <= r_nx;
215
          o  <= o_nx;
216
          a  <= a_nx;
217
          y  <= y_nx;
218
          xx <= xx_nx;
219
          sl <= sl_nx;
220
          cl <= cl_nx;
221
          s  <= s_nx;
222
          k_reg <= k;
223
       end
224
   end // always @ (posedge clk or negedge reset_n)
225
 
226
   //pa pb sr cl
227
   always @(/*AS*/c8 or cl or cl_reset or cl_set or ld_pa or ld_pb or ld_sr
228
            or ne or pa or pb or pc or s or set_s or sr or status or t3 or t3) begin
229
      pa_nx = pa;
230
      pb_nx = pb;
231
      sr_nx = sr;
232
      cl_nx = cl;
233
      s_nx = s;
234
 
235
      if (ld_sr & t3)
236
        sr_nx = {pc[4:0], !((pc != 31) && (|pc[5:4]) && ((pc[3:0] == 15) || (pc[5:4] != 3)))};
237
 
238
      if (ld_pa & t3)
239
        pa_nx = pb;
240
 
241
      if (ld_pb & t3)
242
        pb_nx = pa;
243
      else if (ldp & t3)
244
        pb_nx = {i_bus[0],i_bus[1],i_bus[2],i_bus[3]};
245
 
246
      if (cl_set & t3)
247
        cl_nx = 1'b1;
248
      else if (cl_reset & t3)
249
        cl_nx = 1'b0;
250
 
251
      if (t3 & (c8 | ne))
252
        s_nx = status;
253
      else if (set_s & t3)
254
        s_nx = 1'b1;
255
   end // always @ (...
256
 
257
   always @(/*AS*/a or alu_out or auta or t3) begin
258
       a_nx = a;
259
       if (auta & t3)
260
         a_nx = alu_out;
261
   end
262
 
263
   always @(/*AS*/alu_out or auty or t3 or y) begin
264
      y_nx = y;
265
      if (auty & t3)
266
        y_nx = alu_out;
267
   end
268
 
269
   always @ (/*AS*/status or sl or stsl) begin
270
      sl_nx = sl;
271
      if (stsl)
272
        sl_nx = status;
273
   end
274
 
275
   always @(/*AS*/comx or i_bus or ldx or t3 or xx) begin
276
      xx_nx = xx;
277
      if (ldx & t3)
278
        xx_nx = {i_bus[0],i_bus[1]};
279
      else if (comx & t3)
280
        xx_nx = ~xx;
281
   end
282
 
283
   always @(/*AS*/a or clo or o or sl or tdo) begin
284
       o_nx = o;
285
       if (clo)
286
         o_nx = 0;
287
       else if (tdo)
288
         o_nx = {sl, a};
289
   end
290
 
291
   // Instruction decoder CPLD and logic
292
   always @(/*AS*/i_bus) begin
293
      br     = 1'b0;
294
      call   = 1'b0;
295
      clo    = 1'b0;
296
      comx   = 1'b0;
297
      ldp    = 1'b0;
298
      ldx    = 1'b0;
299
      sbit   = 1'b0;
300
      rbit   = 1'b0;
301
      retn   = 1'b0;
302
      rstr   = 1'b0;
303
      setr   = 1'b0;
304
      tdo    = 1'b0;
305
      alec   = 1'b0;
306
      alem   = 1'b0;
307
      amaac  = 1'b0;
308
      a6aac  = 1'b0;
309
      a8aac  = 1'b0;
310
      a10aac = 1'b0;
311
      cla    = 1'b0;
312
      cpaiz  = 1'b0;
313
      dan    = 1'b0;
314
      dman   = 1'b0;
315
      dyn    = 1'b0;
316
      ia     = 1'b0;
317
      imac   = 1'b0;
318
      iyc    = 1'b0;
319
      knez   = 1'b0;
320
      mnez   = 1'b0;
321
      saman  = 1'b0;
322
      tam    = 1'b0;
323
      tamiy  = 1'b0;
324
      tamza  = 1'b0;
325
      tay    = 1'b0;
326
      tbit1  = 1'b0;
327
      tcy    = 1'b0;
328
      tcmiy  = 1'b0;
329
      tka    = 1'b0;
330
      tma    = 1'b0;
331
      tmy    = 1'b0;
332
      tya    = 1'b0;
333
      xma    = 1'b0;
334
      ynea   = 1'b0;
335
      ynec   = 1'b0;
336
      casex(i_bus[7:0])
337
        //Fixed instructions
338
        8'b10xx_xxxx : br   = 1'b1;
339
        8'b11xx_xxxx : call = 1'b1;
340
        8'b0000_1011 : clo  = 1'b1;
341
        8'b0000_0000 : comx = 1'b1;
342
        8'b0001_xxxx : ldp  = 1'b1;
343
        8'b0011_11xx : ldx  = 1'b1;
344
        8'b0011_00xx : sbit = 1'b1;
345
        8'b0011_01xx : rbit = 1'b1;
346
        8'b0000_1111 : retn = 1'b1;
347
        8'b0000_1100 : rstr = 1'b1;
348
        8'b0000_1101 : setr = 1'b1;
349
        8'b0000_1010 : tdo  = 1'b1;
350
        // Programable instructions
351
        8'b0111_xxxx : alec   = 1'b1;
352
        8'b0010_1001 : alem   = 1'b1;
353
        8'b0010_0101 : amaac  = 1'b1;
354
        8'b0000_0110 : a6aac  = 1'b1;
355
        8'b0000_0001 : a8aac  = 1'b1;
356
        8'b0000_0101 : a10aac = 1'b1;
357
        8'b0010_1111 : cla    = 1'b1;
358
        8'b0010_1101 : cpaiz  = 1'b1;
359
        8'b0000_0111 : dan    = 1'b1;
360
        8'b0010_1010 : dman   = 1'b1;
361
        8'b0010_1100 : dyn    = 1'b1;
362
        8'b0000_1110 : ia     = 1'b1;
363
        8'b0010_1000 : imac   = 1'b1;
364
        8'b0010_1011 : iyc    = 1'b1;
365
        8'b0000_1001 : knez   = 1'b1;
366
        8'b0010_0110 : mnez   = 1'b1;
367
        8'b0010_0111 : saman  = 1'b1;
368
        8'b0000_0011 : tam    = 1'b1;
369
        8'b0010_0000 : tamiy  = 1'b1;
370
        8'b0000_0100 : tamza  = 1'b1;
371
        8'b0010_0100 : tay    = 1'b1;
372
        8'b0011_10xx : tbit1  = 1'b1;
373
        8'b0100_xxxx : tcy    = 1'b1;
374
        8'b0110_xxxx : tcmiy  = 1'b1;
375
        8'b0000_1000 : tka    = 1'b1;
376
        8'b0010_0001 : tma    = 1'b1;
377
        8'b0010_0010 : tmy    = 1'b1;
378
        8'b0010_0011 : tya    = 1'b1;
379
        8'b0010_1110 : xma    = 1'b1;
380
        8'b0000_0010 : ynea   = 1'b1;
381
        8'b0101_xxxx : ynec   = 1'b1;
382
        default : ;//nop
383
      endcase // case(i_bus[7:0])
384
   end // always @ (...
385
 
386
   // Instruction decoder PLA OR logic
387
   always @(/*AS*/a10aac or a6aac or a8aac or alec or alem or amaac or br
388
            or call or cla or clo or comx or cpaiz or dan or dman or dyn or ia
389
            or imac or iyc or knez or ldp or ldx or mnez or rbit or retn
390
            or rstr or saman or sbit or setr or tam or tamiy or tamza or tay
391
            or tbit1 or tcmiy or tcy or tdo or tka or tma or tmy or tya or xma
392
            or ynea or ynec) begin
393
      //active in t1      
394
      ckp  = 1'b0;
395
      ytp  = 1'b0;
396
      mtp  = 1'b0;
397
      atn  = 1'b0;
398
      natn = 1'b0;
399
      mtn  = 1'b0;
400
      ftn  = 1'b0;
401
      ckn  = 1'b0;
402
      cin  = 1'b0;
403
      ne   = 1'b0;
404
      c8   = 1'b0;
405
      // acrive during t2
406
      sto = 1'b0;
407
      ckm = 1'b0;
408
      //active during t3 
409
      auta = 1'b0;
410
      auty = 1'b0;
411
      stsl = 1'b0;
412
      case(1'b1)
413
        // Fixded instructions
414
        br     : begin
415
        end
416
        call   : begin
417
        end
418
        clo    : begin
419
        end
420
        comx   : begin
421
        end
422
        ldp    : begin
423
        end
424
        ldx    : begin
425
        end
426
        sbit   : begin
427
        end
428
        rbit   : begin
429
        end
430
        retn   : begin
431
        end
432
        rstr   : begin
433
        end
434
        setr   : begin
435
        end
436
        tdo    : begin
437
           auty =1'b1;
438
           ftn =1'b1;
439
           ytp =1'b1;
440
        end
441
        //Programable instructions
442
        tcy   : begin
443
           auty =1'b1;
444
           ckp =1'b1;
445
        end
446
 
447
        ynec  : begin
448
           ne =1'b1;
449
           ckn =1'b1;
450
           ytp =1'b1;
451
        end
452
 
453
        tcmiy : begin
454
           auty =1'b1;
455
           cin =1'b1;
456
           ytp =1'b1;
457
           ckm =1'b1;
458
        end
459
 
460
        alec  : begin
461
           cin =1'b1;
462
           c8 =1'b1;
463
           natn =1'b1;
464
           ckp =1'b1;
465
        end
466
 
467
        tamiy : begin
468
           auty =1'b1;
469
           cin =1'b1;
470
           ytp =1'b1;
471
           sto =1'b1;
472
        end
473
 
474
        tma   : begin
475
           auta =1'b1;
476
           mtp =1'b1;
477
        end
478
 
479
        tmy   : begin
480
           auty =1'b1;
481
           mtp =1'b1;
482
        end
483
 
484
        tya   : begin
485
           auta =1'b1;
486
           ytp =1'b1;
487
        end
488
 
489
        tay   : begin
490
           auty =1'b1;
491
           atn =1'b1;
492
        end
493
 
494
        xma    : begin
495
           mtp  = 1'b1;
496
           sto  = 1'b1;
497
           auta = 1'b1;
498
        end
499
 
500
        amaac : begin
501
           auta =1'b1;
502
           c8 =1'b1;
503
           atn =1'b1;
504
           mtp =1'b1;
505
        end
506
 
507
        mnez  : begin
508
           ne =1'b1;
509
           mtp =1'b1;
510
        end
511
 
512
        saman : begin
513
           auta =1'b1;
514
           cin =1'b1;
515
           c8 =1'b1;
516
           natn =1'b1;
517
           mtp =1'b1;
518
        end
519
 
520
        imac  : begin
521
           auta =1'b1;
522
           cin =1'b1;
523
           c8 =1'b1;
524
           mtp =1'b1;
525
        end
526
 
527
        alem   : begin
528
/* -----\/----- EXCLUDED -----\/-----
529
           mtp  = 1'b1;
530
           natn = 1'b1;
531
           cin  = 1'b1;
532
           c8   = 1'b1;
533
 -----/\----- EXCLUDED -----/\----- */
534
        end
535
 
536
        dman  : begin
537
           auta =1'b1;
538
           c8 =1'b1;
539
           ftn =1'b1;
540
           mtp =1'b1;
541
        end
542
 
543
        iyc   : begin
544
           auty =1'b1;
545
           cin =1'b1;
546
           c8 =1'b1;
547
           ytp =1'b1;
548
        end
549
 
550
        dyn   : begin
551
           auty =1'b1;
552
           c8 =1'b1;
553
           ftn =1'b1;
554
           ytp =1'b1;
555
        end
556
 
557
        cpaiz : begin
558
           natn = 1'b1;
559
           cin  = 1'b1;
560
           c8   = 1'b1;
561
           auta = 1'b1;
562
        end
563
 
564
        cla   : begin
565
           auta =1'b1;
566
        end
567
 
568
        tbit1 : begin
569
           ne =1'b1;
570
           ckn =1'b1;
571
           mtp =1'b1;
572
           ckp =1'b1;
573
        end
574
 
575
        a8aac : begin
576
           auta =1'b1;
577
           c8 =1'b1;
578
           atn =1'b1;
579
           ckp =1'b1;
580
        end
581
 
582
        a10aac : begin
583
           ckp  = 1'b1;
584
           atn  = 1'b1;
585
           c8   = 1'b1;
586
           auta = 1'b1;
587
        end
588
 
589
        ynea  : begin
590
           stsl =1'b1;
591
           ne =1'b1;
592
           atn =1'b1;
593
           ytp =1'b1;
594
        end
595
 
596
        tam   : begin
597
           sto =1'b1;
598
        end
599
 
600
        tamza : begin
601
           auta =1'b1;
602
           sto =1'b1;
603
        end
604
 
605
        a6aac : begin
606
           auta =1'b1;
607
           c8 =1'b1;
608
           atn =1'b1;
609
           ckp =1'b1;
610
        end
611
 
612
        dan   : begin
613
           auta =1'b1;
614
           cin =1'b1;
615
           c8 =1'b1;
616
           atn =1'b1;
617
           ckp =1'b1;
618
        end
619
 
620
        tka   : begin
621
           auta =1'b1;
622
           ckp =1'b1;
623
        end
624
 
625
        knez  : begin
626
           ne =1'b1;
627
           ckp =1'b1;
628
        end
629
 
630
        ia    : begin
631
           auta =1'b1;
632
           cin =1'b1;
633
           atn =1'b1;
634
        end
635
      endcase // case(1'b1)
636
   end
637
   //R-logic
638
   always @(/*AS*/r or rstr or setr or y) begin
639
       r_nx = r;
640
       if (setr | rstr)
641
         case (y)
642
 
643
              1 : r_nx[ 1] = setr & (~rstr);
644
              2 : r_nx[ 2] = setr & (~rstr);
645
              3 : r_nx[ 3] = setr & (~rstr);
646
              4 : r_nx[ 4] = setr & (~rstr);
647
              5 : r_nx[ 5] = setr & (~rstr);
648
              6 : r_nx[ 6] = setr & (~rstr);
649
              7 : r_nx[ 7] = setr & (~rstr);
650
              8 : r_nx[ 8] = setr & (~rstr);
651
              9 : r_nx[ 9] = setr & (~rstr);
652
             10 : r_nx[10] = setr & (~rstr);
653
             11 : r_nx[11] = setr & (~rstr);
654
             12 : r_nx[12] = setr & (~rstr);
655
         endcase
656
   end // always @ (...
657
 
658
   //Q output logic
659
   always @(/*AS*/o) begin
660
      case(o[3:0]) // abcd efg-SL
661
 
662
         1 : q = {7'b0110_000,~o[4]};   // seven-seg 1                f   b
663
         2 : q = {7'b1101_101,~o[4]};   // seven-seg 2                  g
664
         3 : q = {7'b1111_001,~o[4]};   // seven-seg 3                e   c
665
         4 : q = {7'b0110_011,~o[4]};   // seven-seg 4                  d
666
         5 : q = {7'b1011_011,~o[4]};   // seven-seg 5
667
         6 : q = {7'b1011_111,~o[4]};   // seven-seg 6
668
         7 : q = {7'b1110_000,~o[4]};   // seven-seg 7
669
         8 : q = {7'b1111_111,~o[4]};   // seven-seg 8
670
         9 : q = {7'b1111_011,~o[4]};   // seven-seg 9
671
        10 : q = {7'b0000_000,~o[4]};   // seven-seg Blank
672
        11 : q = {7'b0100_000,~o[4]};   // seven-seg '
673
        12 : q = {7'b1001_111,~o[4]};   // seven-seg E
674
        13 : q = {7'b1000_111,~o[4]};   // seven-seg F
675
        14 : q = {7'b0000_001,~o[4]};   // seven-seg -
676
        15 : q = {7'b0100_001,~o[4]};   // seven-seg -'
677
      endcase
678
   end // always @ (...
679
 
680
   //cki_bus logic
681
   always @ (/*AS*/i_bus or k_reg) begin
682
      if (i_bus[7:3] == 5'b00000|| i_bus[7:6] == 2'b01)
683
        cki_bus = {i_bus[0],i_bus[1],i_bus[2],i_bus[3]};
684
      else if (i_bus[7:3] == 5'b00001)
685
        cki_bus = k_reg;
686
      else if (i_bus[7:4] == 4'h3)
687
        case ({i_bus[0],i_bus[1]})
688
 
689
          1 : cki_bus = 4'b1101;
690
          2 : cki_bus = 4'b1011;
691
          3 : cki_bus = 4'b0111;
692
        endcase // case ({i_bus[0],i_bus[1]})
693
      else //if (i_bus[7:4] == 4'h2)
694
        cki_bus = 0;
695
   end
696
 
697
   // N-mux
698
   always @ (/*AS*/a or atn or cki_bus or ckn or ftn or mtn or natn or ram_do) begin
699
       n_mux = (a & {4{atn}}) | (~a & {4{natn}}) |
700
               (ram_do & {4{mtn}}) | ({4{ftn}}) |
701
               (cki_bus & {4{ckn}});
702
   end
703
 
704
   //P-mux
705
   always @ (/*AS*/cki_bus or ckp or mtp or ram_do or y or ytp) begin
706
       p_mux = (cki_bus & {4{ckp}}) | (y & {4{ytp}}) |
707
               (ram_do & {4{mtp}});
708
   end
709
 
710
   assign ram_wr = (sto | ckm | sbit | rbit) & t3;
711
   //write mux
712
   always @(/*AS*/a or cki_bus or ckm or ram_do or rbit or sbit or sto)begin
713
      ram_din = cki_bus & {4{ckm}} | (a & {4{sto}}) |
714
                {4{sbit}} & (~cki_bus | ram_do) |
715
                {4{rbit}} & (cki_bus & ram_do);
716
   end
717
   alu alu(
718
        // Outputs
719
        .sum (alu_out),
720
        .status (status),
721
        // Inputs
722
        .a (n_mux),
723
        .b (p_mux),
724
        .cin (cin),
725
        .cy_out (c8),
726
        .comp_out (ne)
727
        );
728
 
729
   rom rom (
730
            // Outputs
731
            .data (i_bus),
732
            // Inputs
733
            .address ({pa,pc})
734
            );
735
 
736
   ram ram (
737
            // Outputs
738
            .dout (ram_do),
739
            // Inputs
740
            .clk (clk),
741
            .reset_n (reset_n),
742
            .wr (ram_wr),
743
            .din (ram_din),
744
            .addr ({xx,y})
745
            );
746
   tms1000_pc tms1000_pc(
747
                         // Outputs
748
                         .pc  (pc),
749
                         // Inputs
750
                         .clk (clk),
751
                         .reset_n (reset_n),
752
                         .ld_pc ((w2pc | sr2pc) & t3),
753
                         .pc_en (t3),
754
                         .din   (({6{w2pc}} & i_bus[5:0]) | ({6{sr2pc}} & sr))
755
                         );
756
 
757
   // for debug only
758
/* -----\/----- EXCLUDED -----\/-----
759
   //reg [100*8:1] instruction[0:2047];
760
   reg [100*8:1] instruction;
761
   reg [3:0]   imm;
762
   reg         imm_f;
763
   initial $readmemh("icalc.mem",instruction);
764
   always @(pa or pc) begin
765
       $write ($time,,"%x %0s\t",{pa,pc},instruction[{pa,pc}]);
766
   end
767
   always @(negedge t3) begin
768
       $display("x=%x y=%x a=%x m(%0d,%0d)=%x s=%b pa=%x pb=%x cl=%b", xx, y, a, xx, y, ram_do, s, pa, pb, cl);
769
   end
770
 
771
   always @(negedge clk) begin
772
       if (t1) begin
773
           case(1'b1)
774
               // Fixded instructions
775
               br     : begin instruction = "br    "; imm_f = 1; imm = i_bus[7:4];end
776
               call   : begin instruction = "call  "; imm_f = 1; imm = i_bus[7:4];end
777
               clo    : begin instruction = "clo   "; imm_f = 0; imm = 0;end
778
               comx   : begin instruction = "comx  "; imm_f = 0; imm = 0;end
779
               ldp    : begin instruction = "ldp   "; imm_f = 1; imm = {i_bus[0],i_bus[1],i_bus[2],i_bus[3]};end
780
               ldx    : begin instruction = "ldx   "; imm_f = 1; imm = {i_bus[0],i_bus[1]};end
781
               sbit   : begin instruction = "sbit  "; imm_f = 1; imm = {i_bus[0],i_bus[1]};end
782
               rbit   : begin instruction = "rbit  "; imm_f = 1; imm = {i_bus[0],i_bus[1]};end
783
               retn   : begin instruction = "retn  "; imm_f = 0; imm = 0;end
784
               rstr   : begin instruction = "rstr  "; imm_f = 0; imm = 0;end
785
               setr   : begin instruction = "setr  "; imm_f = 0; imm = 0;end
786
               tdo    : begin instruction = "tdo   "; imm_f = 0; imm = 0;end
787
               alec   : begin instruction = "alec  "; imm_f = 1; imm = {i_bus[0],i_bus[1],i_bus[2],i_bus[3]};end
788
               alem   : begin instruction = "alem  "; imm_f = 0; imm = 0;end
789
               amaac  : begin instruction = "amaac "; imm_f = 0; imm = 0;end
790
               a6aac  : begin instruction = "a6aac "; imm_f = 0; imm = 0;end
791
               a8aac  : begin instruction = "a8aac "; imm_f = 0; imm = 0;end
792
               a10aac : begin instruction = "a10aac"; imm_f = 0; imm = 0;end
793
               cla    : begin instruction = "cla   "; imm_f = 0; imm = 0;end
794
               cpaiz  : begin instruction = "cpaiz "; imm_f = 0; imm = 0;end
795
               dan    : begin instruction = "dan   "; imm_f = 0; imm = 0;end
796
               dman   : begin instruction = "dman  "; imm_f = 0; imm = 0;end
797
               dyn    : begin instruction = "dyn   "; imm_f = 0; imm = 0;end
798
               ia     : begin instruction = "ia    "; imm_f = 0; imm = 0;end
799
               imac   : begin instruction = "imac  "; imm_f = 0; imm = 0;end
800
               iyc    : begin instruction = "iyc   "; imm_f = 0; imm = 0;end
801
               knez   : begin instruction = "knez  "; imm_f = 0; imm = 0;end
802
               mnez   : begin instruction = "mnez  "; imm_f = 0; imm = 0;end
803
               saman  : begin instruction = "saman "; imm_f = 0; imm = 0;end
804
               tam    : begin instruction = "tam   "; imm_f = 0; imm = 0;end
805
               tamiy  : begin instruction = "tamiy "; imm_f = 0; imm = 0;end
806
               tamza  : begin instruction = "tamza "; imm_f = 0; imm = 0;end
807
               tay    : begin instruction = "tay   "; imm_f = 0; imm = 0;end
808
               tbit1  : begin instruction = "tbit1 "; imm_f = 1; imm = {i_bus[0],i_bus[1]};end
809
               tcy    : begin instruction = "tcy   "; imm_f = 1; imm = {i_bus[0],i_bus[1],i_bus[2],i_bus[3]};end
810
               tcmiy  : begin instruction = "tcmiy "; imm_f = 1; imm = {i_bus[0],i_bus[1],i_bus[2],i_bus[3]};end
811
               tka    : begin instruction = "tka   "; imm_f = 0; imm = 0;end
812
               tma    : begin instruction = "tma   "; imm_f = 0; imm = 0;end
813
               tmy    : begin instruction = "tmy   "; imm_f = 0; imm = 0;end
814
               tya    : begin instruction = "tya   "; imm_f = 0; imm = 0;end
815
               xma    : begin instruction = "xma   "; imm_f = 0; imm = 0;end
816
               ynea   : begin instruction = "ynea  "; imm_f = 0; imm = 0;end
817
               ynec   : begin instruction = "ynec  "; imm_f = 1; imm = {i_bus[0],i_bus[1],i_bus[2],i_bus[3]};end
818
           endcase // case(1'b1)
819
 
820
           if (imm_f)
821
             $display($time,,"%x %0s %d",{pa,pc},instruction, imm);
822
           else
823
             $display($time,,"%x %0s ",{pa,pc},instruction);
824
       end // if (t1)
825
   end // always @ (...
826
 -----/\----- EXCLUDED -----/\----- */
827
endmodule // tms1000
828
 
829
module alu (/*AUTOARG*/
830
   // Outputs
831
   sum, status,
832
   // Inputs
833
   a, b, cin, cy_out, comp_out
834
   );
835
   input [3:0] a;
836
   input [3:0] b;
837
   input       cin, cy_out, comp_out;
838
   output [3:0] sum;
839
   output       status;
840
   wire         cy;
841
   wire         ne = (a != b); //comparator
842
   assign       {cy, sum} = a + b + cin; // adder
843
   assign       status = (cy & cy_out) | (ne & comp_out);
844
endmodule // alu
845
 
846
module rom (/*AUTOARG*/
847
   // Outputs
848
   data,
849
   // Inputs
850
   address
851
   );
852
   input [9:0] address;
853
   output [7:0] data;
854
   reg [7:0]    memory [0:1023];
855
   initial $readmemh("sr16.mem", memory);
856
   assign       data = memory [address];
857
endmodule // rom
858
 
859
module ram (/*AUTOARG*/
860
   // Outputs
861
   dout,
862
   // Inputs
863
   clk, reset_n, wr, din, addr
864
   );
865
   input clk, reset_n;
866
   input wr;
867
   input [3:0] din;
868
   output [3:0] dout;
869
   input [5:0]  addr;
870
   reg [3:0]    ram_mem [0:63];
871
   assign       dout = ram_mem[addr];
872
 
873
//For debug only
874
/* -----\/----- EXCLUDED -----\/-----*/
875
   wire  [16*4-1:0]  Xreg_0 = {ram_mem[15], ram_mem[14], ram_mem[13], ram_mem[12], ram_mem[11], ram_mem[10], ram_mem[9], ram_mem[8], ram_mem[7], ram_mem[6], ram_mem[5], ram_mem[4], ram_mem[3], ram_mem[2], ram_mem[1], ram_mem[0]};
876
   wire  [16*4-1:0]  Xreg_1 = {ram_mem[31], ram_mem[30], ram_mem[29], ram_mem[28], ram_mem[27], ram_mem[26], ram_mem[25], ram_mem[24], ram_mem[23], ram_mem[22], ram_mem[21], ram_mem[20], ram_mem[19], ram_mem[18], ram_mem[17], ram_mem[16]};
877
   wire  [16*4-1:0]  Xreg_2 = {ram_mem[47], ram_mem[46], ram_mem[45], ram_mem[44], ram_mem[43], ram_mem[42], ram_mem[41], ram_mem[40], ram_mem[39], ram_mem[38], ram_mem[37], ram_mem[36], ram_mem[35], ram_mem[34], ram_mem[33], ram_mem[32]};
878
   wire  [16*4-1:0]  Xreg_3 = {ram_mem[63], ram_mem[62], ram_mem[61], ram_mem[60], ram_mem[59], ram_mem[58], ram_mem[57], ram_mem[56], ram_mem[55], ram_mem[54], ram_mem[53], ram_mem[52], ram_mem[51], ram_mem[50], ram_mem[49], ram_mem[48]};
879
/* -----/\----- EXCLUDED -----/\----- */
880
 
881
   always @(posedge clk or negedge reset_n) begin
882
       if (!reset_n ) begin
883
           begin : mem_init_loop
884
              integer i;
885
               for (i=0; i<64; i=i+1)
886
               ram_mem[i] <= i;
887
           end
888
       end else begin
889
           if (wr)
890
             ram_mem[addr] <= din;
891
       end
892
   end
893
endmodule // ram
894
 
895
 
896
module tms1000_pc (/*AUTOARG*/
897
   // Outputs
898
   pc,
899
   // Inputs
900
   clk, reset_n, ld_pc, pc_en, din
901
   );
902
   input clk, reset_n;
903
   input ld_pc, pc_en;
904
   input [5:0] din;
905
   output [5:0] pc;
906
   reg [5:0] pc;
907
   wire         a = ~&{~pc[5], pc[4:0]};
908
   wire         b = |pc[5:4];
909
   wire         c = ~&{(~&pc[3:0]),pc[5:4]};
910
   wire         sin = ~&{a, b, c};
911
   always @(posedge clk or negedge reset_n) begin
912
      if (!reset_n)
913
        pc <= 0;
914
      else
915
        if (ld_pc)
916
          pc <= din;
917
        else if (pc_en)
918
          pc <= {pc[4:0], sin};
919
   end
920
endmodule // tms1000_pc
921
 

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