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sonicwave |
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-- Company: University of Southern Denmark
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-- Engineer: Simon Falsig
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--
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-- Create Date: 7/3/2010
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-- Design Name: TosNet
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-- Module Name: tdl_top - Behavioral
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-- File Name: tdl_top.vhd
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-- Project Name: TosNet
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-- Target Devices: Spartan3/6
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-- Tool versions: Xilinx ISE 12.2
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-- Description: The datalink layer implementation and physical layer wrapper
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-- for the TosNet stack.
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--
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-- Revision:
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-- Revision 3.2 - Initial release
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--
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-- Copyright 2010
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--
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-- This module is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU Lesser General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This module is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with this module. If not, see <http://www.gnu.org/licenses/>.
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--------------------------------------------------------------------------------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use work.crcpack.all;
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use work.commandpack.all;
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entity tdl_top is
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Port( node_id : in STD_LOGIC_VECTOR(3 downto 0);
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reg_enable : in STD_LOGIC_VECTOR(7 downto 0);
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watchdog_threshold : in STD_LOGIC_VECTOR(17 downto 0);
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data_out_ext : out STD_LOGIC_VECTOR(7 downto 0);
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data_out_strobe_ext : out STD_LOGIC;
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data_out_enable_ext : out STD_LOGIC;
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data_in_ext : in STD_LOGIC_VECTOR(7 downto 0);
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data_in_strobe_ext : in STD_LOGIC;
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data_in_enable_ext : in STD_LOGIC;
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buffer_full : inout STD_LOGIC;
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packet_error : inout STD_LOGIC;
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force_packet_error : inout STD_LOGIC;
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sync_strobe : inout STD_LOGIC;
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online : out STD_LOGIC;
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network_reg_addr : in STD_LOGIC_VECTOR(3 downto 0);
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network_reg_data : out STD_LOGIC_VECTOR(31 downto 0);
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network_reg_clk : in STD_LOGIC;
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node_is_master : out STD_LOGIC;
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node_address : out STD_LOGIC_VECTOR(3 downto 0);
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clk_50M : in STD_LOGIC;
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reset : in STD_LOGIC;
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sig_in : in STD_LOGIC;
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sig_out : inout STD_LOGIC);
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end tdl_top;
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architecture Behavioral of tdl_top is
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attribute buffer_type: string;
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attribute buffer_type of network_reg_clk: signal is "none"; --Make sure that the network register clock doesn't use a GCLK
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type MAIN_STATES is (IDLE, MASTER_DSC, NET_DSC, REG_DSC, SYNC_DSC, DATA, ERROR);
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type TX_STATES is (IDLE, DATA_CMD, DATA, CRC, ERROR);
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type RX_STATES is (IDLE, CMD, DATA, CRC, ERROR);
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signal main_state : MAIN_STATES := IDLE;
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signal next_main_state : MAIN_STATES := IDLE;
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signal tx_state : TX_STATES := IDLE;
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signal next_tx_state : TX_STATES := IDLE;
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signal rx_state : RX_STATES := IDLE;
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signal next_rx_state : RX_STATES := IDLE;
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signal tx_data : STD_LOGIC_VECTOR(7 downto 0);
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signal tx_clk_en : STD_LOGIC;
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signal tx_enable : STD_LOGIC;
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signal tx_clk_div_reset : STD_LOGIC;
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signal tx_clk_div_reset_ack : STD_LOGIC;
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signal rx_data : STD_LOGIC_VECTOR(7 downto 0);
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signal rx_error : STD_LOGIC;
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signal rx_valid : STD_LOGIC;
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signal rx_clk : STD_LOGIC;
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signal rx_cmd_valid : STD_LOGIC;
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signal rx_cmd_valid_buffer_1: STD_LOGIC;
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signal rx_cmd_valid_buffer_2: STD_LOGIC;
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signal main_counter : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
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signal last_tx_clk_en : STD_LOGIC;
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signal last_rx_clk : STD_LOGIC;
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signal last_data_in_strobe : STD_LOGIC;
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signal input_buffer : STD_LOGIC_VECTOR(7 downto 0);
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signal data_buffer : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
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signal data_out_buffer_1 : STD_LOGIC_VECTOR(7 downto 0);
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signal data_out_buffer_2 : STD_LOGIC_VECTOR(7 downto 0);
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signal data_out_enable_buffer_1 : STD_LOGIC;
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signal data_out_enable_buffer_2 : STD_LOGIC;
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signal crcgen_rx_output_buffer : STD_LOGIC_VECTOR(7 downto 0);
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signal data_buffer_counter : STD_LOGIC := '0';
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signal input_available : STD_LOGIC;
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signal internal_reset : STD_LOGIC := '0';
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signal do_internal_reset : STD_LOGIC := '0';
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signal watchdog_counter : STD_LOGIC_VECTOR(17 downto 0) := "000000000000000000";
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signal master_dsc_enable : STD_LOGIC;
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signal master_dsc_done : STD_LOGIC;
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signal master_dsc_reset : STD_LOGIC;
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signal is_master : STD_LOGIC;
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signal net_dsc_enable : STD_LOGIC;
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signal net_dsc_done : STD_LOGIC;
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signal net_dsc_reset : STD_LOGIC;
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signal node_count : STD_LOGIC_VECTOR(3 downto 0);
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signal address : STD_LOGIC_VECTOR(3 downto 0);
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signal reg_dsc_enable : STD_LOGIC;
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signal reg_dsc_done : STD_LOGIC;
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signal reg_dsc_reset : STD_LOGIC;
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signal sync_dsc_enable : STD_LOGIC;
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signal sync_dsc_done : STD_LOGIC;
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signal sync_dsc_reset : STD_LOGIC;
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signal data_enable : STD_LOGIC;
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signal network_reg_internal_clk : STD_LOGIC;
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signal network_reg_internal_write_data : STD_LOGIC_VECTOR(7 downto 0);
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signal network_reg_internal_addr : STD_LOGIC_VECTOR(5 downto 0);
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signal network_reg_internal_we : STD_LOGIC_VECTOR(0 downto 0);
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signal network_reg_internal_read_data : STD_LOGIC_VECTOR(7 downto 0);
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signal network_reg_internal_clk_net : STD_LOGIC;
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signal network_reg_internal_write_data_net : STD_LOGIC_VECTOR(7 downto 0);
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signal network_reg_internal_addr_net : STD_LOGIC_VECTOR(5 downto 0);
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signal network_reg_internal_we_net : STD_LOGIC_VECTOR(0 downto 0);
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signal network_reg_internal_clk_reg : STD_LOGIC;
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signal network_reg_internal_write_data_reg : STD_LOGIC_VECTOR(7 downto 0);
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signal network_reg_internal_addr_reg : STD_LOGIC_VECTOR(5 downto 0);
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signal network_reg_internal_we_reg : STD_LOGIC_VECTOR(0 downto 0);
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signal data_out : STD_LOGIC_VECTOR(7 downto 0);
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signal data_out_strobe : STD_LOGIC;
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signal data_out_enable : STD_LOGIC;
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signal data_in : STD_LOGIC_VECTOR(7 downto 0);
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signal data_in_master : STD_LOGIC_VECTOR(7 downto 0);
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signal data_in_net : STD_LOGIC_VECTOR(7 downto 0);
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signal data_in_reg : STD_LOGIC_VECTOR(7 downto 0);
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signal data_in_sync : STD_LOGIC_VECTOR(7 downto 0);
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signal data_in_strobe : STD_LOGIC;
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signal data_in_strobe_master : STD_LOGIC;
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signal data_in_strobe_net : STD_LOGIC;
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signal data_in_strobe_reg : STD_LOGIC;
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signal data_in_strobe_sync : STD_LOGIC;
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signal data_in_enable : STD_LOGIC;
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signal data_in_enable_master : STD_LOGIC;
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signal data_in_enable_net : STD_LOGIC;
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signal data_in_enable_reg : STD_LOGIC;
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signal data_in_enable_sync : STD_LOGIC;
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signal crcgen_tx_input : STD_LOGIC_VECTOR(7 downto 0);
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signal crcgen_tx_output : STD_LOGIC_VECTOR(7 downto 0);
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signal crcgen_tx_reset : STD_LOGIC;
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signal crcgen_tx_clk : STD_LOGIC := '0';
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signal crcgen_tx_clk_en : STD_LOGIC := '0';
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signal crcgen_tx_clk_en_buffer : STD_LOGIC := '0';
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signal crc_tx_done : STD_LOGIC := '0';
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signal crcgen_rx_input : STD_LOGIC_VECTOR(7 downto 0);
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signal crcgen_rx_output : STD_LOGIC_VECTOR(7 downto 0);
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signal crcgen_rx_reset : STD_LOGIC;
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signal crcgen_rx_clk : STD_LOGIC;
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signal crcgen_rx_clk_en : STD_LOGIC;
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signal tpl_reset : STD_LOGIC;
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component tpl_tx is
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Port ( data : in STD_LOGIC_VECTOR(7 downto 0);
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clk_50M : in STD_LOGIC;
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clk_data_en : out STD_LOGIC;
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enable : in STD_LOGIC;
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reset : in STD_LOGIC;
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sig_out : out STD_LOGIC;
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clk_div_reset : in STD_LOGIC;
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clk_div_reset_ack : out STD_LOGIC);
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end component;
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component tpl_rx is
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Port ( data : out STD_LOGIC_VECTOR(7 downto 0);
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valid : out STD_LOGIC;
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error : out STD_LOGIC;
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clk_data : out STD_LOGIC;
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clk_50M : in STD_LOGIC;
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reset : in STD_LOGIC;
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sig_in : in STD_LOGIC);
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end component;
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component tdl_app_master is
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Port ( app_enable : in STD_LOGIC;
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app_data_in : in STD_LOGIC_VECTOR(7 downto 0);
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app_data_in_strobe : in STD_LOGIC;
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app_data_out : out STD_LOGIC_VECTOR(7 downto 0);
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app_data_out_strobe : out STD_LOGIC;
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app_data_out_enable : out STD_LOGIC;
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app_buffer_full : in STD_LOGIC;
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app_packet_error : in STD_LOGIC;
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app_force_packet_error : out STD_LOGIC;
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app_cmd_valid : in STD_LOGIC;
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app_sync_strobe : in STD_LOGIC;
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app_is_master : out STD_LOGIC;
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app_dsc_done : out STD_LOGIC;
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app_node_id : in STD_LOGIC_VECTOR(3 downto 0);
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app_clk : in STD_LOGIC;
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app_reset : in STD_LOGIC);
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end component;
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component tdl_app_net is
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Port ( app_enable : in STD_LOGIC;
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app_data_in : in STD_LOGIC_VECTOR(7 downto 0);
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app_data_in_strobe : in STD_LOGIC;
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app_data_out : out STD_LOGIC_VECTOR(7 downto 0);
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app_data_out_strobe : out STD_LOGIC;
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app_data_out_enable : out STD_LOGIC;
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app_buffer_full : in STD_LOGIC;
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app_packet_error : in STD_LOGIC;
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app_force_packet_error : out STD_LOGIC;
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app_cmd_valid : in STD_LOGIC;
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app_sync_strobe : in STD_LOGIC;
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app_is_master : in STD_LOGIC;
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app_dsc_done : out STD_LOGIC;
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app_network_reg_clk : out STD_LOGIC;
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app_network_reg_addr : out STD_LOGIC_VECTOR(5 downto 0);
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app_network_reg_data_in : in STD_LOGIC_VECTOR(7 downto 0);
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app_network_reg_data_out : out STD_LOGIC_VECTOR(7 downto 0);
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app_network_reg_we : inout STD_LOGIC_VECTOR(0 downto 0);
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app_node_count : out STD_LOGIC_VECTOR(3 downto 0);
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app_node_address : out STD_LOGIC_VECTOR(3 downto 0);
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app_node_id : in STD_LOGIC_VECTOR(3 downto 0);
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app_clk : in STD_LOGIC;
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app_reset : in STD_LOGIC);
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end component;
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component tdl_app_reg is
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Port ( app_enable : in STD_LOGIC;
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app_data_in : in STD_LOGIC_VECTOR(7 downto 0);
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app_data_in_strobe : in STD_LOGIC;
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app_data_out : out STD_LOGIC_VECTOR(7 downto 0);
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app_data_out_strobe : out STD_LOGIC;
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app_data_out_enable : out STD_LOGIC;
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app_buffer_full : in STD_LOGIC;
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app_packet_error : in STD_LOGIC;
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app_force_packet_error : out STD_LOGIC;
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app_cmd_valid : in STD_LOGIC;
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app_sync_strobe : in STD_LOGIC;
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app_is_master : in STD_LOGIC;
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app_dsc_done : out STD_LOGIC;
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app_network_reg_clk : out STD_LOGIC;
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app_network_reg_addr : out STD_LOGIC_VECTOR(5 downto 0);
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app_network_reg_data_in : in STD_LOGIC_VECTOR(7 downto 0);
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app_network_reg_data_out : out STD_LOGIC_VECTOR(7 downto 0);
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app_network_reg_we : inout STD_LOGIC_VECTOR(0 downto 0);
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app_node_count : in STD_LOGIC_VECTOR(3 downto 0);
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app_node_address : in STD_LOGIC_VECTOR(3 downto 0);
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app_node_id : in STD_LOGIC_VECTOR(3 downto 0);
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app_reg_enable : in STD_LOGIC_VECTOR(7 downto 0);
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app_clk : in STD_LOGIC;
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app_reset : in STD_LOGIC);
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end component;
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component tdl_app_sync is
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Port ( app_enable : in STD_LOGIC;
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app_data_in : in STD_LOGIC_VECTOR(7 downto 0);
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app_data_in_strobe : in STD_LOGIC;
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app_data_in_enable : in STD_LOGIC;
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294 |
|
|
app_data_out : out STD_LOGIC_VECTOR(7 downto 0);
|
295 |
|
|
app_data_out_strobe : out STD_LOGIC;
|
296 |
|
|
app_data_out_enable : out STD_LOGIC;
|
297 |
|
|
app_buffer_full : in STD_LOGIC;
|
298 |
|
|
app_packet_error : in STD_LOGIC;
|
299 |
|
|
app_force_packet_error : out STD_LOGIC;
|
300 |
|
|
app_cmd_valid : in STD_LOGIC;
|
301 |
|
|
app_sync_strobe : out STD_LOGIC;
|
302 |
|
|
app_is_master : in STD_LOGIC;
|
303 |
|
|
app_dsc_done : out STD_LOGIC;
|
304 |
|
|
app_node_id : in STD_LOGIC_VECTOR(3 downto 0);
|
305 |
|
|
app_node_count : in STD_LOGIC_VECTOR(3 downto 0);
|
306 |
|
|
app_node_address : in STD_LOGIC_VECTOR(3 downto 0);
|
307 |
|
|
app_clk : in STD_LOGIC;
|
308 |
|
|
app_reset : in STD_LOGIC);
|
309 |
|
|
end component;
|
310 |
|
|
|
311 |
|
|
component crcgen is
|
312 |
|
|
Port( reset : in STD_LOGIC;
|
313 |
|
|
clk : in STD_LOGIC;
|
314 |
|
|
clk_en : in STD_LOGIC;
|
315 |
|
|
Din : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
|
316 |
|
|
Xout : out STD_LOGIC_VECTOR(CRCDIM - 1 downto 0));
|
317 |
|
|
end component;
|
318 |
|
|
|
319 |
|
|
component network_register is
|
320 |
|
|
Port ( clka : in STD_LOGIC;
|
321 |
|
|
dina : in STD_LOGIC_VECTOR(7 downto 0);
|
322 |
|
|
addra : in STD_LOGIC_VECTOR(5 downto 0);
|
323 |
|
|
douta : out STD_LOGIC_VECTOR(7 downto 0);
|
324 |
|
|
wea : in STD_LOGIC_VECTOR(0 downto 0);
|
325 |
|
|
clkb : in STD_LOGIC;
|
326 |
|
|
dinb : in STD_LOGIC_VECTOR(31 downto 0);
|
327 |
|
|
addrb : in STD_LOGIC_VECTOR(3 downto 0);
|
328 |
|
|
web : in STD_LOGIC_VECTOR(0 downto 0);
|
329 |
|
|
doutb : out STD_LOGIC_VECTOR(31 downto 0));
|
330 |
|
|
end component;
|
331 |
|
|
|
332 |
|
|
begin
|
333 |
|
|
|
334 |
|
|
tpl_tx_inst : tpl_tx
|
335 |
|
|
Port map ( data => tx_data,
|
336 |
|
|
enable => tx_enable,
|
337 |
|
|
clk_50M => clk_50M,
|
338 |
|
|
clk_data_en => tx_clk_en,
|
339 |
|
|
reset => tpl_reset,
|
340 |
|
|
sig_out => sig_out,
|
341 |
|
|
clk_div_reset => tx_clk_div_reset,
|
342 |
|
|
clk_div_reset_ack => tx_clk_div_reset_ack);
|
343 |
|
|
|
344 |
|
|
tpl_rx_inst : tpl_rx
|
345 |
|
|
Port map ( data => rx_data,
|
346 |
|
|
valid => rx_valid,
|
347 |
|
|
error => rx_error,
|
348 |
|
|
clk_data => rx_clk,
|
349 |
|
|
clk_50M => clk_50M,
|
350 |
|
|
reset => tpl_reset,
|
351 |
|
|
sig_in => sig_in);
|
352 |
|
|
|
353 |
|
|
|
354 |
|
|
app_master_inst : tdl_app_master
|
355 |
|
|
Port map ( app_enable => master_dsc_enable,
|
356 |
|
|
app_data_in => data_out,
|
357 |
|
|
app_data_in_strobe => data_out_strobe,
|
358 |
|
|
app_data_out => data_in_master,
|
359 |
|
|
app_data_out_strobe => data_in_strobe_master,
|
360 |
|
|
app_data_out_enable => data_in_enable_master,
|
361 |
|
|
app_buffer_full => buffer_full,
|
362 |
|
|
app_packet_error => packet_error,
|
363 |
|
|
app_cmd_valid => rx_cmd_valid,
|
364 |
|
|
app_sync_strobe => sync_strobe,
|
365 |
|
|
app_is_master => is_master,
|
366 |
|
|
app_dsc_done => master_dsc_done,
|
367 |
|
|
app_node_id => node_id,
|
368 |
|
|
app_clk => clk_50M,
|
369 |
|
|
app_reset => master_dsc_reset);
|
370 |
|
|
|
371 |
|
|
app_net_inst : tdl_app_net
|
372 |
|
|
Port map ( app_enable => net_dsc_enable,
|
373 |
|
|
app_data_in => data_out,
|
374 |
|
|
app_data_in_strobe => data_out_strobe,
|
375 |
|
|
app_data_out => data_in_net,
|
376 |
|
|
app_data_out_strobe => data_in_strobe_net,
|
377 |
|
|
app_data_out_enable => data_in_enable_net,
|
378 |
|
|
app_buffer_full => buffer_full,
|
379 |
|
|
app_packet_error => packet_error,
|
380 |
|
|
app_cmd_valid => rx_cmd_valid,
|
381 |
|
|
app_sync_strobe => sync_strobe,
|
382 |
|
|
app_is_master => is_master,
|
383 |
|
|
app_dsc_done => net_dsc_done,
|
384 |
|
|
app_network_reg_clk => network_reg_internal_clk_net,
|
385 |
|
|
app_network_reg_data_in => network_reg_internal_read_data,
|
386 |
|
|
app_network_reg_data_out => network_reg_internal_write_data_net,
|
387 |
|
|
app_network_reg_addr => network_reg_internal_addr_net,
|
388 |
|
|
app_network_reg_we => network_reg_internal_we_net,
|
389 |
|
|
app_node_count => node_count,
|
390 |
|
|
app_node_address => address,
|
391 |
|
|
app_node_id => node_id,
|
392 |
|
|
app_clk => clk_50M,
|
393 |
|
|
app_reset => net_dsc_reset);
|
394 |
|
|
|
395 |
|
|
app_reg_inst : tdl_app_reg
|
396 |
|
|
Port map ( app_enable => reg_dsc_enable,
|
397 |
|
|
app_data_in => data_out,
|
398 |
|
|
app_data_in_strobe => data_out_strobe,
|
399 |
|
|
app_data_out => data_in_reg,
|
400 |
|
|
app_data_out_strobe => data_in_strobe_reg,
|
401 |
|
|
app_data_out_enable => data_in_enable_reg,
|
402 |
|
|
app_buffer_full => buffer_full,
|
403 |
|
|
app_packet_error => packet_error,
|
404 |
|
|
app_cmd_valid => rx_cmd_valid,
|
405 |
|
|
app_sync_strobe => sync_strobe,
|
406 |
|
|
app_is_master => is_master,
|
407 |
|
|
app_dsc_done => reg_dsc_done,
|
408 |
|
|
app_network_reg_clk => network_reg_internal_clk_reg,
|
409 |
|
|
app_network_reg_data_in => network_reg_internal_read_data,
|
410 |
|
|
app_network_reg_data_out => network_reg_internal_write_data_reg,
|
411 |
|
|
app_network_reg_addr => network_reg_internal_addr_reg,
|
412 |
|
|
app_network_reg_we => network_reg_internal_we_reg,
|
413 |
|
|
app_node_count => node_count,
|
414 |
|
|
app_node_address => address,
|
415 |
|
|
app_node_id => node_id,
|
416 |
|
|
app_reg_enable => reg_enable,
|
417 |
|
|
app_clk => clk_50M,
|
418 |
|
|
app_reset => reg_dsc_reset);
|
419 |
|
|
|
420 |
|
|
app_sync_inst : tdl_app_sync
|
421 |
|
|
Port map( app_enable => sync_dsc_enable,
|
422 |
|
|
app_data_in => data_out,
|
423 |
|
|
app_data_in_strobe => data_out_strobe,
|
424 |
|
|
app_data_in_enable => data_out_enable,
|
425 |
|
|
app_data_out => data_in_sync,
|
426 |
|
|
app_data_out_strobe => data_in_strobe_sync,
|
427 |
|
|
app_data_out_enable => data_in_enable_sync,
|
428 |
|
|
app_buffer_full => buffer_full,
|
429 |
|
|
app_packet_error => packet_error,
|
430 |
|
|
app_cmd_valid => rx_cmd_valid,
|
431 |
|
|
app_sync_strobe => sync_strobe,
|
432 |
|
|
app_is_master => is_master,
|
433 |
|
|
app_dsc_done => sync_dsc_done,
|
434 |
|
|
app_node_id => node_id,
|
435 |
|
|
app_node_count => node_count,
|
436 |
|
|
app_node_address => address,
|
437 |
|
|
app_clk => clk_50M,
|
438 |
|
|
app_reset => sync_dsc_reset);
|
439 |
|
|
|
440 |
|
|
crcgen_tx_inst : crcgen
|
441 |
|
|
Port map ( reset => crcgen_tx_reset,
|
442 |
|
|
clk => crcgen_tx_clk,
|
443 |
|
|
clk_en => crcgen_tx_clk_en,
|
444 |
|
|
Din => crcgen_tx_input,
|
445 |
|
|
Xout => crcgen_tx_output);
|
446 |
|
|
|
447 |
|
|
crcgen_rx_inst : crcgen
|
448 |
|
|
Port map ( reset => crcgen_rx_reset,
|
449 |
|
|
clk => crcgen_rx_clk,
|
450 |
|
|
clk_en => crcgen_rx_clk_en,
|
451 |
|
|
Din => crcgen_rx_input,
|
452 |
|
|
Xout => crcgen_rx_output);
|
453 |
|
|
|
454 |
|
|
crcgen_rx_clk <= clk_50M;
|
455 |
|
|
crcgen_rx_clk_en <= '1' when ((rx_clk = '1') and (last_rx_clk = '0')) else '0';
|
456 |
|
|
crcgen_rx_reset <= not rx_valid;
|
457 |
|
|
crcgen_rx_input <= rx_data;
|
458 |
|
|
|
459 |
|
|
crcgen_tx_clk <= clk_50M;
|
460 |
|
|
|
461 |
|
|
network_register_inst : network_register
|
462 |
|
|
Port map ( clka => network_reg_internal_clk,
|
463 |
|
|
dina => network_reg_internal_write_data,
|
464 |
|
|
addra => network_reg_internal_addr,
|
465 |
|
|
wea => network_reg_internal_we,
|
466 |
|
|
douta => network_reg_internal_read_data,
|
467 |
|
|
clkb => network_reg_clk,
|
468 |
|
|
dinb => "00000000000000000000000000000000",
|
469 |
|
|
addrb => network_reg_addr,
|
470 |
|
|
web => "0",
|
471 |
|
|
doutb => network_reg_data);
|
472 |
|
|
|
473 |
|
|
node_is_master <= is_master;
|
474 |
|
|
node_address <= address;
|
475 |
|
|
online <= data_enable;
|
476 |
|
|
|
477 |
|
|
process(clk_50M)
|
478 |
|
|
begin
|
479 |
|
|
if(clk_50M = '1' and clk_50M'EVENT) then
|
480 |
|
|
if(reset = '1') then
|
481 |
|
|
main_state <= IDLE;
|
482 |
|
|
tx_state <= IDLE;
|
483 |
|
|
rx_state <= IDLE;
|
484 |
|
|
watchdog_counter <= (others => '0');
|
485 |
|
|
else
|
486 |
|
|
main_state <= next_main_state;
|
487 |
|
|
|
488 |
|
|
if(data_in_strobe = '1' and last_data_in_strobe = '0' and data_in_enable = '1') then --The initial 8 bit input buffer
|
489 |
|
|
input_buffer <= data_in;
|
490 |
|
|
input_available <= '1';
|
491 |
|
|
end if;
|
492 |
|
|
|
493 |
|
|
if(tx_clk_en = '0' and input_available = '1') then --The main 8 bit input data buffer
|
494 |
|
|
if(data_buffer_counter = '0') then
|
495 |
|
|
data_buffer <= input_buffer;
|
496 |
|
|
data_buffer_counter <= '1';
|
497 |
|
|
input_available <= '0';
|
498 |
|
|
end if;
|
499 |
|
|
end if;
|
500 |
|
|
|
501 |
|
|
last_tx_clk_en <= tx_clk_en;
|
502 |
|
|
last_rx_clk <= rx_clk;
|
503 |
|
|
last_data_in_strobe <= data_in_strobe;
|
504 |
|
|
end if;
|
505 |
|
|
|
506 |
|
|
if(main_state = next_main_state) then
|
507 |
|
|
main_counter <= main_counter + 1;
|
508 |
|
|
else
|
509 |
|
|
main_counter <= "00000000";
|
510 |
|
|
end if;
|
511 |
|
|
|
512 |
|
|
case main_state is --Main state machine
|
513 |
|
|
when IDLE =>
|
514 |
|
|
master_dsc_enable <= '0';
|
515 |
|
|
net_dsc_enable <= '0';
|
516 |
|
|
reg_dsc_enable <= '0';
|
517 |
|
|
sync_dsc_enable <= '0';
|
518 |
|
|
data_enable <= '0';
|
519 |
|
|
master_dsc_reset <= '1';
|
520 |
|
|
net_dsc_reset <= '1';
|
521 |
|
|
reg_dsc_reset <= '1';
|
522 |
|
|
sync_dsc_reset <= '1';
|
523 |
|
|
input_buffer <= "00000000";
|
524 |
|
|
input_available <= '0';
|
525 |
|
|
data_buffer <= (others => '0');
|
526 |
|
|
data_buffer_counter <= '0';
|
527 |
|
|
watchdog_counter <= (others => '0');
|
528 |
|
|
internal_reset <= '0';
|
529 |
|
|
do_internal_reset <= '0';
|
530 |
|
|
if(main_counter < 42) then
|
531 |
|
|
tpl_reset <= '1';
|
532 |
|
|
else
|
533 |
|
|
tpl_reset <= '0';
|
534 |
|
|
end if;
|
535 |
|
|
when MASTER_DSC =>
|
536 |
|
|
master_dsc_enable <= '1';
|
537 |
|
|
net_dsc_enable <= '0';
|
538 |
|
|
reg_dsc_enable <= '0';
|
539 |
|
|
sync_dsc_enable <= '0';
|
540 |
|
|
data_enable <= '0';
|
541 |
|
|
master_dsc_reset <= '0';
|
542 |
|
|
net_dsc_reset <= '0';
|
543 |
|
|
reg_dsc_reset <= '0';
|
544 |
|
|
sync_dsc_reset <= '0';
|
545 |
|
|
internal_reset <= '0';
|
546 |
|
|
do_internal_reset <= '0';
|
547 |
|
|
when NET_DSC =>
|
548 |
|
|
master_dsc_enable <= '0';
|
549 |
|
|
net_dsc_enable <= '1';
|
550 |
|
|
reg_dsc_enable <= '0';
|
551 |
|
|
sync_dsc_enable <= '0';
|
552 |
|
|
data_enable <= '0';
|
553 |
|
|
when REG_DSC =>
|
554 |
|
|
master_dsc_enable <= '0';
|
555 |
|
|
net_dsc_enable <= '0';
|
556 |
|
|
reg_dsc_enable <= '1';
|
557 |
|
|
sync_dsc_enable <= '0';
|
558 |
|
|
data_enable <= '0';
|
559 |
|
|
when SYNC_DSC =>
|
560 |
|
|
master_dsc_enable <= '0';
|
561 |
|
|
net_dsc_enable <= '0';
|
562 |
|
|
reg_dsc_enable <= '0';
|
563 |
|
|
sync_dsc_enable <= '1';
|
564 |
|
|
data_enable <= '0';
|
565 |
|
|
when DATA =>
|
566 |
|
|
master_dsc_enable <= '0';
|
567 |
|
|
net_dsc_enable <= '0';
|
568 |
|
|
reg_dsc_enable <= '0';
|
569 |
|
|
sync_dsc_enable <= '1'; --Keep app_sync enabled to maintain the sync signal during operation
|
570 |
|
|
data_enable <= '1';
|
571 |
|
|
when ERROR =>
|
572 |
|
|
end case;
|
573 |
|
|
|
574 |
|
|
if(do_internal_reset = '1') then --Perform reset if requested internally...
|
575 |
|
|
internal_reset <= '1';
|
576 |
|
|
end if;
|
577 |
|
|
|
578 |
|
|
if(reset = '1' or internal_reset = '1') then
|
579 |
|
|
tx_state <= IDLE;
|
580 |
|
|
rx_state <= IDLE;
|
581 |
|
|
else
|
582 |
|
|
tx_state <= next_tx_state;
|
583 |
|
|
rx_state <= next_rx_state;
|
584 |
|
|
end if;
|
585 |
|
|
|
586 |
|
|
crcgen_tx_clk_en_buffer <= tx_clk_en;
|
587 |
|
|
crcgen_tx_clk_en <= crcgen_tx_clk_en_buffer;
|
588 |
|
|
|
589 |
|
|
if(tx_state = IDLE) then --This is used to optimize the jitter performance, by restarting the clock enable generation of the physical transmission layer, thus creating a better synchronization with the upper layers. Without, you risk waiting for tx_clk_en for a full 1.25 MHz clock cycle (800 ns) - by resetting the clock generation you wait 0 to 4 50 MHz clock cycles (max 80 ns) instead.
|
590 |
|
|
tx_clk_div_reset <= '0';
|
591 |
|
|
else
|
592 |
|
|
tx_clk_div_reset <= '1';
|
593 |
|
|
end if;
|
594 |
|
|
|
595 |
|
|
case tx_state is --Transmission state machine, this part needs to run on clk_50M to avoid multisourcing data_buffer
|
596 |
|
|
when IDLE =>
|
597 |
|
|
tx_data <= "00000000";
|
598 |
|
|
tx_enable <= '0';
|
599 |
|
|
crcgen_tx_reset <= '1';
|
600 |
|
|
crc_tx_done <= '0';
|
601 |
|
|
when DATA_CMD => --Transmit first nibble of DATA command
|
602 |
|
|
if(tx_clk_en = '1' and tx_clk_div_reset_ack = '1') then
|
603 |
|
|
tx_data <= CMD_DATA & "0000";
|
604 |
|
|
tx_enable <= '1';
|
605 |
|
|
crcgen_tx_reset <= '0';
|
606 |
|
|
crcgen_tx_input <= CMD_DATA & "0000";
|
607 |
|
|
end if;
|
608 |
|
|
when DATA => --Transmit contents of data buffer
|
609 |
|
|
if(tx_clk_en = '1' and tx_clk_div_reset_ack = '1') then
|
610 |
|
|
if(not(data_buffer_counter = '0')) then
|
611 |
|
|
tx_data <= data_buffer;
|
612 |
|
|
data_buffer_counter <= '0';
|
613 |
|
|
tx_enable <= '1';
|
614 |
|
|
|
615 |
|
|
crcgen_tx_reset <= '0'; --Load the transmitted byte into the CRC module
|
616 |
|
|
crcgen_tx_input <= data_buffer;
|
617 |
|
|
else --AARRG... Buffer underrun... do.. erm... something...
|
618 |
|
|
tx_enable <= '0';
|
619 |
|
|
end if;
|
620 |
|
|
elsif((data_in_enable = '0') and (data_buffer_counter = '0') and (crcgen_tx_clk_en = '1')) then --When data has been transmitted, load a byte containing all zeros into the CRC module
|
621 |
|
|
crcgen_tx_input <= "00000000";
|
622 |
|
|
crcgen_tx_clk_en_buffer <= '1';
|
623 |
|
|
crc_tx_done <= '1';
|
624 |
|
|
end if;
|
625 |
|
|
|
626 |
|
|
when CRC => --Transmit CRC checksum
|
627 |
|
|
if(tx_clk_en = '1') then
|
628 |
|
|
if(force_packet_error = '1') then
|
629 |
|
|
tx_data <= not crcgen_tx_output(7 downto 0); --Flip the CRC byte to make sure this packet produces a CRC error at the receiver... Of course you can neven be completely sure with a CRC check, but the probability is quite good;)
|
630 |
|
|
else
|
631 |
|
|
tx_data <= crcgen_tx_output(7 downto 0);
|
632 |
|
|
end if;
|
633 |
|
|
|
634 |
|
|
tx_enable <= '1';
|
635 |
|
|
end if;
|
636 |
|
|
when ERROR =>
|
637 |
|
|
end case;
|
638 |
|
|
|
639 |
|
|
|
640 |
|
|
if(rx_clk = '0' and last_rx_clk = '1') then
|
641 |
|
|
data_out <= data_out_buffer_2;
|
642 |
|
|
data_out_buffer_2 <= data_out_buffer_1;
|
643 |
|
|
data_out_enable <= data_out_enable_buffer_2;
|
644 |
|
|
data_out_enable_buffer_2 <= data_out_enable_buffer_1;
|
645 |
|
|
rx_cmd_valid <= rx_cmd_valid_buffer_2;
|
646 |
|
|
rx_cmd_valid_buffer_2 <= rx_cmd_valid_buffer_1;
|
647 |
|
|
end if;
|
648 |
|
|
|
649 |
|
|
case rx_state is
|
650 |
|
|
when IDLE =>
|
651 |
|
|
data_out_buffer_1 <= (others => '0');
|
652 |
|
|
data_out_buffer_2 <= (others => '0');
|
653 |
|
|
data_out_enable_buffer_1 <= '0';
|
654 |
|
|
data_out_enable_buffer_2 <= '0';
|
655 |
|
|
rx_cmd_valid_buffer_1 <= '0';
|
656 |
|
|
rx_cmd_valid_buffer_2 <= '0';
|
657 |
|
|
when CMD =>
|
658 |
|
|
watchdog_counter <= (others => '0'); --We are receiving something => The network is alive (in some way at least) => Reset the watchdog
|
659 |
|
|
if(rx_clk = '1' and last_rx_clk = '0') then
|
660 |
|
|
data_out_buffer_1 <= rx_data;
|
661 |
|
|
|
662 |
|
|
rx_cmd_valid_buffer_1 <= '0';
|
663 |
|
|
case main_state is
|
664 |
|
|
when IDLE =>
|
665 |
|
|
when MASTER_DSC =>
|
666 |
|
|
data_out_enable_buffer_1 <= '1';
|
667 |
|
|
|
668 |
|
|
case rx_data(7 downto 4) is --Check for a valid command
|
669 |
|
|
when CMD_MASTER_DSC =>
|
670 |
|
|
rx_cmd_valid_buffer_1 <= '1';
|
671 |
|
|
when CMD_MASTER_SET =>
|
672 |
|
|
rx_cmd_valid_buffer_1 <= '1';
|
673 |
|
|
when others =>
|
674 |
|
|
end case;
|
675 |
|
|
|
676 |
|
|
when NET_DSC =>
|
677 |
|
|
data_out_enable_buffer_1 <= '1';
|
678 |
|
|
|
679 |
|
|
case rx_data(7 downto 4) is --Check for a valid command
|
680 |
|
|
when CMD_MASTER_DSC => --If we receive master discovery packets, the network is being reset, so do the same here
|
681 |
|
|
do_internal_reset <= '1';
|
682 |
|
|
when CMD_NET_DSC =>
|
683 |
|
|
rx_cmd_valid_buffer_1 <= '1';
|
684 |
|
|
when CMD_NET_SET =>
|
685 |
|
|
rx_cmd_valid_buffer_1 <= '1';
|
686 |
|
|
when others =>
|
687 |
|
|
end case;
|
688 |
|
|
|
689 |
|
|
when REG_DSC =>
|
690 |
|
|
data_out_enable_buffer_1 <= '1';
|
691 |
|
|
|
692 |
|
|
case rx_data(7 downto 4) is --As above
|
693 |
|
|
when CMD_MASTER_DSC =>
|
694 |
|
|
do_internal_reset <= '1';
|
695 |
|
|
when CMD_REG_DSC =>
|
696 |
|
|
rx_cmd_valid_buffer_1 <= '1';
|
697 |
|
|
when CMD_REG_SET =>
|
698 |
|
|
rx_cmd_valid_buffer_1 <= '1';
|
699 |
|
|
when others =>
|
700 |
|
|
end case;
|
701 |
|
|
|
702 |
|
|
when SYNC_DSC =>
|
703 |
|
|
data_out_enable_buffer_1 <= '1';
|
704 |
|
|
|
705 |
|
|
case rx_data(7 downto 4) is --As above (this is actually a leftover from an early sync_dsc implementation, where the delay was measured at startup - currently a fixed delay is used instead, but it's nice to keep this around (also to be able to react to network resets during the sync_dsc state quickly))
|
706 |
|
|
when CMD_MASTER_DSC =>
|
707 |
|
|
do_internal_reset <= '1';
|
708 |
|
|
when CMD_SYNC_DSC =>
|
709 |
|
|
rx_cmd_valid_buffer_1 <= '1';
|
710 |
|
|
when CMD_SYNC_SET =>
|
711 |
|
|
rx_cmd_valid_buffer_1 <= '1';
|
712 |
|
|
when others =>
|
713 |
|
|
end case;
|
714 |
|
|
|
715 |
|
|
when DATA =>
|
716 |
|
|
data_out_enable_buffer_1 <= '0';
|
717 |
|
|
|
718 |
|
|
case rx_data(7 downto 4) is --As above
|
719 |
|
|
when CMD_MASTER_DSC =>
|
720 |
|
|
do_internal_reset <= '1';
|
721 |
|
|
when CMD_DATA =>
|
722 |
|
|
rx_cmd_valid_buffer_1 <= '1';
|
723 |
|
|
when others =>
|
724 |
|
|
end case;
|
725 |
|
|
|
726 |
|
|
when ERROR =>
|
727 |
|
|
end case;
|
728 |
|
|
end if;
|
729 |
|
|
when DATA =>
|
730 |
|
|
watchdog_counter <= (others => '0');
|
731 |
|
|
if(rx_clk = '1' and last_rx_clk = '0') then
|
732 |
|
|
data_out_enable_buffer_1 <= '1';
|
733 |
|
|
data_out_buffer_1 <= rx_data;
|
734 |
|
|
end if;
|
735 |
|
|
crcgen_rx_output_buffer <= crcgen_rx_output;
|
736 |
|
|
when CRC =>
|
737 |
|
|
data_out_enable_buffer_1 <= '0';
|
738 |
|
|
data_out_enable_buffer_2 <= '0';
|
739 |
|
|
if(crcgen_rx_output_buffer = "00000000") then
|
740 |
|
|
packet_error <= '0';
|
741 |
|
|
else
|
742 |
|
|
packet_error <= '1';
|
743 |
|
|
end if;
|
744 |
|
|
when ERROR =>
|
745 |
|
|
end case;
|
746 |
|
|
|
747 |
|
|
if(tx_clk_en = '0' and last_tx_clk_en = '1') then
|
748 |
|
|
watchdog_counter <= watchdog_counter + 1; --Increment the watchdog
|
749 |
|
|
|
750 |
|
|
if(watchdog_counter = watchdog_threshold) then --If the watchdog timer crosses the threshold, perform an internal reset
|
751 |
|
|
do_internal_reset <= '1';
|
752 |
|
|
end if;
|
753 |
|
|
end if;
|
754 |
|
|
|
755 |
|
|
end if;
|
756 |
|
|
end process;
|
757 |
|
|
|
758 |
|
|
data_out_strobe <= rx_clk and data_out_enable;
|
759 |
|
|
|
760 |
|
|
process(main_state, main_counter, master_dsc_done, net_dsc_done, reg_dsc_done, sync_dsc_done, data_buffer_counter, internal_reset)
|
761 |
|
|
begin
|
762 |
|
|
case main_state is
|
763 |
|
|
when IDLE =>
|
764 |
|
|
if(main_counter = 100 and data_buffer_counter = '0') then
|
765 |
|
|
next_main_state <= MASTER_DSC;
|
766 |
|
|
else
|
767 |
|
|
next_main_state <= IDLE;
|
768 |
|
|
end if;
|
769 |
|
|
when MASTER_DSC =>
|
770 |
|
|
if(internal_reset = '1') then
|
771 |
|
|
next_main_state <= IDLE;
|
772 |
|
|
elsif(master_dsc_done = '1' and data_buffer_counter = '0') then
|
773 |
|
|
next_main_state <= NET_DSC;
|
774 |
|
|
else
|
775 |
|
|
next_main_state <= MASTER_DSC;
|
776 |
|
|
end if;
|
777 |
|
|
when NET_DSC =>
|
778 |
|
|
if(internal_reset = '1') then
|
779 |
|
|
next_main_state <= IDLE;
|
780 |
|
|
elsif(net_dsc_done = '1' and data_buffer_counter = '0') then
|
781 |
|
|
next_main_state <= REG_DSC;
|
782 |
|
|
else
|
783 |
|
|
next_main_state <= NET_DSC;
|
784 |
|
|
end if;
|
785 |
|
|
when REG_DSC =>
|
786 |
|
|
if(internal_reset = '1') then
|
787 |
|
|
next_main_state <= IDLE;
|
788 |
|
|
elsif(reg_dsc_done = '1' and data_buffer_counter = '0') then
|
789 |
|
|
next_main_state <= SYNC_DSC;
|
790 |
|
|
else
|
791 |
|
|
next_main_state <= REG_DSC;
|
792 |
|
|
end if;
|
793 |
|
|
when SYNC_DSC =>
|
794 |
|
|
if(internal_reset = '1') then
|
795 |
|
|
next_main_state <= IDLE;
|
796 |
|
|
elsif(sync_dsc_done = '1' and data_buffer_counter = '0') then
|
797 |
|
|
next_main_state <= DATA;
|
798 |
|
|
else
|
799 |
|
|
next_main_state <= SYNC_DSC;
|
800 |
|
|
end if;
|
801 |
|
|
when DATA =>
|
802 |
|
|
if(internal_reset = '1') then
|
803 |
|
|
next_main_state <= IDLE;
|
804 |
|
|
else
|
805 |
|
|
next_main_state <= DATA;
|
806 |
|
|
end if;
|
807 |
|
|
when ERROR =>
|
808 |
|
|
if(internal_reset = '1') then
|
809 |
|
|
next_main_state <= IDLE;
|
810 |
|
|
else
|
811 |
|
|
next_main_state <= ERROR;
|
812 |
|
|
end if;
|
813 |
|
|
when others =>
|
814 |
|
|
next_main_state <= ERROR;
|
815 |
|
|
end case;
|
816 |
|
|
end process;
|
817 |
|
|
|
818 |
|
|
|
819 |
|
|
process(tx_state, data_in_enable, data_buffer_counter, main_state, crc_tx_done, tx_clk_en, tx_enable)
|
820 |
|
|
begin
|
821 |
|
|
case tx_state is
|
822 |
|
|
when IDLE =>
|
823 |
|
|
if(data_buffer_counter = '0') then
|
824 |
|
|
next_tx_state <= IDLE;
|
825 |
|
|
else
|
826 |
|
|
if(main_state = DATA) then
|
827 |
|
|
next_tx_state <= DATA_CMD;
|
828 |
|
|
else
|
829 |
|
|
next_tx_state <= DATA;
|
830 |
|
|
end if;
|
831 |
|
|
end if;
|
832 |
|
|
when DATA_CMD =>
|
833 |
|
|
if(tx_enable = '1') then
|
834 |
|
|
next_tx_state <= DATA;
|
835 |
|
|
else
|
836 |
|
|
next_tx_state <= DATA_CMD;
|
837 |
|
|
end if;
|
838 |
|
|
when DATA =>
|
839 |
|
|
if(crc_tx_done = '1') then
|
840 |
|
|
next_tx_state <= CRC;
|
841 |
|
|
else
|
842 |
|
|
next_tx_state <= DATA;
|
843 |
|
|
end if;
|
844 |
|
|
when CRC =>
|
845 |
|
|
if(crc_tx_done = '1' and tx_clk_en = '1') then
|
846 |
|
|
next_tx_state <= IDLE;
|
847 |
|
|
else
|
848 |
|
|
next_tx_state <= CRC;
|
849 |
|
|
end if;
|
850 |
|
|
when ERROR =>
|
851 |
|
|
next_tx_state <= IDLE;
|
852 |
|
|
end case;
|
853 |
|
|
end process;
|
854 |
|
|
|
855 |
|
|
|
856 |
|
|
process(rx_state, rx_valid, rx_data, rx_error, rx_clk, last_rx_clk) --Receive state machine
|
857 |
|
|
begin
|
858 |
|
|
case rx_state is
|
859 |
|
|
when IDLE =>
|
860 |
|
|
if(rx_valid = '1') then
|
861 |
|
|
if(rx_error = '1') then
|
862 |
|
|
next_rx_state <= ERROR;
|
863 |
|
|
else
|
864 |
|
|
next_rx_state <= CMD;
|
865 |
|
|
end if;
|
866 |
|
|
else
|
867 |
|
|
next_rx_state <= IDLE;
|
868 |
|
|
end if;
|
869 |
|
|
when CMD =>
|
870 |
|
|
if(rx_clk = '1' and last_rx_clk = '0') then
|
871 |
|
|
if(rx_valid = '1') then
|
872 |
|
|
if(rx_error = '1') then
|
873 |
|
|
next_rx_state <= ERROR;
|
874 |
|
|
else
|
875 |
|
|
next_rx_state <= DATA;
|
876 |
|
|
end if;
|
877 |
|
|
else
|
878 |
|
|
next_rx_state <= CRC;
|
879 |
|
|
end if;
|
880 |
|
|
else
|
881 |
|
|
next_rx_state <= CMD;
|
882 |
|
|
end if;
|
883 |
|
|
when DATA =>
|
884 |
|
|
if(rx_clk = '1' and last_rx_clk = '0') then
|
885 |
|
|
if(rx_valid = '1') then
|
886 |
|
|
if(rx_error = '1') then
|
887 |
|
|
next_rx_state <= ERROR;
|
888 |
|
|
else
|
889 |
|
|
next_rx_state <= DATA;
|
890 |
|
|
end if;
|
891 |
|
|
else
|
892 |
|
|
next_rx_state <= CRC;
|
893 |
|
|
end if;
|
894 |
|
|
else
|
895 |
|
|
next_rx_state <= DATA;
|
896 |
|
|
end if;
|
897 |
|
|
when CRC =>
|
898 |
|
|
next_rx_state <= IDLE;
|
899 |
|
|
when ERROR =>
|
900 |
|
|
next_rx_state <= IDLE;
|
901 |
|
|
end case;
|
902 |
|
|
end process;
|
903 |
|
|
|
904 |
|
|
|
905 |
|
|
|
906 |
|
|
buffer_full <= '1' when (data_buffer_counter = '1') or (input_available = '1') else '0';
|
907 |
|
|
|
908 |
|
|
--TosNet protocol interface input multiplexing
|
909 |
|
|
data_in <= data_in_master when master_dsc_enable = '1' else
|
910 |
|
|
data_in_net when net_dsc_enable = '1' else
|
911 |
|
|
data_in_reg when reg_dsc_enable = '1' else
|
912 |
|
|
data_in_ext when data_enable = '1' else
|
913 |
|
|
data_in_sync when sync_dsc_enable = '1' else --Sync needs to be last (or at least just after ext), as it will be kept enabled during operation... Same goes for the other two signals...
|
914 |
|
|
"00000000";
|
915 |
|
|
data_in_strobe <= data_in_strobe_master when master_dsc_enable = '1' else
|
916 |
|
|
data_in_strobe_net when net_dsc_enable = '1' else
|
917 |
|
|
data_in_strobe_reg when reg_dsc_enable = '1' else
|
918 |
|
|
data_in_strobe_ext when data_enable = '1' else
|
919 |
|
|
data_in_strobe_sync when sync_dsc_enable = '1' else
|
920 |
|
|
'0';
|
921 |
|
|
data_in_enable <= data_in_enable_master when master_dsc_enable = '1' else
|
922 |
|
|
data_in_enable_net when net_dsc_enable = '1' else
|
923 |
|
|
data_in_enable_reg when reg_dsc_enable = '1' else
|
924 |
|
|
data_in_enable_ext when data_enable = '1' else
|
925 |
|
|
data_in_enable_sync when sync_dsc_enable = '1' else
|
926 |
|
|
'0';
|
927 |
|
|
|
928 |
|
|
--Network register interface multiplexing
|
929 |
|
|
network_reg_internal_clk <= network_reg_internal_clk_net when net_dsc_enable = '1' else
|
930 |
|
|
network_reg_internal_clk_reg when reg_dsc_enable = '1' else
|
931 |
|
|
'0';
|
932 |
|
|
network_reg_internal_write_data <= network_reg_internal_write_data_net when net_dsc_enable = '1' else
|
933 |
|
|
network_reg_internal_write_data_reg when reg_dsc_enable = '1' else
|
934 |
|
|
"00000000";
|
935 |
|
|
network_reg_internal_addr <= network_reg_internal_addr_net when net_dsc_enable = '1' else
|
936 |
|
|
network_reg_internal_addr_reg when reg_dsc_enable = '1' else
|
937 |
|
|
"000000";
|
938 |
|
|
network_reg_internal_we <= network_reg_internal_we_net when net_dsc_enable = '1' else
|
939 |
|
|
network_reg_internal_we_reg when reg_dsc_enable = '1' else
|
940 |
|
|
"0";
|
941 |
|
|
|
942 |
|
|
--TosNet protocol interface output gating
|
943 |
|
|
data_out_ext <= data_out when data_enable = '1' else "00000000";
|
944 |
|
|
data_out_enable_ext <= data_out_enable when data_enable = '1' else '0';
|
945 |
|
|
data_out_strobe_ext <= data_out_strobe when data_enable = '1' else '0';
|
946 |
|
|
|
947 |
|
|
end Behavioral;
|
948 |
|
|
|