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sonicwave |
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-- Company: University of Southern Denmark
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-- Engineer: Simon Falsig
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--
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-- Create Date: 19/3/2009
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-- Design Name: TosNet
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-- Module Name: tpl_rx - Behavioral
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-- File Name: tpl_rx.vhd
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-- Project Name: TosNet
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-- Target Devices: Spartan3/6
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-- Tool versions: Xilinx ISE 12.2
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-- Description: The receive part of the TosNet physical layer.
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--
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-- Revision:
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-- Revision 3.2 - Initial release
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--
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-- Copyright 2010
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--
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-- This module is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU Lesser General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This module is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with this module. If not, see <http://www.gnu.org/licenses/>.
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity tpl_rx is
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Port ( data : out STD_LOGIC_VECTOR(7 downto 0);
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valid : out STD_LOGIC;
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error : out STD_LOGIC;
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clk_data : out STD_LOGIC;
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clk_50M : in STD_LOGIC;
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reset : in STD_LOGIC;
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sig_in : in STD_LOGIC);
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end tpl_rx;
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architecture Behavioral of tpl_rx is
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type STATES is (IDLE, QUIET, REC_START, REC_SEED, REC_DATA, REC_ERROR);
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signal state : STATES := IDLE;
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signal next_state : STATES := IDLE;
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signal sig_in_sync : STD_LOGIC := '0';
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signal last_sig_in_sync : STD_LOGIC := '0';
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signal in_buffer : STD_LOGIC_VECTOR(9 downto 0) := "0000000000";
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signal data_buffer : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
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signal bit_counter : STD_LOGIC_VECTOR(3 downto 0) := "0000";
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signal last_bit_counter : STD_LOGIC_VECTOR(3 downto 0) := "0000";
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signal clk_data_int : STD_LOGIC := '0';
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signal valid_int : STD_LOGIC := '0';
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signal bit_counter_synced : STD_LOGIC := '0';
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signal lfsr_rec_out : STD_LOGIC_VECTOR(7 downto 0);
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signal lfsr_rec_seed : STD_LOGIC_VECTOR(7 downto 0);
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signal lfsr_rec_reset : STD_LOGIC;
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signal lfsr_rec_clk : STD_LOGIC;
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signal lfsr_rec_clk_en : STD_LOGIC;
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signal dec_clk : STD_LOGIC;
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signal dec_clk_en : STD_LOGIC;
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signal dec_in : STD_LOGIC_VECTOR(9 downto 0);
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signal dec_out : STD_LOGIC_VECTOR(7 downto 0);
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signal dec_kout : STD_LOGIC;
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signal dec_code_err : STD_LOGIC;
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component lfsr is
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generic (
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lfsr_length : STD_LOGIC_VECTOR(7 downto 0);
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lfsr_out_length : STD_LOGIC_VECTOR(7 downto 0);
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lfsr_allow_zero : STD_LOGIC);
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port (
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lfsr_out : out STD_LOGIC_VECTOR((conv_integer(lfsr_out_length) - 1) downto 0);
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lfsr_seed : in STD_LOGIC_VECTOR((conv_integer(lfsr_length) - 1) downto 0);
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lfsr_reset : in STD_LOGIC;
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lfsr_clk : in STD_LOGIC;
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lfsr_clk_en : in STD_LOGIC);
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end component;
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component dec_8b10b is
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port (
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clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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din : in STD_LOGIC_VECTOR(9 downto 0);
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dout : out STD_LOGIC_VECTOR(7 downto 0);
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kout : out STD_LOGIC;
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code_err : out STD_LOGIC);
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end component;
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begin
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clk_data <= clk_data_int;
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valid <= valid_int and not dec_kout;
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lfsr_rec_clk <= clk_50M;
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lfsr_rec : lfsr
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Generic map ( lfsr_length => "00001000",
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lfsr_out_length => "00001000",
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lfsr_allow_zero => '0')
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Port map ( lfsr_out => lfsr_rec_out,
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lfsr_seed => lfsr_rec_seed,
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lfsr_reset => lfsr_rec_reset,
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lfsr_clk => lfsr_rec_clk,
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lfsr_clk_en => lfsr_rec_clk_en);
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dec_clk <= clk_50M;
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data_buffer <= dec_out xor lfsr_rec_out;
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dec : dec_8b10b
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Port map ( clk => dec_clk,
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ce => dec_clk_en,
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din => dec_in,
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dout => dec_out,
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kout => dec_kout,
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code_err => dec_code_err);
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process(clk_50M)
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variable sig_in_counter : STD_LOGIC_VECTOR(1 downto 0) := "00";
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begin
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if(clk_50M = '1' and clk_50M'event) then
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if(reset = '1') then
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state <= IDLE;
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else
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state <= next_state;
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end if;
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sig_in_sync <= sig_in;
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last_sig_in_sync <= sig_in_sync;
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if(last_sig_in_sync = sig_in_sync) then
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sig_in_counter := sig_in_counter + 1;
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else
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sig_in_counter := (others => '0');
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end if;
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if(sig_in_counter(1 downto 0) = "01") then --This should be the approximate middle of the bit cell
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in_buffer <= sig_in_sync & in_buffer(9 downto 1);
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bit_counter <= bit_counter + 1;
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if(bit_counter = 0) then
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dec_in <= in_buffer;
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clk_data_int <= '1';
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elsif(bit_counter = 5) then
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clk_data_int <= '0';
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end if;
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end if;
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if(bit_counter = 10) then
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bit_counter <= "0000";
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end if;
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if((bit_counter = 1) and (last_bit_counter = 0)) then
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dec_clk_en <= '1';
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else
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dec_clk_en <= '0';
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end if;
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lfsr_rec_clk_en <= dec_clk_en;
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last_bit_counter <= bit_counter;
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case state is
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when IDLE =>
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lfsr_rec_seed <= "00000000";
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data <= "00000000";
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valid_int <= '0';
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error <= '0';
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when QUIET =>
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bit_counter_synced <= '0';
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lfsr_rec_seed <= "00000000";
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lfsr_rec_reset <= '1';
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data <= "00000000";
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valid_int <= '0';
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error <= '0';
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when REC_START =>
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if(bit_counter_synced = '0') then
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bit_counter <= "0000";
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bit_counter_synced <= '1';
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end if;
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lfsr_rec_seed <= "00000000";
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lfsr_rec_reset <= '1';
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data <= "00000000";
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valid_int <= '0';
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error <= '0';
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when REC_SEED =>
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lfsr_rec_reset <= '1';
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if(bit_counter = 9) then
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lfsr_rec_seed <= dec_out;
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end if;
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data <= "00000000";
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valid_int <= '0';
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error <= '0';
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when REC_DATA =>
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lfsr_rec_reset <= '0';
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if(bit_counter = 2) then
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data <= data_buffer;
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valid_int <= '1';
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error <= '0';
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end if;
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when REC_ERROR =>
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error <= '1';
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end case;
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end if;
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end process;
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process(state, in_buffer, bit_counter, dec_kout, dec_code_err)
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begin
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case state is
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when IDLE =>
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next_state <= QUIET;
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when QUIET =>
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if(in_buffer = "0101111100" or in_buffer = "1010000011") then
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next_state <= REC_START;
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else
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next_state <= QUIET;
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end if;
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when REC_START =>
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if(bit_counter = 10) then
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next_state <= REC_SEED;
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else
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next_state <= REC_START;
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end if;
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when REC_SEED =>
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if(dec_code_err = '1') then --Need to wait until this state to check the decoder error output, as otherwise we may pick up the result of decoding something unaligned, resulting in a whole lot of errors that really aren't there...
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next_state <= REC_ERROR;
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elsif(bit_counter = 10) then
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next_state <= REC_DATA;
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else
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next_state <= REC_SEED;
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end if;
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when REC_DATA =>
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if(dec_code_err = '1') then
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next_state <= REC_ERROR;
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elsif(bit_counter = 10 and dec_kout = '1') then
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next_state <= QUIET;
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else
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next_state <= REC_DATA;
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end if;
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when REC_ERROR =>
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next_state <= QUIET;
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end case;
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end process;
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end Behavioral;
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