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sonicwave |
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-- Company: University of Southern Denmark
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-- Engineer: Simon Falsig
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--
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-- Create Date: 12/3/2009
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-- Design Name: TosNet
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-- Module Name: tdl_tx - Behavioral
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-- File Name: tdl_tx.vhd
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-- Project Name: TosNet
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-- Target Devices: Spartan3/6
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-- Tool versions: Xilinx ISE 12.2
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-- Description: The transmit part of the TosNet physical layer.
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--
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-- Revision:
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-- Revision 3.2 - Initial release
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--
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-- Copyright 2010
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--
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-- This module is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU Lesser General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This module is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with this module. If not, see <http://www.gnu.org/licenses/>.
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--------------------------------------------------------------------------------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity tpl_tx is
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Port ( data : in STD_LOGIC_VECTOR(7 downto 0);
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clk_50M : in STD_LOGIC;
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clk_data_en : out STD_LOGIC;
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enable : in STD_LOGIC;
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reset : in STD_LOGIC;
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sig_out : out STD_LOGIC;
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clk_div_reset : in STD_LOGIC;
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clk_div_reset_ack : out STD_LOGIC);
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end tpl_tx;
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architecture Behavioral of tpl_tx is
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constant LFSR_INITIAL_SEED : STD_LOGIC_VECTOR(7 downto 0) := "01010101";
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constant K_COMMA_1 : STD_LOGIC_VECTOR(7 downto 0) := "00111100";
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constant K_COMMA_2 : STD_LOGIC_VECTOR(7 downto 0) := "10111100";
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signal last_clk_div_reset : STD_LOGIC;
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signal reset_clk_div : STD_LOGIC := '0';
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signal clk_div : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
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signal clk_en_12M5 : STD_LOGIC;
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signal clk_en_1M25_0 : STD_LOGIC;
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signal clk_en_1M25_1 : STD_LOGIC;
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signal clk_en_1M25_2 : STD_LOGIC;
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signal clk_en_1M25_3 : STD_LOGIC;
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signal data_buffer_1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
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signal data_buffer_2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
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signal data_buffer_3 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
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signal enable_buffer_1 : STD_LOGIC := '0';
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signal enable_buffer_2 : STD_LOGIC := '0';
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signal out_buffer : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
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type STATES is (IDLE, TRN_START, TRN_SEED, TRN_DATA);
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signal state : STATES := IDLE;
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signal next_state : STATES := IDLE;
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signal lfsr_seed_out : STD_LOGIC_VECTOR(7 downto 0);
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signal lfsr_seed_seed : STD_LOGIC_VECTOR(7 downto 0);
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signal lfsr_seed_reset : STD_LOGIC;
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signal lfsr_seed_clk : STD_LOGIC;
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signal lfsr_seed_clk_en : STD_LOGIC;
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signal lfsr_trn_out : STD_LOGIC_VECTOR(7 downto 0);
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signal lfsr_trn_seed : STD_LOGIC_VECTOR(7 downto 0);
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signal lfsr_trn_reset : STD_LOGIC;
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signal lfsr_trn_clk : STD_LOGIC;
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signal lfsr_trn_clk_en : STD_LOGIC;
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signal enc_in : STD_LOGIC_VECTOR(7 downto 0) := K_COMMA_1;
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signal enc_out : STD_LOGIC_VECTOR(9 downto 0);
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signal enc_kin : STD_LOGIC := '1';
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signal enc_clk : STD_LOGIC;
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signal enc_clk_en : STD_LOGIC;
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component lfsr is
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generic (
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lfsr_length : STD_LOGIC_VECTOR(7 downto 0);
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lfsr_out_length : STD_LOGIC_VECTOR(7 downto 0);
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lfsr_allow_zero : STD_LOGIC);
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port (
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lfsr_out : out STD_LOGIC_VECTOR((conv_integer(lfsr_out_length) - 1) downto 0);
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lfsr_seed : in STD_LOGIC_VECTOR((conv_integer(lfsr_length) - 1) downto 0);
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lfsr_reset : in STD_LOGIC;
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lfsr_clk : in STD_LOGIC;
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lfsr_clk_en : in STD_LOGIC);
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end component;
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component enc_8b10b is
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port (
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din : in STD_LOGIC_VECTOR(7 downto 0);
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kin : in STD_LOGIC;
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clk : in STD_LOGIC;
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dout : out STD_LOGIC_VECTOR(9 downto 0);
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ce : in STD_LOGIC);
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end component;
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begin
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clk_data_en <= clk_en_1M25_0;
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lfsr_seed_seed <= LFSR_INITIAL_SEED;
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lfsr_seed_clk <= clk_50M;
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lfsr_seed_reset <= reset;
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lfsr_trn_clk <= clk_50M;
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lfsr_trn_clk_en <= clk_en_1M25_1;
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lfsr_seed : lfsr
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Generic map ( lfsr_length => "00001000",
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lfsr_out_length => "00001000",
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lfsr_allow_zero => '0')
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Port map ( lfsr_out => lfsr_seed_out,
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lfsr_seed => lfsr_seed_seed,
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lfsr_reset => lfsr_seed_reset,
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lfsr_clk => lfsr_seed_clk,
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lfsr_clk_en => lfsr_seed_clk_en);
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lfsr_trn : lfsr
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Generic map ( lfsr_length => "00001000",
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lfsr_out_length => "00001000",
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lfsr_allow_zero => '0')
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Port map ( lfsr_out => lfsr_trn_out,
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lfsr_seed => lfsr_trn_seed,
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lfsr_reset => lfsr_trn_reset,
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lfsr_clk => lfsr_trn_clk,
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lfsr_clk_en => lfsr_trn_clk_en);
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enc : enc_8b10b
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Port map ( din => enc_in,
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kin => enc_kin,
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clk => enc_clk,
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dout => enc_out,
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ce => enc_clk_en);
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enc_clk <= clk_50M;
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enc_clk_en <= clk_en_1M25_2;
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process(clk_50M)
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begin
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if(clk_50M = '1' and clk_50M'event) then
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if(clk_div_reset = '1' and last_clk_div_reset = '0') then
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reset_clk_div <= '1';
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elsif(clk_div_reset = '0') then
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clk_div_reset_ack <= '0';
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end if;
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if(reset_clk_div = '1' and clk_div(1 downto 0) = "11") then
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clk_div <= "100100";
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reset_clk_div <= '0';
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clk_div_reset_ack <= '1';
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else
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if(clk_div = 39) then
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clk_div <= (others => '0');
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else
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clk_div <= clk_div + 1;
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end if;
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end if;
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last_clk_div_reset <= clk_div_reset;
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end if;
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end process;
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clk_en_12M5 <= '1' when clk_div(1 downto 0) = "11" else '0'; --Sync the phase to clk_en_1M25_3
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clk_en_1M25_0 <= '1' when clk_div = "000000" else '0'; --We're using phase-shifted versions of the clock-enables to minimize the latency of the system, as all the parts are perfectly pipelined anyway
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clk_en_1M25_1 <= '1' when clk_div = "000001" else '0';
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clk_en_1M25_2 <= '1' when clk_div = "000010" else '0';
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clk_en_1M25_3 <= '1' when clk_div = "000011" else '0';
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lfsr_trn_seed <= lfsr_seed_out;
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process(clk_50M)
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begin
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if(clk_50M = '1' and clk_50M'event) then
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if(reset = '1') then
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state <= IDLE;
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elsif(clk_en_1M25_1 = '1') then
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state <= next_state;
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data_buffer_3 <= data_buffer_2;
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data_buffer_2 <= data_buffer_1;
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data_buffer_1 <= data;
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enable_buffer_2 <= enable_buffer_1;
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enable_buffer_1 <= enable;
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end if;
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end if;
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end process;
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process(state, lfsr_trn_seed, data_buffer_3, lfsr_trn_out, clk_en_1M25_1)
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begin
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case state is
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when IDLE =>
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enc_in <= K_COMMA_1;
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enc_kin <= '1';
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lfsr_trn_reset <= '1';
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lfsr_seed_clk_en <= clk_en_1M25_1;
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when TRN_START =>
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enc_in <= K_COMMA_2;
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enc_kin <= '1';
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lfsr_trn_reset <= '1';
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lfsr_seed_clk_en <= '0';
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when TRN_SEED =>
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enc_in <= lfsr_trn_seed;
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enc_kin <= '0';
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lfsr_trn_reset <= '0';
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lfsr_seed_clk_en <= '0';
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when TRN_DATA =>
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enc_in <= data_buffer_3 xor lfsr_trn_out;
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enc_kin <= '0';
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lfsr_trn_reset <= '0';
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lfsr_seed_clk_en <= '0';
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end case;
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end process;
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process(clk_50M)
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begin
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if(clk_50M = '1' and clk_50M'event) then
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if(reset = '1') then
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out_buffer <= (others => '0');
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sig_out <= '0';
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elsif(clk_en_12M5 = '1') then
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if(clk_en_1M25_3 = '1') then
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out_buffer <= enc_out;
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else
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out_buffer <= '0' & out_buffer(9 downto 1);
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end if;
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sig_out <= out_buffer(0);
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end if;
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end if;
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end process;
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process(state, enable, enable_buffer_2)
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begin
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case state is
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when IDLE =>
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if(enable = '1') then
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next_state <= TRN_START;
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else
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next_state <= IDLE;
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end if;
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when TRN_START =>
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next_state <= TRN_SEED;
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when TRN_SEED =>
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next_state <= TRN_DATA;
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when TRN_DATA =>
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if(enable_buffer_2 = '1') then
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next_state <= TRN_DATA;
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else
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next_state <= IDLE;
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end if;
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end case;
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end process;
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end Behavioral;
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