URL https://opencores.org/ocsvn/ts7300_opencore/ts7300_opencore/trunk

Subversion Repositories ts7300_opencore

[/] [ts7300_opencore/] [trunk/] [ethernet/] [eth_cop.v] - Blame information for rev 6

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_cop.v                                                   ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001, 2002 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2003/06/13 11:55:37  mohor
// Define file in eth_cop.v is changed to eth_defines.v. Some defines were
// moved from tb_eth_defines.v to eth_defines.v.
//
// Revision 1.3  2002/10/10 16:43:59  mohor
// Minor $display change.
//
// Revision 1.2  2002/09/09 12:54:13  mohor
// error acknowledge cycle termination added to display.
//
// Revision 1.1  2002/08/14 17:16:07  mohor
// Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
// interfaces:
// - Host connects to the master interface
// - Ethernet master (DMA) connects to the second master interface
// - Memory interface connects to the slave interface
// - Ethernet slave interface (access to registers and BDs) connects to second
//   slave interface
//
//
//
//
//
 
`include "eth_defines.v"
`include "timescale.v"
 
module eth_cop
(
  // WISHBONE common
  wb_clk_i, wb_rst_i,
 
  // WISHBONE MASTER 1
  m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i,  m1_wb_dat_o,
  m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o,
  m1_wb_err_o,
 
  // WISHBONE MASTER 2
  m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i,  m2_wb_dat_o,
  m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o,
  m2_wb_err_o,
 
  // WISHBONE slave 1
        s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o,  s1_wb_cyc_o,
        s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i,
        s1_wb_dat_o,
 
  // WISHBONE slave 2
        s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o,  s2_wb_cyc_o,
        s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
        s2_wb_dat_o
);
 
parameter Tp=1;
 
// WISHBONE common
input wb_clk_i, wb_rst_i;
 
// WISHBONE MASTER 1
input  [31:0] m1_wb_adr_i, m1_wb_dat_i;
input   [3:0] m1_wb_sel_i;
input         m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i;
output [31:0] m1_wb_dat_o;
output        m1_wb_ack_o, m1_wb_err_o;
 
// WISHBONE MASTER 2
input  [31:0] m2_wb_adr_i, m2_wb_dat_i;
input   [3:0] m2_wb_sel_i;
input         m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i;
output [31:0] m2_wb_dat_o;
output        m2_wb_ack_o, m2_wb_err_o;
 
// WISHBONE slave 1
input  [31:0] s1_wb_dat_i;
input         s1_wb_ack_i, s1_wb_err_i;
output [31:0] s1_wb_adr_o, s1_wb_dat_o;
output  [3:0] s1_wb_sel_o;
output        s1_wb_we_o,  s1_wb_cyc_o, s1_wb_stb_o;
 
// WISHBONE slave 2
input  [31:0] s2_wb_dat_i;
input         s2_wb_ack_i, s2_wb_err_i;
output [31:0] s2_wb_adr_o, s2_wb_dat_o;
output  [3:0] s2_wb_sel_o;
output        s2_wb_we_o,  s2_wb_cyc_o, s2_wb_stb_o;
 
reg           m1_in_progress;
reg           m2_in_progress;
reg    [31:0] s1_wb_adr_o;
reg     [3:0] s1_wb_sel_o;
reg           s1_wb_we_o;
reg    [31:0] s1_wb_dat_o;
reg           s1_wb_cyc_o;
reg           s1_wb_stb_o;
reg    [31:0] s2_wb_adr_o;
reg     [3:0] s2_wb_sel_o;
reg           s2_wb_we_o;
reg    [31:0] s2_wb_dat_o;
reg           s2_wb_cyc_o;
reg           s2_wb_stb_o;
 
reg           m1_wb_ack_o;
reg    [31:0] m1_wb_dat_o;
reg           m2_wb_ack_o;
reg    [31:0] m2_wb_dat_o;
 
reg           m1_wb_err_o;
reg           m2_wb_err_o;
 
wire m_wb_access_finished;
wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (`M1_ADDRESSED_S1 | `M1_ADDRESSED_S2);
wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (`M2_ADDRESSED_S1 | `M2_ADDRESSED_S2);
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if(wb_rst_i)
    begin
      m1_in_progress <=#Tp 0;
      m2_in_progress <=#Tp 0;
      s1_wb_adr_o    <=#Tp 0;
      s1_wb_sel_o    <=#Tp 0;
      s1_wb_we_o     <=#Tp 0;
      s1_wb_dat_o    <=#Tp 0;
      s1_wb_cyc_o    <=#Tp 0;
      s1_wb_stb_o    <=#Tp 0;
      s2_wb_adr_o    <=#Tp 0;
      s2_wb_sel_o    <=#Tp 0;
      s2_wb_we_o     <=#Tp 0;
      s2_wb_dat_o    <=#Tp 0;
      s2_wb_cyc_o    <=#Tp 0;
      s2_wb_stb_o    <=#Tp 0;
    end
  else
    begin
      case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished})  // synopsys_full_case synopsys_paralel_case
        5'b00_10_0, 5'b00_11_0 :
          begin
            m1_in_progress <=#Tp 1'b1;  // idle: m1 or (m1 & m2) want access: m1 -> m
            if(`M1_ADDRESSED_S1)
              begin
                s1_wb_adr_o <=#Tp m1_wb_adr_i;
                s1_wb_sel_o <=#Tp m1_wb_sel_i;
                s1_wb_we_o  <=#Tp m1_wb_we_i;
                s1_wb_dat_o <=#Tp m1_wb_dat_i;
                s1_wb_cyc_o <=#Tp 1'b1;
                s1_wb_stb_o <=#Tp 1'b1;
              end
            else if(`M1_ADDRESSED_S2)
              begin
                s2_wb_adr_o <=#Tp m1_wb_adr_i;
                s2_wb_sel_o <=#Tp m1_wb_sel_i;
                s2_wb_we_o  <=#Tp m1_wb_we_i;
                s2_wb_dat_o <=#Tp m1_wb_dat_i;
                s2_wb_cyc_o <=#Tp 1'b1;
                s2_wb_stb_o <=#Tp 1'b1;
              end
            else
              $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
          end
        5'b00_01_0 :
          begin
            m2_in_progress <=#Tp 1'b1;  // idle: m2 wants access: m2 -> m
            if(`M2_ADDRESSED_S1)
              begin
                s1_wb_adr_o <=#Tp m2_wb_adr_i;
                s1_wb_sel_o <=#Tp m2_wb_sel_i;
                s1_wb_we_o  <=#Tp m2_wb_we_i;
                s1_wb_dat_o <=#Tp m2_wb_dat_i;
                s1_wb_cyc_o <=#Tp 1'b1;
                s1_wb_stb_o <=#Tp 1'b1;
              end
            else if(`M2_ADDRESSED_S2)
              begin
                s2_wb_adr_o <=#Tp m2_wb_adr_i;
                s2_wb_sel_o <=#Tp m2_wb_sel_i;
                s2_wb_we_o  <=#Tp m2_wb_we_i;
                s2_wb_dat_o <=#Tp m2_wb_dat_i;
                s2_wb_cyc_o <=#Tp 1'b1;
                s2_wb_stb_o <=#Tp 1'b1;
              end
            else
              $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
          end
        5'b10_10_1, 5'b10_11_1 :
          begin
            m1_in_progress <=#Tp 1'b0;  // m1 in progress. Cycle is finished. Send ack or err to m1.
            if(`M1_ADDRESSED_S1)
              begin
                s1_wb_cyc_o <=#Tp 1'b0;
                s1_wb_stb_o <=#Tp 1'b0;
              end
            else if(`M1_ADDRESSED_S2)
              begin
                s2_wb_cyc_o <=#Tp 1'b0;
                s2_wb_stb_o <=#Tp 1'b0;
              end
          end
        5'b01_01_1, 5'b01_11_1 :
          begin
            m2_in_progress <=#Tp 1'b0;  // m2 in progress. Cycle is finished. Send ack or err to m2.
            if(`M2_ADDRESSED_S1)
              begin
                s1_wb_cyc_o <=#Tp 1'b0;
                s1_wb_stb_o <=#Tp 1'b0;
              end
            else if(`M2_ADDRESSED_S2)
              begin
                s2_wb_cyc_o <=#Tp 1'b0;
                s2_wb_stb_o <=#Tp 1'b0;
              end
          end
      endcase
    end
end
 
// Generating Ack for master 1
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M1_ADDRESSED_S1 or `M1_ADDRESSED_S2)
begin
  if(m1_in_progress)
    begin
      if(`M1_ADDRESSED_S1) begin
        m1_wb_ack_o <= s1_wb_ack_i;
        m1_wb_dat_o <= s1_wb_dat_i;
      end
      else if(`M1_ADDRESSED_S2) begin
        m1_wb_ack_o <= s2_wb_ack_i;
        m1_wb_dat_o <= s2_wb_dat_i;
      end
    end
  else
    m1_wb_ack_o <= 0;
end
 
 
// Generating Ack for master 2
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2)
begin
  if(m2_in_progress)
    begin
      if(`M2_ADDRESSED_S1) begin
        m2_wb_ack_o <= s1_wb_ack_i;
        m2_wb_dat_o <= s1_wb_dat_i;
      end
      else if(`M2_ADDRESSED_S2) begin
        m2_wb_ack_o <= s2_wb_ack_i;
        m2_wb_dat_o <= s2_wb_dat_i;
      end
    end
  else
    m2_wb_ack_o <= 0;
end
 
 
// Generating Err for master 1
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
          m1_wb_cyc_i or m1_wb_stb_i)
begin
  if(m1_in_progress)  begin
    if(`M1_ADDRESSED_S1)
      m1_wb_err_o <= s1_wb_err_i;
    else if(`M1_ADDRESSED_S2)
      m1_wb_err_o <= s2_wb_err_i;
  end
  else if(m1_wb_cyc_i & m1_wb_stb_i & ~`M1_ADDRESSED_S1 & ~`M1_ADDRESSED_S2)
    m1_wb_err_o <= 1'b1;
  else
    m1_wb_err_o <= 1'b0;
end
 
 
// Generating Err for master 2
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
          m2_wb_cyc_i or m2_wb_stb_i)
begin
  if(m2_in_progress)  begin
    if(`M2_ADDRESSED_S1)
      m2_wb_err_o <= s1_wb_err_i;
    else if(`M2_ADDRESSED_S2)
      m2_wb_err_o <= s2_wb_err_i;
  end
  else if(m2_wb_cyc_i & m2_wb_stb_i & ~`M2_ADDRESSED_S1 & ~`M2_ADDRESSED_S2)
    m2_wb_err_o <= 1'b1;
  else
    m2_wb_err_o <= 1'b0;
end
 
 
assign m_wb_access_finished = m1_wb_ack_o | m1_wb_err_o | m2_wb_ack_o | m2_wb_err_o;
 
 
// Activity monitor
integer cnt;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if(wb_rst_i)
    cnt <=#Tp 0;
  else
  if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i)
    cnt <=#Tp 0;
  else
  if(s1_wb_cyc_o | s2_wb_cyc_o)
    cnt <=#Tp cnt+1;
end
 
always @ (posedge wb_clk_i)
begin
  if(cnt==1000) begin
    $display("(%0t)(%m) ERROR: WB activity ??? ", $time);
    if(s1_wb_cyc_o) begin
      $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
      $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
      $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
      $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
    end
    else if(s2_wb_cyc_o) begin
      $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
      $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
      $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
      $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
    end
 
    $stop;
  end
end
 
 
always @ (posedge wb_clk_i)
begin
  if(s1_wb_err_i & s1_wb_cyc_o) begin
    $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
    $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
    $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
    $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
    $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
    $stop;
  end
  if(s2_wb_err_i & s2_wb_cyc_o) begin
    $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
    $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
    $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
    $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
    $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
    $stop;
  end
end
 
 
 
endmodule

Browse

Tools

Subversion Repositories ts7300_opencore

[/] [ts7300_opencore/] [trunk/] [ethernet/] [eth_cop.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	2	joff	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_cop.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects/ethmac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001, 2002 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44			`// Revision 1.4 2003/06/13 11:55:37 mohor`
45			`// Define file in eth_cop.v is changed to eth_defines.v. Some defines were`
46			`// moved from tb_eth_defines.v to eth_defines.v.`
47			`//`
48			`// Revision 1.3 2002/10/10 16:43:59 mohor`
49			`// Minor $display change.`
50			`//`
51			`// Revision 1.2 2002/09/09 12:54:13 mohor`
52			`// error acknowledge cycle termination added to display.`
53			`//`
54			`// Revision 1.1 2002/08/14 17:16:07 mohor`
55			`// Traffic cop with 2 wishbone master interfaces and 2 wishbona slave`
56			`// interfaces:`
57			`// - Host connects to the master interface`
58			`// - Ethernet master (DMA) connects to the second master interface`
59			`// - Memory interface connects to the slave interface`
60			`// - Ethernet slave interface (access to registers and BDs) connects to second`
61			`// slave interface`
62			`//`
63			`//`
64			`//`
65			`//`
66			`//`
67
68			`include "eth_defines.v"
69			`include "timescale.v"
70
71			`module eth_cop`
72			`(`
73			`// WISHBONE common`
74			`wb_clk_i, wb_rst_i,`
75
76			`// WISHBONE MASTER 1`
77			`m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i, m1_wb_dat_o,`
78			`m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o,`
79			`m1_wb_err_o,`
80
81			`// WISHBONE MASTER 2`
82			`m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i, m2_wb_dat_o,`
83			`m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o,`
84			`m2_wb_err_o,`
85
86			`// WISHBONE slave 1`
87			`s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o, s1_wb_cyc_o,`
88			`s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i,`
89			`s1_wb_dat_o,`
90
91			`// WISHBONE slave 2`
92			`s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o, s2_wb_cyc_o,`
93			`s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,`
94			`s2_wb_dat_o`
95			`);`
96
97			`parameter Tp=1;`
98
99			`// WISHBONE common`
100			`input wb_clk_i, wb_rst_i;`
101
102			`// WISHBONE MASTER 1`
103			`input [31:0] m1_wb_adr_i, m1_wb_dat_i;`
104			`input [3:0] m1_wb_sel_i;`
105			`input m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i;`
106			`output [31:0] m1_wb_dat_o;`
107			`output m1_wb_ack_o, m1_wb_err_o;`
108
109			`// WISHBONE MASTER 2`
110			`input [31:0] m2_wb_adr_i, m2_wb_dat_i;`
111			`input [3:0] m2_wb_sel_i;`
112			`input m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i;`
113			`output [31:0] m2_wb_dat_o;`
114			`output m2_wb_ack_o, m2_wb_err_o;`
115
116			`// WISHBONE slave 1`
117			`input [31:0] s1_wb_dat_i;`
118			`input s1_wb_ack_i, s1_wb_err_i;`
119			`output [31:0] s1_wb_adr_o, s1_wb_dat_o;`
120			`output [3:0] s1_wb_sel_o;`
121			`output s1_wb_we_o, s1_wb_cyc_o, s1_wb_stb_o;`
122
123			`// WISHBONE slave 2`
124			`input [31:0] s2_wb_dat_i;`
125			`input s2_wb_ack_i, s2_wb_err_i;`
126			`output [31:0] s2_wb_adr_o, s2_wb_dat_o;`
127			`output [3:0] s2_wb_sel_o;`
128			`output s2_wb_we_o, s2_wb_cyc_o, s2_wb_stb_o;`
129
130			`reg m1_in_progress;`
131			`reg m2_in_progress;`
132			`reg [31:0] s1_wb_adr_o;`
133			`reg [3:0] s1_wb_sel_o;`
134			`reg s1_wb_we_o;`
135			`reg [31:0] s1_wb_dat_o;`
136			`reg s1_wb_cyc_o;`
137			`reg s1_wb_stb_o;`
138			`reg [31:0] s2_wb_adr_o;`
139			`reg [3:0] s2_wb_sel_o;`
140			`reg s2_wb_we_o;`
141			`reg [31:0] s2_wb_dat_o;`
142			`reg s2_wb_cyc_o;`
143			`reg s2_wb_stb_o;`
144
145			`reg m1_wb_ack_o;`
146			`reg [31:0] m1_wb_dat_o;`
147			`reg m2_wb_ack_o;`
148			`reg [31:0] m2_wb_dat_o;`
149
150			`reg m1_wb_err_o;`
151			`reg m2_wb_err_o;`
152
153			`wire m_wb_access_finished;`
154			wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (`M1_ADDRESSED_S1 \| `M1_ADDRESSED_S2);
155			wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (`M2_ADDRESSED_S1 \| `M2_ADDRESSED_S2);
156
157			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
158			`begin`
159			`if(wb_rst_i)`
160			`begin`
161			`m1_in_progress <=#Tp 0;`
162			`m2_in_progress <=#Tp 0;`
163			`s1_wb_adr_o <=#Tp 0;`
164			`s1_wb_sel_o <=#Tp 0;`
165			`s1_wb_we_o <=#Tp 0;`
166			`s1_wb_dat_o <=#Tp 0;`
167			`s1_wb_cyc_o <=#Tp 0;`
168			`s1_wb_stb_o <=#Tp 0;`
169			`s2_wb_adr_o <=#Tp 0;`
170			`s2_wb_sel_o <=#Tp 0;`
171			`s2_wb_we_o <=#Tp 0;`
172			`s2_wb_dat_o <=#Tp 0;`
173			`s2_wb_cyc_o <=#Tp 0;`
174			`s2_wb_stb_o <=#Tp 0;`
175			`end`
176			`else`
177			`begin`
178			`case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished}) // synopsys_full_case synopsys_paralel_case`
179			`5'b00_10_0, 5'b00_11_0 :`
180			`begin`
181			`m1_in_progress <=#Tp 1'b1; // idle: m1 or (m1 & m2) want access: m1 -> m`
182			if(`M1_ADDRESSED_S1)
183			`begin`
184			`s1_wb_adr_o <=#Tp m1_wb_adr_i;`
185			`s1_wb_sel_o <=#Tp m1_wb_sel_i;`
186			`s1_wb_we_o <=#Tp m1_wb_we_i;`
187			`s1_wb_dat_o <=#Tp m1_wb_dat_i;`
188			`s1_wb_cyc_o <=#Tp 1'b1;`
189			`s1_wb_stb_o <=#Tp 1'b1;`
190			`end`
191			else if(`M1_ADDRESSED_S2)
192			`begin`
193			`s2_wb_adr_o <=#Tp m1_wb_adr_i;`
194			`s2_wb_sel_o <=#Tp m1_wb_sel_i;`
195			`s2_wb_we_o <=#Tp m1_wb_we_i;`
196			`s2_wb_dat_o <=#Tp m1_wb_dat_i;`
197			`s2_wb_cyc_o <=#Tp 1'b1;`
198			`s2_wb_stb_o <=#Tp 1'b1;`
199			`end`
200			`else`
201			`$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);`
202			`end`
203			`5'b00_01_0 :`
204			`begin`
205			`m2_in_progress <=#Tp 1'b1; // idle: m2 wants access: m2 -> m`
206			if(`M2_ADDRESSED_S1)
207			`begin`
208			`s1_wb_adr_o <=#Tp m2_wb_adr_i;`
209			`s1_wb_sel_o <=#Tp m2_wb_sel_i;`
210			`s1_wb_we_o <=#Tp m2_wb_we_i;`
211			`s1_wb_dat_o <=#Tp m2_wb_dat_i;`
212			`s1_wb_cyc_o <=#Tp 1'b1;`
213			`s1_wb_stb_o <=#Tp 1'b1;`
214			`end`
215			else if(`M2_ADDRESSED_S2)
216			`begin`
217			`s2_wb_adr_o <=#Tp m2_wb_adr_i;`
218			`s2_wb_sel_o <=#Tp m2_wb_sel_i;`
219			`s2_wb_we_o <=#Tp m2_wb_we_i;`
220			`s2_wb_dat_o <=#Tp m2_wb_dat_i;`
221			`s2_wb_cyc_o <=#Tp 1'b1;`
222			`s2_wb_stb_o <=#Tp 1'b1;`
223			`end`
224			`else`
225			`$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);`
226			`end`
227			`5'b10_10_1, 5'b10_11_1 :`
228			`begin`
229			`m1_in_progress <=#Tp 1'b0; // m1 in progress. Cycle is finished. Send ack or err to m1.`
230			if(`M1_ADDRESSED_S1)
231			`begin`
232			`s1_wb_cyc_o <=#Tp 1'b0;`
233			`s1_wb_stb_o <=#Tp 1'b0;`
234			`end`
235			else if(`M1_ADDRESSED_S2)
236			`begin`
237			`s2_wb_cyc_o <=#Tp 1'b0;`
238			`s2_wb_stb_o <=#Tp 1'b0;`
239			`end`
240			`end`
241			`5'b01_01_1, 5'b01_11_1 :`
242			`begin`
243			`m2_in_progress <=#Tp 1'b0; // m2 in progress. Cycle is finished. Send ack or err to m2.`
244			if(`M2_ADDRESSED_S1)
245			`begin`
246			`s1_wb_cyc_o <=#Tp 1'b0;`
247			`s1_wb_stb_o <=#Tp 1'b0;`
248			`end`
249			else if(`M2_ADDRESSED_S2)
250			`begin`
251			`s2_wb_cyc_o <=#Tp 1'b0;`
252			`s2_wb_stb_o <=#Tp 1'b0;`
253			`end`
254			`end`
255			`endcase`
256			`end`
257			`end`
258
259			`// Generating Ack for master 1`
260			always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M1_ADDRESSED_S1 or `M1_ADDRESSED_S2)
261			`begin`
262			`if(m1_in_progress)`
263			`begin`
264			if(`M1_ADDRESSED_S1) begin
265			`m1_wb_ack_o <= s1_wb_ack_i;`
266			`m1_wb_dat_o <= s1_wb_dat_i;`
267			`end`
268			else if(`M1_ADDRESSED_S2) begin
269			`m1_wb_ack_o <= s2_wb_ack_i;`
270			`m1_wb_dat_o <= s2_wb_dat_i;`
271			`end`
272			`end`
273			`else`
274			`m1_wb_ack_o <= 0;`
275			`end`
276
277
278			`// Generating Ack for master 2`
279			always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2)
280			`begin`
281			`if(m2_in_progress)`
282			`begin`
283			if(`M2_ADDRESSED_S1) begin
284			`m2_wb_ack_o <= s1_wb_ack_i;`
285			`m2_wb_dat_o <= s1_wb_dat_i;`
286			`end`
287			else if(`M2_ADDRESSED_S2) begin
288			`m2_wb_ack_o <= s2_wb_ack_i;`
289			`m2_wb_dat_o <= s2_wb_dat_i;`
290			`end`
291			`end`
292			`else`
293			`m2_wb_ack_o <= 0;`
294			`end`
295
296
297			`// Generating Err for master 1`
298			always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
299			`m1_wb_cyc_i or m1_wb_stb_i)`
300			`begin`
301			`if(m1_in_progress) begin`
302			if(`M1_ADDRESSED_S1)
303			`m1_wb_err_o <= s1_wb_err_i;`
304			else if(`M1_ADDRESSED_S2)
305			`m1_wb_err_o <= s2_wb_err_i;`
306			`end`
307			else if(m1_wb_cyc_i & m1_wb_stb_i & ~`M1_ADDRESSED_S1 & ~`M1_ADDRESSED_S2)
308			`m1_wb_err_o <= 1'b1;`
309			`else`
310			`m1_wb_err_o <= 1'b0;`
311			`end`
312
313
314			`// Generating Err for master 2`
315			always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
316			`m2_wb_cyc_i or m2_wb_stb_i)`
317			`begin`
318			`if(m2_in_progress) begin`
319			if(`M2_ADDRESSED_S1)
320			`m2_wb_err_o <= s1_wb_err_i;`
321			else if(`M2_ADDRESSED_S2)
322			`m2_wb_err_o <= s2_wb_err_i;`
323			`end`
324			else if(m2_wb_cyc_i & m2_wb_stb_i & ~`M2_ADDRESSED_S1 & ~`M2_ADDRESSED_S2)
325			`m2_wb_err_o <= 1'b1;`
326			`else`
327			`m2_wb_err_o <= 1'b0;`
328			`end`
329
330
331			`assign m_wb_access_finished = m1_wb_ack_o \| m1_wb_err_o \| m2_wb_ack_o \| m2_wb_err_o;`
332
333
334			`// Activity monitor`
335			`integer cnt;`
336			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
337			`begin`
338			`if(wb_rst_i)`
339			`cnt <=#Tp 0;`
340			`else`
341			`if(s1_wb_ack_i \| s1_wb_err_i \| s2_wb_ack_i \| s2_wb_err_i)`
342			`cnt <=#Tp 0;`
343			`else`
344			`if(s1_wb_cyc_o \| s2_wb_cyc_o)`
345			`cnt <=#Tp cnt+1;`
346			`end`
347
348			`always @ (posedge wb_clk_i)`
349			`begin`
350			`if(cnt==1000) begin`
351			`$display("(%0t)(%m) ERROR: WB activity ??? ", $time);`
352			`if(s1_wb_cyc_o) begin`
353			`$display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);`
354			`$display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);`
355			`$display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);`
356			`$display("s1_wb_we_o = 0x%0x", s1_wb_we_o);`
357			`end`
358			`else if(s2_wb_cyc_o) begin`
359			`$display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);`
360			`$display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);`
361			`$display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);`
362			`$display("s2_wb_we_o = 0x%0x", s2_wb_we_o);`
363			`end`
364
365			`$stop;`
366			`end`
367			`end`
368
369
370			`always @ (posedge wb_clk_i)`
371			`begin`
372			`if(s1_wb_err_i & s1_wb_cyc_o) begin`
373			`$display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);`
374			`$display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);`
375			`$display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);`
376			`$display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);`
377			`$display("s1_wb_we_o = 0x%0x", s1_wb_we_o);`
378			`$stop;`
379			`end`
380			`if(s2_wb_err_i & s2_wb_cyc_o) begin`
381			`$display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);`
382			`$display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);`
383			`$display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);`
384			`$display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);`
385			`$display("s2_wb_we_o = 0x%0x", s2_wb_we_o);`
386			`$stop;`
387			`end`
388			`end`
389
390
391
392			`endmodule`