OpenCores
URL https://opencores.org/ocsvn/ts7300_opencore/ts7300_opencore/trunk

Subversion Repositories ts7300_opencore

[/] [ts7300_opencore/] [trunk/] [ethernet/] [eth_fifo.v] - Blame information for rev 5

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 joff
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_fifo.v                                                  ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001 Authors                                   ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44
// Revision 1.4  2005/02/21 12:48:07  igorm
45
// Warning fixes.
46
//
47
// Revision 1.3  2002/04/22 13:45:52  mohor
48
// Generic ram or Xilinx ram can be used in fifo (selectable by setting
49
// ETH_FIFO_XILINX in eth_defines.v).
50
//
51
// Revision 1.2  2002/03/25 13:33:04  mohor
52
// When clear and read/write are active at the same time, cnt and pointers are
53
// set to 1.
54
//
55
// Revision 1.1  2002/02/05 16:44:39  mohor
56
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
57
// MHz. Statuses, overrun, control frame transmission and reception still  need
58
// to be fixed.
59
//
60
//
61
 
62
`include "eth_defines.v"
63
`include "timescale.v"
64
 
65
module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty, cnt);
66
 
67
parameter DATA_WIDTH    = 32;
68
parameter DEPTH         = 8;
69
parameter CNT_WIDTH     = 4;
70
 
71
parameter Tp            = 1;
72
 
73
input                     clk;
74
input                     reset;
75
input                     write;
76
input                     read;
77
input                     clear;
78
input   [DATA_WIDTH-1:0]  data_in;
79
 
80
output  [DATA_WIDTH-1:0]  data_out;
81
output                    almost_full;
82
output                    full;
83
output                    almost_empty;
84
output                    empty;
85
output  [CNT_WIDTH-1:0]   cnt;
86
 
87
`ifdef ETH_FIFO_XILINX
88
`else
89
  `ifdef ETH_ALTERA_ALTSYNCRAM
90
  `else
91
    reg     [DATA_WIDTH-1:0]  fifo  [0:DEPTH-1];
92
    reg     [DATA_WIDTH-1:0]  data_out;
93
  `endif
94
`endif
95
 
96
reg     [CNT_WIDTH-1:0]   cnt;
97
reg     [CNT_WIDTH-2:0]   read_pointer;
98
reg     [CNT_WIDTH-2:0]   write_pointer;
99
 
100
 
101
always @ (posedge clk or posedge reset)
102
begin
103
  if(reset)
104
    cnt <=#Tp 0;
105
  else
106
  if(clear)
107
    cnt <=#Tp { {(CNT_WIDTH-1){1'b0}}, read^write};
108
  else
109
  if(read ^ write)
110
    if(read)
111
      cnt <=#Tp cnt - 1'b1;
112
    else
113
      cnt <=#Tp cnt + 1'b1;
114
end
115
 
116
always @ (posedge clk or posedge reset)
117
begin
118
  if(reset)
119
    read_pointer <=#Tp 0;
120
  else
121
  if(clear)
122
    read_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, read};
123
  else
124
  if(read & ~empty)
125
    read_pointer <=#Tp read_pointer + 1'b1;
126
end
127
 
128
always @ (posedge clk or posedge reset)
129
begin
130
  if(reset)
131
    write_pointer <=#Tp 0;
132
  else
133
  if(clear)
134
    write_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, write};
135
  else
136
  if(write & ~full)
137
    write_pointer <=#Tp write_pointer + 1'b1;
138
end
139
 
140
assign empty = ~(|cnt);
141
assign almost_empty = cnt == 1;
142
assign full  = cnt == DEPTH;
143
assign almost_full  = &cnt[CNT_WIDTH-2:0];
144
 
145
 
146
 
147
`ifdef ETH_FIFO_XILINX
148
  xilinx_dist_ram_16x32 fifo
149
  ( .data_out(data_out),
150
    .we(write & ~full),
151
    .data_in(data_in),
152
    .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer),
153
    .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
154
    .wclk(clk)
155
  );
156
`else   // !ETH_FIFO_XILINX
157
`ifdef ETH_ALTERA_ALTSYNCRAM
158
  altera_dpram_16x32    altera_dpram_16x32_inst
159
  (
160
        .data             (data_in),
161
        .wren             (write & ~full),
162
        .wraddress        (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
163
        .rdaddress        (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ),
164
        .clock            (clk),
165
        .q                (data_out)
166
  );  //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE
167
`else   // !ETH_ALTERA_ALTSYNCRAM
168
  always @ (posedge clk)
169
  begin
170
    if(write & clear)
171
      fifo[0] <=#Tp data_in;
172
    else
173
   if(write & ~full)
174
      fifo[write_pointer] <=#Tp data_in;
175
  end
176
 
177
 
178
  always @ (posedge clk)
179
  begin
180
    if(clear)
181
      data_out <=#Tp fifo[0];
182
    else
183
      data_out <=#Tp fifo[read_pointer];
184
  end
185
`endif  // !ETH_ALTERA_ALTSYNCRAM
186
`endif  // !ETH_FIFO_XILINX
187
 
188
 
189
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.