OpenCores
URL https://opencores.org/ocsvn/ts7300_opencore/ts7300_opencore/trunk

Subversion Repositories ts7300_opencore

[/] [ts7300_opencore/] [trunk/] [ethernet/] [eth_rxcounters.v] - Blame information for rev 5

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 joff
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_rxcounters.v                                            ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
11
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
12
////                                                              ////
13
////  All additional information is avaliable in the Readme.txt   ////
14
////  file.                                                       ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2001 Authors                                   ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
//
43
// CVS Revision History
44
//
45
// $Log: not supported by cvs2svn $
46
// Revision 1.6  2005/02/21 11:00:57  igorm
47
// Delayed CRC fixed.
48
//
49
// Revision 1.5  2002/02/15 11:13:29  mohor
50
// Format of the file changed a bit.
51
//
52
// Revision 1.4  2002/02/14 20:19:41  billditt
53
// Modified for Address Checking,
54
// addition of eth_addrcheck.v
55
//
56
// Revision 1.3  2002/01/23 10:28:16  mohor
57
// Link in the header changed.
58
//
59
// Revision 1.2  2001/10/19 08:43:51  mohor
60
// eth_timescale.v changed to timescale.v This is done because of the
61
// simulation of the few cores in a one joined project.
62
//
63
// Revision 1.1  2001/08/06 14:44:29  mohor
64
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
65
// Include files fixed to contain no path.
66
// File names and module names changed ta have a eth_ prologue in the name.
67
// File eth_timescale.v is used to define timescale
68
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
69
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
70
// and Mdo_OE. The bidirectional signal must be created on the top level. This
71
// is done due to the ASIC tools.
72
//
73
// Revision 1.1  2001/07/30 21:23:42  mohor
74
// Directory structure changed. Files checked and joind together.
75
//
76
// Revision 1.1  2001/06/27 21:26:19  mohor
77
// Initial release of the RxEthMAC module.
78
//
79
//
80
//
81
//
82
//
83
//
84
 
85
 
86
`include "timescale.v"
87
 
88
 
89
module eth_rxcounters (MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
90
                       MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
91
                       ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
92
                       ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
93
                      );
94
 
95
parameter Tp = 1;
96
 
97
input         MRxClk;
98
input         Reset;
99
input         MRxDV;
100
input         StateSFD;
101
input [1:0]   StateData;
102
input         MRxDEqD;
103
input         StateIdle;
104
input         StateDrop;
105
input         DlyCrcEn;
106
input         StatePreamble;
107
input         Transmitting;
108
input         HugEn;
109
input [15:0]  MaxFL;
110
input         r_IFG;
111
 
112
output        IFGCounterEq24;           // IFG counter reaches 9600 ns (960 ns)
113
output [3:0]  DlyCrcCnt;                // Delayed CRC counter
114
output        ByteCntEq0;               // Byte counter = 0
115
output        ByteCntEq1;               // Byte counter = 1
116
output        ByteCntEq2;               // Byte counter = 2  
117
output        ByteCntEq3;               // Byte counter = 3  
118
output        ByteCntEq4;               // Byte counter = 4  
119
output        ByteCntEq5;               // Byte counter = 5  
120
output        ByteCntEq6;               // Byte counter = 6
121
output        ByteCntEq7;               // Byte counter = 7
122
output        ByteCntGreat2;            // Byte counter > 2
123
output        ByteCntSmall7;            // Byte counter < 7
124
output        ByteCntMaxFrame;          // Byte counter = MaxFL
125
output [15:0] ByteCntOut;               // Byte counter
126
 
127
wire          ResetByteCounter;
128
wire          IncrementByteCounter;
129
wire          ResetIFGCounter;
130
wire          IncrementIFGCounter;
131
wire          ByteCntMax;
132
 
133
reg   [15:0]  ByteCnt;
134
reg   [3:0]   DlyCrcCnt;
135
reg   [4:0]   IFGCounter;
136
 
137
wire  [15:0]  ByteCntDelayed;
138
 
139
 
140
 
141
assign ResetByteCounter = MRxDV & (StateSFD & MRxDEqD | StateData[0] & ByteCntMaxFrame);
142
 
143
assign IncrementByteCounter = ~ResetByteCounter & MRxDV &
144
                              (StatePreamble | StateSFD | StateIdle & ~Transmitting |
145
                               StateData[1] & ~ByteCntMax & ~(DlyCrcEn & |DlyCrcCnt)
146
                              );
147
 
148
 
149
always @ (posedge MRxClk or posedge Reset)
150
begin
151
  if(Reset)
152
    ByteCnt[15:0] <= #Tp 16'h0;
153
  else
154
    begin
155
      if(ResetByteCounter)
156
        ByteCnt[15:0] <= #Tp 16'h0;
157
      else
158
      if(IncrementByteCounter)
159
        ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
160
     end
161
end
162
 
163
assign ByteCntDelayed = ByteCnt + 3'h4;
164
assign ByteCntOut = DlyCrcEn? ByteCntDelayed : ByteCnt;
165
 
166
assign ByteCntEq0       = ByteCnt == 16'h0;
167
assign ByteCntEq1       = ByteCnt == 16'h1;
168
assign ByteCntEq2       = ByteCnt == 16'h2;
169
assign ByteCntEq3       = ByteCnt == 16'h3;
170
assign ByteCntEq4       = ByteCnt == 16'h4;
171
assign ByteCntEq5       = ByteCnt == 16'h5;
172
assign ByteCntEq6       = ByteCnt == 16'h6;
173
assign ByteCntEq7       = ByteCnt == 16'h7;
174
assign ByteCntGreat2    = ByteCnt >  16'h2;
175
assign ByteCntSmall7    = ByteCnt <  16'h7;
176
assign ByteCntMax       = ByteCnt == 16'hffff;
177
assign ByteCntMaxFrame  = ByteCnt == MaxFL[15:0] & ~HugEn;
178
 
179
 
180
assign ResetIFGCounter = StateSFD  &  MRxDV & MRxDEqD | StateDrop;
181
 
182
assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24;
183
 
184
always @ (posedge MRxClk or posedge Reset)
185
begin
186
  if(Reset)
187
    IFGCounter[4:0] <= #Tp 5'h0;
188
  else
189
    begin
190
      if(ResetIFGCounter)
191
        IFGCounter[4:0] <= #Tp 5'h0;
192
      else
193
      if(IncrementIFGCounter)
194
        IFGCounter[4:0] <= #Tp IFGCounter[4:0] + 1'b1;
195
    end
196
end
197
 
198
 
199
 
200
assign IFGCounterEq24 = (IFGCounter[4:0] == 5'h18) | r_IFG; // 24*400 = 9600 ns or r_IFG is set to 1
201
 
202
 
203
always @ (posedge MRxClk or posedge Reset)
204
begin
205
  if(Reset)
206
    DlyCrcCnt[3:0] <= #Tp 4'h0;
207
  else
208
    begin
209
      if(DlyCrcCnt[3:0] == 4'h9)
210
        DlyCrcCnt[3:0] <= #Tp 4'h0;
211
      else
212
      if(DlyCrcEn & StateSFD)
213
        DlyCrcCnt[3:0] <= #Tp 4'h1;
214
      else
215
      if(DlyCrcEn & (|DlyCrcCnt[3:0]))
216
        DlyCrcCnt[3:0] <= #Tp DlyCrcCnt[3:0] + 1'b1;
217
    end
218
end
219
 
220
 
221
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.