OpenCores
URL https://opencores.org/ocsvn/ts7300_opencore/ts7300_opencore/trunk

Subversion Repositories ts7300_opencore

[/] [ts7300_opencore/] [trunk/] [ethernet/] [eth_shiftreg.v] - Blame information for rev 5

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 joff
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_shiftreg.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001 Authors                                   ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44
// Revision 1.6  2005/03/08 14:45:09  igorm
45
// Case statement improved for synthesys.
46
//
47
// Revision 1.5  2002/08/14 18:16:59  mohor
48
// LinkFail signal was not latching appropriate bit.
49
//
50
// Revision 1.4  2002/03/02 21:06:01  mohor
51
// LinkFail signal was not latching appropriate bit.
52
//
53
// Revision 1.3  2002/01/23 10:28:16  mohor
54
// Link in the header changed.
55
//
56
// Revision 1.2  2001/10/19 08:43:51  mohor
57
// eth_timescale.v changed to timescale.v This is done because of the
58
// simulation of the few cores in a one joined project.
59
//
60
// Revision 1.1  2001/08/06 14:44:29  mohor
61
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
62
// Include files fixed to contain no path.
63
// File names and module names changed ta have a eth_ prologue in the name.
64
// File eth_timescale.v is used to define timescale
65
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
66
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
67
// and Mdo_OE. The bidirectional signal must be created on the top level. This
68
// is done due to the ASIC tools.
69
//
70
// Revision 1.1  2001/07/30 21:23:42  mohor
71
// Directory structure changed. Files checked and joind together.
72
//
73
// Revision 1.3  2001/06/01 22:28:56  mohor
74
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
75
//
76
//
77
 
78
`include "timescale.v"
79
 
80
 
81
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
82
                    LatchByte, ShiftedBit, Prsd, LinkFail);
83
 
84
 
85
parameter Tp=1;
86
 
87
input       Clk;              // Input clock (Host clock)
88
input       Reset;            // Reset signal
89
input       MdcEn_n;          // Enable signal is asserted for one Clk period before Mdc falls.
90
input       Mdi;              // MII input data
91
input [4:0] Fiad;             // PHY address
92
input [4:0] Rgad;             // Register address (within the selected PHY)
93
input [15:0]CtrlData;         // Control data (data to be written to the PHY)
94
input       WriteOp;          // The current operation is a PHY register write operation
95
input [3:0] ByteSelect;       // Byte select
96
input [1:0] LatchByte;        // Byte select for latching (read operation)
97
 
98
output      ShiftedBit;       // Bit shifted out of the shift register
99
output[15:0]Prsd;             // Read Status Data (data read from the PHY)
100
output      LinkFail;         // Link Integrity Signal
101
 
102
reg   [7:0] ShiftReg;         // Shift register for shifting the data in and out
103
reg   [15:0]Prsd;
104
reg         LinkFail;
105
 
106
 
107
 
108
 
109
// ShiftReg[7:0] :: Shift Register Data
110
always @ (posedge Clk or posedge Reset)
111
begin
112
  if(Reset)
113
    begin
114
      ShiftReg[7:0] <= #Tp 8'h0;
115
      Prsd[15:0] <= #Tp 16'h0;
116
      LinkFail <= #Tp 1'b0;
117
    end
118
  else
119
    begin
120
      if(MdcEn_n)
121
        begin
122
          if(|ByteSelect)
123
            begin
124
              case (ByteSelect[3:0])  // synopsys parallel_case full_case
125
                4'h1 :    ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
126
                4'h2 :    ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10};
127
                4'h4 :    ShiftReg[7:0] <= #Tp CtrlData[15:8];
128
                4'h8 :    ShiftReg[7:0] <= #Tp CtrlData[7:0];
129
              endcase
130
            end
131
          else
132
            begin
133
              ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};
134
              if(LatchByte[0])
135
                begin
136
                  Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi};
137
                  if(Rgad == 5'h01)
138
                    LinkFail <= #Tp ~ShiftReg[1];  // this is bit [2], because it is not shifted yet
139
                end
140
              else
141
                begin
142
                  if(LatchByte[1])
143
                    Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi};
144
                end
145
            end
146
        end
147
    end
148
end
149
 
150
 
151
assign ShiftedBit = ShiftReg[7];
152
 
153
 
154
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.