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[/] [ts7300_opencore/] [trunk/] [ethernet/] [eth_spram_256x32.v] - Blame information for rev 6

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_spram_256x32.v                                          ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is available in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001, 2002 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10  2005/02/21 12:48:07  igorm
// Warning fixes.
//
// Revision 1.9  2003/12/05 12:43:06  tadejm
// Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.
//
// Revision 1.8  2003/12/04 14:59:13  simons
// Lapsus fixed (!we -> ~we).
//
// Revision 1.7  2003/11/12 18:24:59  tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
//
// Revision 1.6  2003/10/17 07:46:15  markom
// mbist signals updated according to newest convention
//
// Revision 1.5  2003/08/14 16:42:58  simons
// Artisan ram instance added.
//
// Revision 1.4  2002/10/18 17:04:20  tadejm
// Changed BIST scan signals.
//
// Revision 1.3  2002/10/10 16:29:30  mohor
// BIST added.
//
// Revision 1.2  2002/09/23 18:24:31  mohor
// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).
//
// Revision 1.1  2002/07/23 16:36:09  mohor
// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.
//
//
//
 
`include "eth_defines.v"
`include "timescale.v"
 
module eth_spram_256x32(
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
 
`ifdef ETH_BIST
  ,
  // debug chain signals
  mbist_si_i,       // bist scan serial in
  mbist_so_o,       // bist scan serial out
  mbist_ctrl_i        // bist chain shift control
`endif
 
 
 
);
 
        //
        // Generic synchronous single-port RAM interface
        //
        input           clk;  // Clock, rising edge
        input           rst;  // Reset, active high
        input           ce;   // Chip enable input, active high
        input  [3:0]    we;   // Write enable input, active high
        input           oe;   // Output enable input, active high
        input  [7:0]    addr; // address bus inputs
        input  [31:0]   di;   // input data bus
        output [31:0]   do;   // output data bus
 
 
`ifdef ETH_BIST
  input   mbist_si_i;       // bist scan serial in
  output  mbist_so_o;       // bist scan serial out
  input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
`endif
 
`ifdef ETH_XILINX_RAMB4
 
    /*RAMB4_S16 ram0
    (
        .DO      (do[15:0]),
        .ADDR    (addr),
        .DI      (di[15:0]),
        .EN      (ce),
        .CLK     (clk),
        .WE      (we),
        .RST     (rst)
    );
 
    RAMB4_S16 ram1
    (
        .DO      (do[31:16]),
        .ADDR    (addr),
        .DI      (di[31:16]),
        .EN      (ce),
        .CLK     (clk),
        .WE      (we),
        .RST     (rst)
    );*/
 
    RAMB4_S8 ram0
    (
        .DO      (do[7:0]),
        .ADDR    ({1'b0, addr}),
        .DI      (di[7:0]),
        .EN      (ce),
        .CLK     (clk),
        .WE      (we[0]),
        .RST     (rst)
    );
 
    RAMB4_S8 ram1
    (
        .DO      (do[15:8]),
        .ADDR    ({1'b0, addr}),
        .DI      (di[15:8]),
        .EN      (ce),
        .CLK     (clk),
        .WE      (we[1]),
        .RST     (rst)
    );
 
    RAMB4_S8 ram2
    (
        .DO      (do[23:16]),
        .ADDR    ({1'b0, addr}),
        .DI      (di[23:16]),
        .EN      (ce),
        .CLK     (clk),
        .WE      (we[2]),
        .RST     (rst)
    );
 
    RAMB4_S8 ram3
    (
        .DO      (do[31:24]),
        .ADDR    ({1'b0, addr}),
        .DI      (di[31:24]),
        .EN      (ce),
        .CLK     (clk),
        .WE      (we[3]),
        .RST     (rst)
    );
 
`else   // !ETH_XILINX_RAMB4
`ifdef  ETH_VIRTUAL_SILICON_RAM
  `ifdef ETH_BIST
      //vs_hdsp_256x32_bist ram0_bist
      vs_hdsp_256x32_bw_bist ram0_bist
  `else
      //vs_hdsp_256x32 ram0
      vs_hdsp_256x32_bw ram0
  `endif
      (
        .CK         (clk),
        .CEN        (!ce),
        .WEN        (~we),
        .OEN        (!oe),
        .ADR        (addr),
        .DI         (di),
        .DOUT       (do)
 
      `ifdef ETH_BIST
        ,
        // debug chain signals
        .mbist_si_i       (mbist_si_i),
        .mbist_so_o       (mbist_so_o),
        .mbist_ctrl_i       (mbist_ctrl_i)
      `endif
      );
 
`else   // !ETH_VIRTUAL_SILICON_RAM
 
`ifdef  ETH_ARTISAN_RAM
  `ifdef ETH_BIST
      //art_hssp_256x32_bist ram0_bist
      art_hssp_256x32_bw_bist ram0_bist
  `else
      //art_hssp_256x32 ram0
      art_hssp_256x32_bw ram0
  `endif
      (
        .CLK        (clk),
        .CEN        (!ce),
        .WEN        (~we),
        .OEN        (!oe),
        .A          (addr),
        .D          (di),
        .Q          (do)
 
      `ifdef ETH_BIST
        ,
        // debug chain signals
        .mbist_si_i       (mbist_si_i),
        .mbist_so_o       (mbist_so_o),
        .mbist_ctrl_i     (mbist_ctrl_i)
      `endif
      );
 
`else   // !ETH_ARTISAN_RAM
`ifdef ETH_ALTERA_ALTSYNCRAM
 
    altera_spram_256x32 altera_spram_256x32_inst
    (
          .address        (addr),
          .wren           (ce && (we != 4'd0)),
      .byteena_a      (we),
          .clock          (clk),
          .data           (di),
          .q              (do)
        );  //exemplar attribute altera_spram_256x32_inst NOOPT TRUE
 
`else   // !ETH_ALTERA_ALTSYNCRAM
 
 
        //
        // Generic single-port synchronous RAM model
        //
 
        //
        // Generic RAM's registers and wires
        //
        reg  [ 7: 0] mem0 [255:0]; // RAM content
        reg  [15: 8] mem1 [255:0]; // RAM content
        reg  [23:16] mem2 [255:0]; // RAM content
        reg  [31:24] mem3 [255:0]; // RAM content
        wire [31:0]  q;            // RAM output
        reg  [7:0]   raddr;        // RAM read address
        //
        // Data output drivers
        //
        assign do = (oe & ce) ? q : {32{1'bz}};
 
        //
        // RAM read and write
        //
 
        // read operation
        always@(posedge clk)
          if (ce) // && !we)
                raddr <= #1 addr;    // read address needs to be registered to read clock
 
        assign #1 q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]};
 
        // write operation
        always@(posedge clk)
        begin
                if (ce && we[3])
                        mem3[addr] <= #1 di[31:24];
                if (ce && we[2])
                        mem2[addr] <= #1 di[23:16];
                if (ce && we[1])
                        mem1[addr] <= #1 di[15: 8];
                if (ce && we[0])
                        mem0[addr] <= #1 di[ 7: 0];
        end
 
        // Task prints range of memory
        // *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations. 
        task print_ram;
        input [7:0] start;
        input [7:0] finish;
        integer rnum;
        begin
                for (rnum=start;rnum<=finish;rnum=rnum+1)
                        $display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
        end
        endtask
 
`endif  // !ETH_ALTERA_ALTSYNCRAM
`endif  // !ETH_ARTISAN_RAM
`endif  // !ETH_VIRTUAL_SILICON_RAM
`endif  // !ETH_XILINX_RAMB4
 
endmodule

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[/] [ts7300_opencore/] [trunk/] [ethernet/] [eth_spram_256x32.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	2	joff	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_spram_256x32.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects/ethmac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is available in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001, 2002 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44			`// Revision 1.10 2005/02/21 12:48:07 igorm`
45			`// Warning fixes.`
46			`//`
47			`// Revision 1.9 2003/12/05 12:43:06 tadejm`
48			`// Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.`
49			`//`
50			`// Revision 1.8 2003/12/04 14:59:13 simons`
51			`// Lapsus fixed (!we -> ~we).`
52			`//`
53			`// Revision 1.7 2003/11/12 18:24:59 tadejm`
54			`// WISHBONE slave changed and tested from only 32-bit accesss to byte access.`
55			`//`
56			`// Revision 1.6 2003/10/17 07:46:15 markom`
57			`// mbist signals updated according to newest convention`
58			`//`
59			`// Revision 1.5 2003/08/14 16:42:58 simons`
60			`// Artisan ram instance added.`
61			`//`
62			`// Revision 1.4 2002/10/18 17:04:20 tadejm`
63			`// Changed BIST scan signals.`
64			`//`
65			`// Revision 1.3 2002/10/10 16:29:30 mohor`
66			`// BIST added.`
67			`//`
68			`// Revision 1.2 2002/09/23 18:24:31 mohor`
69			`// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).`
70			`//`
71			`// Revision 1.1 2002/07/23 16:36:09 mohor`
72			`// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.`
73			`//`
74			`//`
75			`//`
76
77			`include "eth_defines.v"
78			`include "timescale.v"
79
80			`module eth_spram_256x32(`
81			`// Generic synchronous single-port RAM interface`
82			`clk, rst, ce, we, oe, addr, di, do`
83
84			`ifdef ETH_BIST
85			`,`
86			`// debug chain signals`
87			`mbist_si_i, // bist scan serial in`
88			`mbist_so_o, // bist scan serial out`
89			`mbist_ctrl_i // bist chain shift control`
90			`endif
91
92
93
94			`);`
95
96			`//`
97			`// Generic synchronous single-port RAM interface`
98			`//`
99			`input clk; // Clock, rising edge`
100			`input rst; // Reset, active high`
101			`input ce; // Chip enable input, active high`
102			`input [3:0] we; // Write enable input, active high`
103			`input oe; // Output enable input, active high`
104			`input [7:0] addr; // address bus inputs`
105			`input [31:0] di; // input data bus`
106			`output [31:0] do; // output data bus`
107
108
109			`ifdef ETH_BIST
110			`input mbist_si_i; // bist scan serial in`
111			`output mbist_so_o; // bist scan serial out`
112			input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
113			`endif
114
115			`ifdef ETH_XILINX_RAMB4
116
117			`/*RAMB4_S16 ram0`
118			`(`
119			`.DO (do[15:0]),`
120			`.ADDR (addr),`
121			`.DI (di[15:0]),`
122			`.EN (ce),`
123			`.CLK (clk),`
124			`.WE (we),`
125			`.RST (rst)`
126			`);`
127
128			`RAMB4_S16 ram1`
129			`(`
130			`.DO (do[31:16]),`
131			`.ADDR (addr),`
132			`.DI (di[31:16]),`
133			`.EN (ce),`
134			`.CLK (clk),`
135			`.WE (we),`
136			`.RST (rst)`
137			`);*/`
138
139			`RAMB4_S8 ram0`
140			`(`
141			`.DO (do[7:0]),`
142			`.ADDR ({1'b0, addr}),`
143			`.DI (di[7:0]),`
144			`.EN (ce),`
145			`.CLK (clk),`
146			`.WE (we[0]),`
147			`.RST (rst)`
148			`);`
149
150			`RAMB4_S8 ram1`
151			`(`
152			`.DO (do[15:8]),`
153			`.ADDR ({1'b0, addr}),`
154			`.DI (di[15:8]),`
155			`.EN (ce),`
156			`.CLK (clk),`
157			`.WE (we[1]),`
158			`.RST (rst)`
159			`);`
160
161			`RAMB4_S8 ram2`
162			`(`
163			`.DO (do[23:16]),`
164			`.ADDR ({1'b0, addr}),`
165			`.DI (di[23:16]),`
166			`.EN (ce),`
167			`.CLK (clk),`
168			`.WE (we[2]),`
169			`.RST (rst)`
170			`);`
171
172			`RAMB4_S8 ram3`
173			`(`
174			`.DO (do[31:24]),`
175			`.ADDR ({1'b0, addr}),`
176			`.DI (di[31:24]),`
177			`.EN (ce),`
178			`.CLK (clk),`
179			`.WE (we[3]),`
180			`.RST (rst)`
181			`);`
182
183			`else // !ETH_XILINX_RAMB4
184			`ifdef ETH_VIRTUAL_SILICON_RAM
185			`ifdef ETH_BIST
186			`//vs_hdsp_256x32_bist ram0_bist`
187			`vs_hdsp_256x32_bw_bist ram0_bist`
188			`else
189			`//vs_hdsp_256x32 ram0`
190			`vs_hdsp_256x32_bw ram0`
191			`endif
192			`(`
193			`.CK (clk),`
194			`.CEN (!ce),`
195			`.WEN (~we),`
196			`.OEN (!oe),`
197			`.ADR (addr),`
198			`.DI (di),`
199			`.DOUT (do)`
200
201			`ifdef ETH_BIST
202			`,`
203			`// debug chain signals`
204			`.mbist_si_i (mbist_si_i),`
205			`.mbist_so_o (mbist_so_o),`
206			`.mbist_ctrl_i (mbist_ctrl_i)`
207			`endif
208			`);`
209
210			`else // !ETH_VIRTUAL_SILICON_RAM
211
212			`ifdef ETH_ARTISAN_RAM
213			`ifdef ETH_BIST
214			`//art_hssp_256x32_bist ram0_bist`
215			`art_hssp_256x32_bw_bist ram0_bist`
216			`else
217			`//art_hssp_256x32 ram0`
218			`art_hssp_256x32_bw ram0`
219			`endif
220			`(`
221			`.CLK (clk),`
222			`.CEN (!ce),`
223			`.WEN (~we),`
224			`.OEN (!oe),`
225			`.A (addr),`
226			`.D (di),`
227			`.Q (do)`
228
229			`ifdef ETH_BIST
230			`,`
231			`// debug chain signals`
232			`.mbist_si_i (mbist_si_i),`
233			`.mbist_so_o (mbist_so_o),`
234			`.mbist_ctrl_i (mbist_ctrl_i)`
235			`endif
236			`);`
237
238			`else // !ETH_ARTISAN_RAM
239			`ifdef ETH_ALTERA_ALTSYNCRAM
240
241			`altera_spram_256x32 altera_spram_256x32_inst`
242			`(`
243			`.address (addr),`
244			`.wren (ce && (we != 4'd0)),`
245			`.byteena_a (we),`
246			`.clock (clk),`
247			`.data (di),`
248			`.q (do)`
249			`); //exemplar attribute altera_spram_256x32_inst NOOPT TRUE`
250
251			`else // !ETH_ALTERA_ALTSYNCRAM
252
253
254			`//`
255			`// Generic single-port synchronous RAM model`
256			`//`
257
258			`//`
259			`// Generic RAM's registers and wires`
260			`//`
261			`reg [ 7: 0] mem0 [255:0]; // RAM content`
262			`reg [15: 8] mem1 [255:0]; // RAM content`
263			`reg [23:16] mem2 [255:0]; // RAM content`
264			`reg [31:24] mem3 [255:0]; // RAM content`
265			`wire [31:0] q; // RAM output`
266			`reg [7:0] raddr; // RAM read address`
267			`//`
268			`// Data output drivers`
269			`//`
270			`assign do = (oe & ce) ? q : {32{1'bz}};`
271
272			`//`
273			`// RAM read and write`
274			`//`
275
276			`// read operation`
277			`always@(posedge clk)`
278			`if (ce) // && !we)`
279			`raddr <= #1 addr; // read address needs to be registered to read clock`
280
281			`assign #1 q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]};`
282
283			`// write operation`
284			`always@(posedge clk)`
285			`begin`
286			`if (ce && we[3])`
287			`mem3[addr] <= #1 di[31:24];`
288			`if (ce && we[2])`
289			`mem2[addr] <= #1 di[23:16];`
290			`if (ce && we[1])`
291			`mem1[addr] <= #1 di[15: 8];`
292			`if (ce && we[0])`
293			`mem0[addr] <= #1 di[ 7: 0];`
294			`end`
295
296			`// Task prints range of memory`
297			`// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.`
298			`task print_ram;`
299			`input [7:0] start;`
300			`input [7:0] finish;`
301			`integer rnum;`
302			`begin`
303			`for (rnum=start;rnum<=finish;rnum=rnum+1)`
304			`$display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);`
305			`end`
306			`endtask`
307
308			`endif // !ETH_ALTERA_ALTSYNCRAM
309			`endif // !ETH_ARTISAN_RAM
310			`endif // !ETH_VIRTUAL_SILICON_RAM
311			`endif // !ETH_XILINX_RAMB4
312
313			`endmodule`