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[/] [ts7300_opencore/] [trunk/] [wb32_blockram.v] - Blame information for rev 6

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1 2 joff 
/* Copyright 2005-2006, Technologic Systems
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 * All Rights Reserved.
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 *
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 * Author(s): Jesse Off <joff@embeddedARM.com>
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 */
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/*
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 *  This program is free software; you can redistribute it and/or modify
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 *  it under the terms of the GNU General Public License v2 as published by
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 *  the Free Software Foundation.
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 *
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 *  This program is distributed in the hope that it will be useful,
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 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
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 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 *  GNU General Public License for more details.
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 *  You should have received a copy of the GNU General Public License
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 *  along with this program; if not, write to the Free Software
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 *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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 */
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module wb32_blockram(
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  wb_clk_i,
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  wb_rst_i,
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  wb1_adr_i,
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  wb1_dat_i,
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  wb1_dat_o,
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  wb1_cyc_i,
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  wb1_stb_i,
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  wb1_ack_o,
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  wb1_we_i,
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  wb1_sel_i,
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  wb2_adr_i,
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  wb2_dat_i,
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  wb2_dat_o,
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  wb2_cyc_i,
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  wb2_stb_i,
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  wb2_ack_o,
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  wb2_we_i,
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  wb2_sel_i
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);
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input wb_clk_i, wb_rst_i;
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input [10:0] wb1_adr_i, wb2_adr_i;
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input [31:0] wb1_dat_i, wb2_dat_i;
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input wb1_cyc_i, wb2_cyc_i, wb1_stb_i, wb2_stb_i, wb1_we_i, wb2_we_i;
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input [3:0] wb1_sel_i, wb2_sel_i;
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output [31:0] wb1_dat_o, wb2_dat_o;
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output reg wb1_ack_o, wb2_ack_o;
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/* Set if wb1 and wb2 are opposite endianness */
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parameter endian_swap = 1'b0;
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reg [31:0] blockram_data_i;
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reg [10:0] blockram_rdadr_i, blockram_wradr_i;
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wire [31:0] blockram_data_o;
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reg [3:0] blockram_wren;
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altera_ram blockram0(
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  .clock(wb_clk_i),
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  .data(blockram_data_i[7:0]),
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  .rdaddress(blockram_rdadr_i),
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  .wraddress(blockram_wradr_i),
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  .wren(blockram_wren[0]),
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  .q(blockram_data_o[7:0])
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);
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altera_ram blockram1(
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  .clock(wb_clk_i),
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  .data(blockram_data_i[15:8]),
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  .rdaddress(blockram_rdadr_i),
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  .wraddress(blockram_wradr_i),
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  .wren(blockram_wren[1]),
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  .q(blockram_data_o[15:8])
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);
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altera_ram blockram2(
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  .clock(wb_clk_i),
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  .data(blockram_data_i[23:16]),
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  .rdaddress(blockram_rdadr_i),
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  .wraddress(blockram_wradr_i),
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  .wren(blockram_wren[2]),
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  .q(blockram_data_o[23:16])
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);
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altera_ram blockram3(
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  .clock(wb_clk_i),
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  .data(blockram_data_i[31:24]),
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  .rdaddress(blockram_rdadr_i),
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  .wraddress(blockram_wradr_i),
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  .wren(blockram_wren[3]),
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  .q(blockram_data_o[31:24])
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);
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reg rdowner = 1'b0;
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reg wrowner = 1'b0;
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reg wb1_rdreq, wb2_rdreq, wb1_wrreq, wb2_wrreq;
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always @(rdowner or wrowner or wb1_adr_i or wb2_adr_i or wb1_dat_i or
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  wb2_dat_i or wb1_sel_i or wb2_sel_i or rdowner or wrowner or
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  wb2_wrreq or wb1_wrreq or endian_swap) begin
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  if (rdowner) blockram_rdadr_i = wb2_adr_i;
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  else blockram_rdadr_i = wb1_adr_i;
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  blockram_wren = 4'b0000;
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  if (wrowner) begin
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    blockram_wradr_i = wb2_adr_i;
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    if (endian_swap) begin
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      blockram_data_i = {wb2_dat_i[7:0], wb2_dat_i[15:8], wb2_dat_i[23:16],
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                         wb2_dat_i[31:24]};
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      if (wb2_wrreq) blockram_wren = {wb2_sel_i[0], wb2_sel_i[1], wb2_sel_i[2],
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                                      wb2_sel_i[3]};
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    end else begin
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      blockram_data_i = wb2_dat_i;
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      if (wb2_wrreq) blockram_wren = wb2_sel_i;
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    end
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  end else begin
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    blockram_wradr_i = wb1_adr_i;
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    blockram_data_i = wb1_dat_i;
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    if (wb1_wrreq) blockram_wren = wb1_sel_i;
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  end
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end
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assign wb1_dat_o = blockram_data_o;
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assign wb2_dat_o = endian_swap ? {blockram_data_o[7:0],
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  blockram_data_o[15:8], blockram_data_o[23:16], blockram_data_o[31:24]} :
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  blockram_data_o;
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always @(wb1_cyc_i or wb1_stb_i or wb1_we_i or wb_rst_i or
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  wb2_cyc_i or wb2_stb_i or wb2_we_i or rdowner or wrowner or
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  wb1_ack_o or wb2_ack_o) begin
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  wb1_rdreq = wb1_cyc_i && wb1_stb_i && !wb1_we_i && !wb1_ack_o;
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  wb2_rdreq = wb2_cyc_i && wb2_stb_i && !wb2_we_i && !wb2_ack_o;
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  wb1_wrreq = wb1_cyc_i && wb1_stb_i && wb1_we_i && !wb1_ack_o;
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  wb2_wrreq = wb2_cyc_i && wb2_stb_i && wb2_we_i && !wb2_ack_o;
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  if (rdowner) begin
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    if (wb1_rdreq && !wb2_rdreq) rdowner = 1'b0;
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    else rdowner = 1'b1;
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  end else begin
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    if (!wb1_rdreq && wb2_rdreq) rdowner = 1'b1;
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    else rdowner = 1'b0;
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  end
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  if (wrowner) begin
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    if (wb1_wrreq && !wb2_wrreq) wrowner = 1'b0;
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    else wrowner = 1'b1;
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  end else begin
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    if (!wb1_wrreq && wb2_wrreq) wrowner = 1'b1;
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    else wrowner = 1'b0;
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  end
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  if (wb_rst_i) begin
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    rdowner = 1'b0;
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    wrowner = 1'b0;
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  end
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end
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always @(posedge wb_clk_i) begin
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  wb1_ack_o <= 1'b0;
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  wb2_ack_o <= 1'b0;
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  if (wb1_rdreq && !rdowner && !wb1_ack_o) begin
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    wb1_ack_o <= 1'b1;
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  end else if (wb2_rdreq && rdowner && !wb2_ack_o) begin
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    wb2_ack_o <= 1'b1;
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  end
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  if (wb1_wrreq && !wrowner && !wb1_ack_o) begin
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    wb1_ack_o <= 1'b1;
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  end else if (wb2_wrreq && wrowner && !wb2_ack_o) begin
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    wb2_ack_o <= 1'b1;
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  end
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end
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endmodule

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