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1 5 david237
-----------------------------------------------------------------------
2
-- Static RAM models (VHDL)                                          --
3
-- David R Brooks                                                    --
4
-- December, 2016.  Perth, Australia                                 --
5
-- Compliance: VHDL 2008                                             --
6
-- NB Simulation only: they are NOT synthesizable.                   --
7
-- Based on: Manufacturers data sheets                               --
8
-- Pinouts & naming agree with Altium libraries & VHDL netlister.    --
9
-- See StaticRAM.vhd                                                 --
10
-----------------------------------------------------------------------
11
 
12
-- NB The Hamburg SRAM component has been altered, splitting the bidirectional
13
-- data bus into separate IN & OUT parts. This is needed so that the bidirectional
14
-- data bus can be exported from these wrapper components.
15
 
16
-----------------------------------------------------------------------
17
-- HM6116: 2K x 8 CMOS static RAM (70 ns)
18
--         Verified 28/12/2016
19
-----------------------------------------------------------------------
20
library ieee;
21
    use ieee.std_logic_1164.all;
22
 
23
    use work.LSTTL.all;
24
    use work.TTLPrivate.all;
25
    use work.Memories.all;
26
 
27
entity HM6116 is
28
generic(
29
    fname : String := "";           -- Name of initialisation file (if any)
30
    --               min    max
31
    tRC   : time   := 70        ns; -- Read cycle (not used)
32
    tAA   : time   :=        70 ns; -- Address access
33
    tACS  : time   :=        70 ns; -- Chip select access
34
    tAOE  : time   :=        30 ns; -- OE\ to output valid
35
    tCLZ  : time   :=  5        ns; -- CS\ to output valid
36
    tOLZ  : time   :=  5        ns; -- OE\ to output valid
37
    tCHZ  : time   :=        20 ns; -- CS  to output Hi-Z
38
    tOHZR : time   :=        20 ns; -- OE  to output Hi-Z
39
    tOH   : time   :=  3        ns; -- OP hold from addr change
40
 
41
    tWC   : time   := 70        ns; -- Write cycle
42
    tCW   : time   := 70        ns; -- CS to end of write
43
    tAW   : time   := 70        ns; -- Address valid to end of write
44
    tAS   : time   :=  0        ns; -- Address setup time
45
    tDS   : time   :=  0        ns; -- Data setup time
46
    tWP   : time   := 50        ns; -- Write pulse width
47
    tWR   : time   :=  0        ns; -- Write recovery time
48
    tDW   : time   := 30        ns; -- Data valid to end of write
49
    tDH   : time   :=  0        ns; -- Data hold from end of write
50
    tWHZ  : time   :=        25 ns; -- Write to OP Hi-Z
51
    tWLZ  : time   :=  5        ns; -- Write to OP Lo-Z     (not used)
52
    tOHZW : time   :=        30 ns; -- OE to OP Hi-Z
53
    tOW   : time   :=  5        ns  -- OP active from end of write
54
);
55
port(
56
    X_1   : in    std_logic;        -- A7
57
    X_2   : in    std_logic;        -- A6
58
    X_3   : in    std_logic;        -- A5
59
    X_4   : in    std_logic;        -- A4
60
    X_5   : in    std_logic;        -- A3
61
    X_6   : in    std_logic;        -- A2
62
    X_7   : in    std_logic;        -- A1
63
    X_8   : in    std_logic;        -- A0
64
    X_9   : inout std_logic;        -- IO0
65
    X_10  : inout std_logic;        -- IO1
66
    X_11  : inout std_logic;        -- IO2
67
    X_12  : inout std_logic;        -- GND
68
    X_13  : inout std_logic;        -- IO3
69
    X_14  : inout std_logic;        -- IO4 
70
    X_15  : inout std_logic;        -- IO5
71
    X_16  : inout std_logic;        -- IO6
72
    X_17  : inout std_logic;        -- IO7
73
    X_18  : in    std_logic;        -- CS\
74
    X_19  : in    std_logic;        -- A10
75
    X_20  : in    std_logic;        -- OE\
76
    X_21  : in    std_logic;        -- WE\
77
    X_22  : in    std_logic;        -- A9
78
    X_23  : in    std_logic;        -- A8
79
    X_24  : inout std_logic         -- Vcc
80
);
81
end entity HM6116;
82
 
83
architecture BEHAV of HM6116 is
84
    signal D, Q : std_logic_vector( 7 downto 0);
85
    signal A    : std_logic_vector(10 downto 0);
86
 
87
    alias nCE is X_18;
88
    alias nOE is X_20;
89
    alias nWE is X_21;
90
 
91
    constant finit : boolean := fname /= "";    -- Initialise at power-up, if file defined
92
 
93
begin
94
    D <= (X_17, X_16, X_15, X_14, X_13, X_11, X_10, X_9);
95
    (X_17, X_16, X_15, X_14, X_13, X_11, X_10, X_9) <= Q;
96
    A <= (X_19, X_22, X_23, X_1, X_2, X_3, X_4, X_5, X_6, X_7, X_8);
97
 
98
    MB: sram
99
    generic map(
100
        value_on_power_up       => 'U',     -- Memory array is filled with this at start
101
        download_on_power_up    => finit,   -- if TRUE, RAM is downloaded at start of simulation 
102
        trace_ram_load          => FALSE,   -- Echoes the data downloaded to the RAM on the screen
103
        enable_nWE_only_control => FALSE,   -- Read-/write access controlled by nWE only
104
 
105
        -- READ-cycle timing parameters
106
        tAA_max                 => tAA,     -- Address Access Time
107
        tOHA_min                => tOH,     -- Output Hold Time
108
        tACE_max                => tACS,    -- nCE/CE2 Access Time
109
        tDOE_max                => tAOE,    -- nOE Access Time
110
        tLZOE_min               => tOLZ,    -- nOE to Low-Z Output
111
        tHZOE_max               => tOHZW,   --  OE to High-Z Output
112
        tLZCE_min               => tCLZ,    -- nCE/CE2 to Low-Z Output
113
        tHZCE_max               => tCHZ,    --  CE/nCE2 to High Z Output
114
 
115
        -- WRITE-cycle timing parameters
116
        tWC_min                 => tWC,     -- Write Cycle Time
117
        tSCE_min                => tCW,     -- nCE/CE2 to Write End
118
        tAW_min                 => tAW,     -- tAW Address Set-up Time to Write End
119
        tHA_min                 => tWR,     -- tHA Address Hold from Write End
120
        tSA_min                 => tAS,     -- Address Set-up Time
121
        tPWE_min                => tWP,     -- nWE Pulse Width
122
        tSD_min                 => tDW,     -- Data Set-up to Write End
123
        tHD_min                 => tDH,     -- Data Hold from Write End
124
        tHZWE_max               => tWHZ,    -- nWE Low to High-Z Output
125
        tLZWE_min               => tOW      -- nWE High to Low-Z Output
126
    )
127
    port map(
128
        nCE                     => nCE,     -- low-active Chip-Enable of the SRAM device; defaults to '1' (inactive)
129
        nOE                     => nOE,     -- low-active Output-Enable of the SRAM device; defaults to '1' (inactive)
130
        nWE                     => nWE,     -- low-active Write-Enable of the SRAM device; defaults to '1' (inactive)
131
        A                       => A,       -- address bus of the SRAM device
132
        D                       => D,       -- data bus to the SRAM device
133
        Q                       => Q,       -- data bus from the SRAM device
134
        CE2                     => '1',     -- high-active Chip-Enable of the SRAM device; defaults to '1'  (active) 
135
        download                => FALSE,   -- A FALSE-to-TRUE transition on this signal downloads the data
136
        download_filename       => fname,   -- name of the download source file
137
        dump                    => FALSE,   -- A FALSE-to-TRUE transition on this signal dumps data
138
        dump_start              => 0,       -- Written to the dump-file are the memory words from memory address 
139
        dump_end                => 0,       -- dump_start to address dump_end (default: all addresses)
140
        dump_filename           => ""       -- name of the dump destination file
141
    );
142
end architecture BEHAV;
143
 
144
-----------------------------------------------------------------------
145
-- IS61C1024: 128K x 8 CMOS static RAM (ISSI) (20 ns)
146
--            Verified 28/12/2016
147
-----------------------------------------------------------------------
148
library ieee;
149
    use ieee.std_logic_1164.all;
150
 
151
    use work.LSTTL.all;
152
    use work.TTLPrivate.all;
153
    use work.Memories.all;
154
 
155
entity IS61C1024 is
156
generic(
157
    fname  : String := "";               -- Name of initialisation file (if any)
158
    -- Read Cycle     Min.  Max. Unit    Parameter                       
159
    tRC    : time :=  20         ns;     -- Read Cycle Time                
160
    tAA    : time :=        20   ns;     -- Address Access Time            
161
    tOHA   : time :=   3         ns;     -- Output Hold Time               
162
    tACE1  : time :=        20   ns;     -- CE1 Access Time                
163
    tACE2  : time :=        20   ns;     -- CE2 Access Time                
164
    tDOE   : time :=         9   ns;     -- Access Time                    
165
    tLZOE  : time :=   0         ns;     -- OE to Low-Z Output             
166
    tHZOE  : time :=         7   ns;     -- OE to High-Z Output            
167
    tLZCE1 : time :=   3         ns;     -- CE1 to Low-Z Output            
168
    tLZCE2 : time :=   3         ns;     -- CE2 to Low-Z Output            
169
    tHZCE  : time :=         9   ns;     -- CE1 or CE2 to High-Z Output    
170
    tPU    : time :=   0         ns;     -- CE1 or CE2 to Power-Up         
171
    tPD    : time :=        18   ns;     -- CE1 or CE2 to Power-Down       
172
 
173
    -- Write Cycle    Min.  Max. Unit    Parameter                       
174
    tWC    : time :=  20         ns;     -- Write Cycle Time               
175
    tSCE1  : time :=  15         ns;     -- CE1 to Write End               
176
    tSCE2  : time :=  15         ns;     -- CE2 to Write End               
177
    tAW    : time :=  15         ns;     -- Address Setup Time to Write End
178
    tHA    : time :=   0         ns;     -- Address Hold from Write End    
179
    tSA    : time :=   0         ns;     -- Address Setup Time             
180
    tPWE   : time :=  12         ns;     -- WE Pulse Width                 
181
    tSD    : time :=  10         ns;     -- Data Setup to Write End        
182
    tHD    : time :=   0         ns;     -- Data Hold from Write End       
183
    tHZWE  : time :=        10   ns;     -- WE LOW to High-Z Output        
184
    tLZWE  : time :=   2         ns      -- WE HIGH to Low-Z Output        
185
);
186
port(
187
--  X_1
188
    X_2  : in    std_logic;  -- A16
189
    X_3  : in    std_logic;  -- A14
190
    X_4  : in    std_logic;  -- A12
191
    X_5  : in    std_logic;  -- A7
192
    X_6  : in    std_logic;  -- A6
193
    X_7  : in    std_logic;  -- A5
194
    X_8  : in    std_logic;  -- A4
195
    X_9  : in    std_logic;  -- A3
196
    X_10 : in    std_logic;  -- A2
197
    X_11 : in    std_logic;  -- A1
198
    X_12 : in    std_logic;  -- A0
199
    X_13 : inout std_logic;  -- IO0
200
    X_14 : inout std_logic;  -- IO1 
201
    X_15 : inout std_logic;  -- IO2
202
    X_16 : inout std_logic;  -- GND
203
    X_17 : inout std_logic;  -- IO3
204
    X_18 : inout std_logic;  -- IO4
205
    X_19 : inout std_logic;  -- IO5
206
    X_20 : inout std_logic;  -- IO6
207
    X_21 : inout std_logic;  -- IO7
208
    X_22 : in    std_logic;  -- CE1\
209
    X_23 : in    std_logic;  -- A10
210
    X_24 : in    std_logic;  -- OE\
211
    X_25 : in    std_logic;  -- A11
212
    X_26 : in    std_logic;  -- A9
213
    X_27 : in    std_logic;  -- A8
214
    X_28 : in    std_logic;  -- A13
215
    X_29 : in    std_logic;  -- WE\
216
    X_30 : in    std_logic;  -- CE2
217
    X_31 : in    std_logic;  -- A15
218
    X_32 : inout std_logic   -- Vcc
219
);
220
end entity IS61C1024;
221
 
222
architecture BEHAV of IS61C1024 is
223
    signal D, Q : std_logic_vector( 7 downto 0);
224
    signal A    : std_logic_vector(16 downto 0);
225
 
226
    alias nCE1 is X_22;
227
    alias CE2  is X_30;
228
    alias nOE  is X_24;
229
    alias nWE  is X_29;
230
 
231
    constant finit : boolean := fname /= "";    -- Initialise at power-up, if file defined
232
 
233
begin
234
         (X_21, X_20, X_19, X_18, X_17, X_15, X_14, X_13) <= Q;  -- Bidirectional bus
235
    D <= (X_21, X_20, X_19, X_18, X_17, X_15, X_14, X_13);
236
    A <= (X_2, X_31, X_3, X_28, X_4, X_25, X_23, X_26, X_27, X_5, X_6, X_7, X_8, X_9, X_10, X_11, X_12);
237
 
238
    MB: sram
239
    generic map(
240
        value_on_power_up       => 'U',     -- Memory array is filled with this at start
241
        download_on_power_up    => finit,   -- if TRUE, RAM is downloaded at start of simulation 
242
        trace_ram_load          => FALSE,   -- Echoes the data downloaded to the RAM on the screen
243
        enable_nWE_only_control => FALSE,   -- Read-/write access controlled by nWE only
244
 
245
        -- READ-cycle timing parameters
246
        tAA_max                 => tAA,     -- Address Access Time
247
        tOHA_min                => tOHA,    -- Output Hold Time
248
        tACE_max                => tACE1,   -- nCE/CE2 Access Time
249
        tDOE_max                => tDOE,    -- nOE Access Time
250
        tLZOE_min               => tLZOE,   -- nOE to Low-Z Output
251
        tHZOE_max               => tHZOE,   --  OE to High-Z Output
252
        tLZCE_min               => tLZCE1,  -- nCE/CE2 to Low-Z Output
253
        tHZCE_max               => tHZCE,   --  CE/nCE2 to High Z Output
254
 
255
        -- WRITE-cycle timing parameters
256
        tWC_min                 => tWC,     -- Write Cycle Time
257
        tSCE_min                => tSCE1,   -- nCE/CE2 to Write End
258
        tAW_min                 => tAW,     -- tAW Address Set-up Time to Write End
259
        tHA_min                 => tHA,     -- tHA Address Hold from Write End
260
        tSA_min                 => tSA,     -- Address Set-up Time
261
        tPWE_min                => tPWE,    -- nWE Pulse Width
262
        tSD_min                 => tSD,     -- Data Set-up to Write End
263
        tHD_min                 => tHD,     -- Data Hold from Write End
264
        tHZWE_max               => tHZWE,   -- nWE Low to High-Z Output
265
        tLZWE_min               => tLZWE    -- nWE High to Low-Z Output
266
    )
267
    port map(
268
        nCE                     => nCE1,    -- low-active Chip-Enable of the SRAM device; defaults to '1' (inactive)
269
        nOE                     => nOE,     -- low-active Output-Enable of the SRAM device; defaults to '1' (inactive)
270
        nWE                     => nWE,     -- low-active Write-Enable of the SRAM device; defaults to '1' (inactive)
271
        A                       => A,       -- address bus of the SRAM device
272
        D                       => D,       -- data bus to the SRAM device
273
        Q                       => Q,       -- data bus from the SRAM device
274
        CE2                     => CE2,     -- high-active Chip-Enable of the SRAM device; defaults to '1'  (active) 
275
        download                => FALSE,   -- A FALSE-to-TRUE transition on this signal downloads the data
276
        download_filename       => fname,   -- name of the download source file
277
        dump                    => FALSE,   -- A FALSE-to-TRUE transition on this signal dumps data
278
        dump_start              => 0,       -- Written to the dump-file are the memory words from memory address 
279
        dump_end                => 0,       -- dump_start to address dump_end (default: all addresses)
280
        dump_filename           => ""       -- name of the dump destination file
281
    );
282
end architecture BEHAV;
283
 
284
-----------------------------------------------------------------------
285
-- MB84256A-10LL : 32K x 8 CMOS static RAM (Fujitsu)
286
--            Verified 28/12/2016
287
-----------------------------------------------------------------------
288
library ieee;
289
    use ieee.std_logic_1164.all;
290
 
291
    use work.LSTTL.all;
292
    use work.TTLPrivate.all;
293
    use work.Memories.all;
294
 
295
entity MB84256 is
296
generic(
297
    fname   : String := "";             -- Name of initialisation file (if any)
298
    -- Read Cycle     Min   Max
299
    tRC     : time := 100       ns;     -- Read cycle time
300
    tAA     : time :=       100 ns;     -- Address access time
301
    tACS    : time :=       100 ns;     -- nCS1 access time
302
    tOE     : time :=        40 ns;     -- Output enable to output valid
303
    tOH     : time :=  20       ns;     -- Output hold from address change
304
    tCLZ    : time :=  10       ns;     -- Chip select to output Lo-Z
305
    tOLZ    : time :=   5       ns;     -- Output enable to output Lo-Z
306
    tCHZ    : time :=        40 ns;     -- Chip select to output Hi-Z
307
    tOHZ    : time :=        40 ns;     -- Output enable to output Hi-Z
308
    -- Write Cycle    Min   Max
309
    tWC     : time := 100       ns;     -- Write cycle time
310
    tAW     : time :=  80       ns;     -- Address valid to end of write
311
    tCW     : time :=  80       ns;     -- Chip select to end of write
312
    tDW     : time :=  40       ns;     -- Data valid to end of write
313
    tDH     : time :=   0       ns;     -- Data hold time
314
    tWP     : time :=  60       ns;     -- Write pulse width
315
    tAS     : time :=   0       ns;     -- Address setup time
316
    tWR     : time :=   5       ns;     -- Write recovery time
317
    tWLZ    : time :=   5       ns;     -- nWE to output Lo-Z
318
    tWHZ    : time :=        40 ns      -- nWE to output Hi-Z
319
);
320
port(
321
    X_1  : in    std_logic;  -- A14
322
    X_2  : in    std_logic;  -- A12
323
    X_3  : in    std_logic;  -- A7
324
    X_4  : in    std_logic;  -- A6
325
    X_5  : in    std_logic;  -- A5
326
    X_6  : in    std_logic;  -- A4
327
    X_7  : in    std_logic;  -- A3
328
    X_8  : in    std_logic;  -- A2
329
    X_9  : in    std_logic;  -- A1
330
    X_10 : in    std_logic;  -- A0
331
    X_11 : inout std_logic;  -- IO0
332
    X_12 : inout std_logic;  -- IO1
333
    X_13 : inout std_logic;  -- IO2
334
    X_14 : inout std_logic;  -- GND
335
    X_15 : inout std_logic;  -- IO3
336
    X_16 : inout std_logic;  -- IO4 
337
    X_17 : inout std_logic;  -- IO5
338
    X_18 : inout std_logic;  -- IO6
339
    X_19 : inout std_logic;  -- IO7
340
    X_20 : in    std_logic;  -- CS\
341
    X_21 : in    std_logic;  -- A10
342
    X_22 : in    std_logic;  -- OE\
343
    X_23 : in    std_logic;  -- A11
344
    X_24 : in    std_logic;  -- A9
345
    X_25 : in    std_logic;  -- A8
346
    X_26 : in    std_logic;  -- A13
347
    X_27 : in    std_logic;  -- WE\
348
    X_28 : inout std_logic   -- Vcc
349
);
350
end entity MB84256;
351
 
352
architecture BEHAV of MB84256 is
353
    signal D, Q : std_logic_vector( 7 downto 0);
354
    signal A    : std_logic_vector(14 downto 0);
355
 
356
    alias nCS is X_20;
357
    alias nOE is X_22;
358
    alias nWE is X_27;
359
 
360
    constant finit : boolean := fname /= "";    -- Initialise at power-up, if file defined
361
 
362
begin
363
          (X_19, X_18, X_17, X_16, X_15, X_13, X_12, X_11) <= Q;   -- Bidirectional bus
364
    D  <= (X_19, X_18, X_17, X_16, X_15, X_13, X_12, X_11);
365
    A  <= (X_1, X_26, X_2, X_23, X_21, X_24, X_25, X_3, X_4, X_5, X_6, X_7, X_8, X_9, X_10);
366
 
367
    MB: sram
368
    generic map(
369
        value_on_power_up       => 'U',     -- Memory array is filled with this at start
370
        download_on_power_up    => finit,   -- if TRUE, RAM is downloaded at start of simulation 
371
        trace_ram_load          => FALSE,   -- Echoes the data downloaded to the RAM on the screen
372
        enable_nWE_only_control => FALSE,   -- Read-/write access controlled by nWE only
373
 
374
        -- READ-cycle timing parameters
375
        tAA_max                 => tAA,     -- Address Access Time
376
        tOHA_min                => tOH,     -- Output Hold Time
377
        tACE_max                => tACS,    -- nCE/CE2 Access Time
378
        tDOE_max                => tOE,     -- nOE Access Time
379
        tLZOE_min               => tOLZ,    -- nOE to Low-Z Output
380
        tHZOE_max               => tOHZ,    --  OE to High-Z Output
381
        tLZCE_min               => tCLZ,    -- nCE/CE2 to Low-Z Output
382
        tHZCE_max               => tCHZ,    --  CE/nCE2 to High Z Output
383
 
384
        -- WRITE-cycle timing parameters
385
        tWC_min                 => tWC,     -- Write Cycle Time
386
        tSCE_min                => tCW,     -- nCE/CE2 to Write End
387
        tAW_min                 => tAW,     -- tAW Address Set-up Time to Write End
388
        tHA_min                 => tWR,     -- tHA Address Hold from Write End
389
        tSA_min                 => tAS,     -- Address Set-up Time
390
        tPWE_min                => tWP,     -- nWE Pulse Width
391
        tSD_min                 => tDW,     -- Data Set-up to Write End
392
        tHD_min                 => tDH,     -- Data Hold from Write End
393
        tHZWE_max               => tWHZ,    -- nWE Low to High-Z Output
394
        tLZWE_min               => tWLZ     -- nWE High to Low-Z Output
395
    )
396
    port map(
397
        nCE                     => nCS,     -- low-active Chip-Enable of the SRAM device; defaults to '1' (inactive)
398
        nOE                     => nOE,     -- low-active Output-Enable of the SRAM device; defaults to '1' (inactive)
399
        nWE                     => nWE,     -- low-active Write-Enable of the SRAM device; defaults to '1' (inactive)
400
        A                       => A,       -- address bus of the SRAM device
401
        D                       => D,       -- data bus to the SRAM device
402
        Q                       => Q,       -- data bus from the SRAM device
403
        CE2                     => '1',     -- high-active Chip-Enable of the SRAM device; defaults to '1'  (active) 
404
        download                => FALSE,   -- A FALSE-to-TRUE transition on this signal downloads the data
405
        download_filename       => fname,   -- name of the download source file
406
        dump                    => FALSE,   -- A FALSE-to-TRUE transition on this signal dumps data
407
        dump_start              => 0,       -- Written to the dump-file are the memory words from memory address 
408
        dump_end                => 0,       -- dump_start to address dump_end (default: all addresses)
409
        dump_filename           => ""       -- name of the dump destination file
410
    );
411
end architecture BEHAV;
412
 
413
-----------------------------------------------------------------------
414
-- CY7C1021-V33: 64K x 16 CMOS static RAM (Cypress)
415
-----------------------------------------------------------------------
416
library ieee;
417
    use ieee.std_logic_1164.all;
418
 
419
    use work.LSTTL.all;
420
    use work.TTLPrivate.all;
421
    use work.Memories.all;
422
 
423
entity CY7C1021 is
424
generic(
425
    fnevn : String := "";           -- Name of even-byte initialisation file (if any)
426
    fnodd : String := "";           -- Name of odd-byte  initialisation file (if any)
427
    -- READ CYCLE     Min  Max
428
    tRC    : time :=   10      ns;  -- Read Cycle Time              
429
    tAA    : time :=        10 ns;  -- Address to Data Valid        
430
    tOHA   : time :=    3      ns;  -- Data Hold from Address Change
431
    tACE   : time :=        10 ns;  -- CE LOW to Data Valid         
432
    tDOE   : time :=         5 ns;  -- OE LOW to Data Valid         
433
    tLZOE  : time :=    0      ns;  -- OE LOW to Low Z              
434
    tHZOE  : time :=         5 ns;  -- OE HIGH to High Z            
435
    tLZCE  : time :=    3      ns;  -- CE LOW to Low Z              
436
    tHZCE  : time :=         5 ns;  -- CE HIGH to High Z            
437
    tPU    : time :=    0      ns;  -- CE LOW to Power-Up           
438
    tPD    : time :=        10 ns;  -- CE HIGH to Power-Down        
439
    tDBE   : time :=         5 ns;  -- Byte Enable to Data Valid    
440
    tLZBE  : time :=    0      ns;  -- Byte Enable to Low Z         
441
    tHZBE  : time :=         5 ns;  -- Byte Disable to High Z       
442
    -- WRITE CYCLE 
443
    tWC    : time :=   10      ns;  -- Write Cycle Time             
444
    tSCE   : time :=    8      ns;  -- CE LOW to Write End          
445
    tAW    : time :=    7      ns;  -- Address Set-Up to Write End  
446
    tHA    : time :=    0      ns;  -- Address Hold from Write End  
447
    tSA    : time :=    0      ns;  -- Address Set-Up to Write Start
448
    tPWE   : time :=    7      ns;  -- WE Pulse Width               
449
    tSD    : time :=    5      ns;  -- Data Set-Up to Write End     
450
    tHD    : time :=    0      ns;  -- Data Hold from Write End     
451
    tLZWE  : time :=    3      ns;  -- WE HIGH to Low Z             
452
    tHZWE  : time :=         5 ns;  -- WE LOW to High Z             
453
    tBW    : time :=    7      ns   -- Byte Enable to End of Write  
454
);
455
port(
456
    X_1    : in    std_logic;       -- A4
457
    X_2    : in    std_logic;       -- A3
458
    X_3    : in    std_logic;       -- A2
459
    X_4    : in    std_logic;       -- A1
460
    X_5    : in    std_logic;       -- A0
461
    X_6    : in    std_logic;       -- CE\
462
    X_7    : inout std_logic;       -- IO0
463
    X_8    : inout std_logic;       -- IO1
464
    X_9    : inout std_logic;       -- IO2
465
    X_10   : inout std_logic;       -- IO3
466
    X_11   : inout std_logic;       -- Vcc
467
    X_12   : inout std_logic;       -- GND
468
    X_13   : inout std_logic;       -- IO4
469
    X_14   : inout std_logic;       -- IO5 
470
    X_15   : inout std_logic;       -- IO6
471
    X_16   : inout std_logic;       -- IO7
472
    X_17   : in    std_logic;       -- WE\
473
    X_18   : inout std_logic;       -- A15
474
    X_19   : inout std_logic;       -- A14
475
    X_20   : inout std_logic;       -- A13
476
    X_21   : inout std_logic;       -- A12
477
--  X_22                            
478
--  X_23                            
479
    X_24   : in    std_logic;       -- A11
480
    X_25   : in    std_logic;       -- A10
481
    X_26   : in    std_logic;       -- A9
482
    X_27   : in    std_logic;       -- A8
483
--  X_28                            
484
    X_29   : inout std_logic;       -- IO8
485
    X_30   : inout std_logic;       -- IO9
486
    X_31   : inout std_logic;       -- IO10
487
    X_32   : inout std_logic;       -- IO11
488
    X_33   : inout std_logic;       -- VCC
489
    X_34   : inout std_logic;       -- GND 
490
    X_35   : inout std_logic;       -- IO12
491
    X_36   : inout std_logic;       -- IO13
492
    X_37   : inout std_logic;       -- IO14
493
    X_38   : inout std_logic;       -- IO15
494
    X_39   : in    std_logic;       -- BLE\
495
    X_40   : in    std_logic;       -- BHE\
496
    X_41   : in    std_logic;       -- OE\
497
    X_42   : in    std_logic;       -- A7
498
    X_43   : in    std_logic;       -- A6
499
    X_44   : in    std_logic        -- A5
500
);
501
end entity CY7C1021;
502
 
503
architecture BEHAV of CY7C1021 is
504
    signal D1, Q1, D2, Q2 : std_logic_vector( 7 downto 0);
505
    signal AD             : std_logic_vector(15 downto 0);
506
    signal CE1, CE2       : std_logic;
507
 
508
    constant finitE : boolean := fnevn /= "";    -- Initialise at power-up, if file defined
509
    constant finitO : boolean := fnodd /= "";
510
 
511
    alias nCE  is X_6;
512
    alias nWE  is X_17;
513
    alias nBLE is X_39;
514
    alias nBHE is X_40;
515
    alias nOE  is X_41;
516
 
517
begin
518
          (X_16, X_15, X_14, X_13, X_10, X_9,  X_8,  X_7 ) <= Q1;  -- Bidirectional bus
519
    D1 <= (X_16, X_15, X_14, X_13, X_10, X_9,  X_8,  X_7 );
520
          (X_38, X_37, X_36, X_35, X_32, X_31, X_30, X_29) <= Q2;  -- Bidirectional bus
521
    D2 <= (X_38, X_37, X_36, X_35, X_32, X_31, X_30, X_29);
522
    AD <= (X_18, X_19, X_20, X_21, X_24, X_25, X_26, X_27,
523
             X_42, X_43, X_44, X_1,  X_2,  X_3,  X_4,  X_5 );
524
    CE1 <= not nBLE;
525
    CE2 <= not nBHE;
526
 
527
    LB: sram         -- Generic RAM component
528
    generic map(
529
        value_on_power_up    => 'U',        -- Memory array is filled with this at start
530
        download_on_power_up => finitE,     -- if TRUE, RAM is downloaded at start of simulation 
531
        trace_ram_load       => false,      -- Echoes the data downloaded to the RAM on the screen
532
        enable_nWE_only_control => false,   -- Read-/write access controlled by nWE only
533
        -- READ-cycle timing parameters
534
        tAA_max           => tAA,           -- Address Access Time
535
        tOHA_min          => tOHA,          -- Output Hold Time
536
        tACE_max          => tACE,          -- nCE/CE2 Access Time
537
        tDOE_max          => tDOE,          -- nOE Access Time
538
        tLZOE_min         => tLZOE,         -- nOE to Low-Z Output
539
        tHZOE_max         => tHZOE,         --  OE to High-Z Output
540
        tLZCE_min         => tLZCE,         -- nCE/CE2 to Low-Z Output
541
        tHZCE_max         => tHZCE,         --  CE/nCE2 to High Z Output
542
 
543
        -- WRITE-cycle timing parameters
544
        tWC_min           => tWC,           -- Write Cycle Time
545
        tSCE_min          => tSCE,          -- nCE/CE2 to Write End
546
        tAW_min           => tAW,           -- tAW Address Set-up Time to Write End
547
        tHA_min           => tHA,           -- tHA Address Hold from Write End
548
        tSA_min           => tSA,           -- Address Set-up Time
549
        tPWE_min          => tPWE,          -- nWE Pulse Width
550
        tSD_min           => tSD,           -- Data Set-up to Write End
551
        tHD_min           => tHD,           -- Data Hold from Write End
552
        tHZWE_max         => tHZWE,         -- nWE Low to High-Z Output
553
        tLZWE_min         => tLZWE          -- nWE High to Low-Z Output
554
    )
555
    port map(
556
        nCE               => nCE,           -- low-active Chip-Enable of the SRAM device; defaults to '1' (inactive)
557
        nOE               => nOE,           -- low-active Output-Enable of the SRAM device; defaults to '1' (inactive)
558
        nWE               => nWE,           -- low-active Write-Enable of the SRAM device; defaults to '1' (inactive)
559
        A                 => AD,            -- address bus of the SRAM device
560
        D                 => D1,            -- data bus to the SRAM device
561
        Q                 => Q1,            -- data bus from the SRAM device
562
        CE2               => CE1,           -- high-active Chip-Enable of the SRAM device; defaults to '1'  (active) 
563
        download          => false,         -- A FALSE-to-TRUE transition on this signal downloads the data
564
        download_filename => "fnevn"        -- name of the download source file
565
    );
566
 
567
    HB: sram         -- Generic RAM component
568
    generic map(
569
        value_on_power_up       => 'U',     -- Memory array is filled with this at start
570
        download_on_power_up    => finitO,  -- if TRUE, RAM is downloaded at start of simulation 
571
        trace_ram_load          => false,   -- Echoes the data downloaded to the RAM on the screen
572
        enable_nWE_only_control => false,   -- Read-/write access controlled by nWE only
573
        -- READ-cycle timing parameters
574
        tAA_max           => tAA,           -- Address Access Time
575
        tOHA_min          => tOHA,          -- Output Hold Time
576
        tACE_max          => tACE,          -- nCE/CE2 Access Time
577
        tDOE_max          => tDOE,          -- nOE Access Time
578
        tLZOE_min         => tLZOE,         -- nOE to Low-Z Output
579
        tHZOE_max         => tHZOE,         --  OE to High-Z Output
580
        tLZCE_min         => tLZCE,         -- nCE/CE2 to Low-Z Output
581
        tHZCE_max         => tHZCE,         --  CE/nCE2 to High Z Output
582
 
583
        -- WRITE-cycle timing parameters
584
        tWC_min           => tWC,           -- Write Cycle Time
585
        tSCE_min          => tSCE,          -- nCE/CE2 to Write End
586
        tAW_min           => tAW,           -- tAW Address Set-up Time to Write End
587
        tHA_min           => tHA,           -- tHA Address Hold from Write End
588
        tSA_min           => tSA,           -- Address Set-up Time
589
        tPWE_min          => tPWE,          -- nWE Pulse Width
590
        tSD_min           => tSD,           -- Data Set-up to Write End
591
        tHD_min           => tHD,           -- Data Hold from Write End
592
        tHZWE_max         => tHZWE,         -- nWE Low to High-Z Output
593
        tLZWE_min         => tLZWE          -- nWE High to Low-Z Output
594
    )
595
    port map(
596
        nCE               => nCE,           -- low-active Chip-Enable of the SRAM device; defaults to '1' (inactive)
597
        nOE               => nOE,           -- low-active Output-Enable of the SRAM device; defaults to '1' (inactive)
598
        nWE               => nWE,           -- low-active Write-Enable of the SRAM device; defaults to '1' (inactive)
599
        A                 => AD,            -- address bus of the SRAM device
600
        D                 => D2,            -- data bus to the SRAM device
601
        Q                 => Q2,            -- data bus from the SRAM device
602
        CE2               => CE2,           -- high-active Chip-Enable of the SRAM device; defaults to '1'  (active) 
603
        download          => false,         -- A FALSE-to-TRUE transition on this signal downloads the data
604
        download_filename => "fnodd"        -- name of the download source file
605
    );
606
end architecture BEHAV;

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