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1 6 david237
-----------------------------------------------------------------------
2
-- Static RAM models (VHDL)                                          --
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-- David R Brooks                                                    --
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-- December, 2016.  Perth, Australia                                 --
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-- Compliance: VHDL 2008                                             --
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-- NB Simulation only: they are NOT synthesizable.                   --
7
-- Based on: Manufacturers data sheets                               --
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-- Pinouts & naming agree with Altium libraries & VHDL netlister.    --
9
-----------------------------------------------------------------------
10
library ieee;
11
    use ieee.std_logic_1164.all;
12
 
13
package MEMORIES is
14
 
15
-----------------------------------------------------------------------
16
-- Generic SRAM model, see https://tams.informatik.uni-hamburg.de/vhdl/models/sram/sram.html
17
-----------------------------------------------------------------------
18
component sram is
19
    generic (
20
        value_on_power_up    : std_logic := 'U';    -- Memory array is filled with this at start
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        download_on_power_up : boolean   := TRUE;   -- if TRUE, RAM is downloaded at start of simulation 
22
        trace_ram_load       : boolean   := TRUE;   -- Echoes the data downloaded to the RAM on the screen
23
                                                    --   (included for debugging purposes)
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        enable_nWE_only_control: boolean := TRUE;   -- Read-/write access controlled by nWE only
25
                                                    --   nOE may be kept active all the time
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        -- READ-cycle timing parameters
27
        tAA_max     : TIME               := 20 NS;  -- Address Access Time
28
        tOHA_min    : TIME               :=  3 NS;  -- Output Hold Time
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        tACE_max    : TIME               := 20 NS;  -- nCE/CE2 Access Time
30
        tDOE_max    : TIME               :=  8 NS;  -- nOE Access Time
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        tLZOE_min   : TIME               :=  0 NS;  -- nOE to Low-Z Output
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        tHZOE_max   : TIME               :=  8 NS;  --  OE to High-Z Output
33
        tLZCE_min   : TIME               :=  3 NS;  -- nCE/CE2 to Low-Z Output
34
        tHZCE_max   : TIME               := 10 NS;  --  CE/nCE2 to High Z Output
35
 
36
        -- WRITE-cycle timing parameters
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        tWC_min     : TIME               := 20 NS;  -- Write Cycle Time
38
        tSCE_min    : TIME               := 18 NS;  -- nCE/CE2 to Write End
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        tAW_min     : TIME               := 15 NS;  -- tAW Address Set-up Time to Write End
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        tHA_min     : TIME               :=  0 NS;  -- tHA Address Hold from Write End
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        tSA_min     : TIME               :=  0 NS;  -- Address Set-up Time
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        tPWE_min    : TIME               := 13 NS;  -- nWE Pulse Width
43
        tSD_min     : TIME               := 10 NS;  -- Data Set-up to Write End
44
        tHD_min     : TIME               :=  0 NS;  -- Data Hold from Write End
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        tHZWE_max   : TIME               := 10 NS;  -- nWE Low to High-Z Output
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        tLZWE_min   : TIME               :=  0 NS   -- nWE High to Low-Z Output
47
    );
48
 
49
    port (
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        nCE         : in    std_logic    := '1';    -- low-active Chip-Enable of the SRAM device; defaults to '1' (inactive)
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        nOE         : in    std_logic    := '1';    -- low-active Output-Enable of the SRAM device; defaults to '1' (inactive)
52
        nWE         : in    std_logic    := '1';    -- low-active Write-Enable of the SRAM device; defaults to '1' (inactive)
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        A           : in    std_logic_vector;       -- address bus of the SRAM device
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        D           : in    std_logic_vector;       -- data bus to the SRAM device
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        Q           : out   std_logic_vector;       -- data bus from the SRAM device
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        CE2         : in    std_logic    := '1';    -- high-active Chip-Enable of the SRAM device; defaults to '1'  (active) 
57
        download    : in    boolean      := FALSE;  -- A FALSE-to-TRUE transition on this signal downloads the data
58
                                                    --   in file specified by download_filename to the RAM
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        download_filename: in string := "sram_load.dat";  -- name of the download source file
60
                                                          --            Passing the filename via a port of type
61
                                                          -- ********** string may cause a problem with some
62
                                                          -- WATCH OUT! simulators. The string signal assigned
63
                                                          -- ********** to the port at least should have the
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                                                          --            same length as the default value.
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        dump        : in    boolean      := FALSE;  -- A FALSE-to-TRUE transition on this signal dumps
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                                                    --   the current content of the memory to the file
67
                                                    --   specified by dump_filename.
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        dump_start  : in    natural      := 0;      -- Written to the dump-file are the memory words from memory address 
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        dump_end    : in    natural      := 0;      -- dump_start to address dump_end (default: all addresses)
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        dump_filename:in    string := "sram_dump.dat"  -- name of the dump destination file
71
                                                       -- (See note at port  download_filename)
72
    );
73
end component sram;
74
 
75
 
76
-----------------------------------------------------------------------
77
-- HM6116, TMM2016 : 2K x 8 CMOS static RAM (HMI, Texas)
78
-----------------------------------------------------------------------
79
component HM6116 is
80
generic(
81
    fname : String := "";           -- Name of initialisation file (if any)
82
    --               min    max
83
    tRC   : time   := 70        ns; -- Read cycle (not used)
84
    tAA   : time   :=        70 ns; -- Address access
85
    tACS  : time   :=        70 ns; -- Chip select access
86
    tAOE  : time   :=        30 ns; -- OE\ to output valid
87
    tCLZ  : time   :=  5        ns; -- CS\ to output valid
88
    tOLZ  : time   :=  5        ns; -- OE\ to output valid
89
    tCHZ  : time   :=        20 ns; -- CS  to output Hi-Z
90
    tOHZR : time   :=        20 ns; -- OE  to output Hi-Z
91
    tOH   : time   :=  3        ns; -- OP hold from addr change
92
 
93
    tWC   : time   := 70        ns; -- Write cycle
94
    tCW   : time   := 70        ns; -- CS to end of write
95
    tAW   : time   := 70        ns; -- Address valid to end of write
96
    tAS   : time   :=  0        ns; -- Address setup time
97
    tDS   : time   :=  0        ns; -- Data setup time
98
    tWP   : time   := 50        ns; -- Write pulse width
99
    tWR   : time   :=  0        ns; -- Write recovery time
100
    tDW   : time   := 30        ns; -- Data valid to end of write
101
    tDH   : time   :=  0        ns; -- Data hold from end of write
102
    tWHZ  : time   :=        25 ns; -- Write to OP Hi-Z
103
    tWLZ  : time   :=  5        ns; -- Write to OP Lo-Z (not used)
104
    tOHZW : time   :=        30 ns; -- OE to OP Hi-Z
105
    tOW   : time   :=  5        ns  -- OP active from end of write
106
);
107
port(
108
    X_1  : in    std_logic;  -- A7
109
    X_2  : in    std_logic;  -- A6
110
    X_3  : in    std_logic;  -- A5
111
    X_4  : in    std_logic;  -- A4
112
    X_5  : in    std_logic;  -- A3
113
    X_6  : in    std_logic;  -- A2
114
    X_7  : in    std_logic;  -- A1
115
    X_8  : in    std_logic;  -- A0
116
    X_9  : inout std_logic;  -- IO0
117
    X_10 : inout std_logic;  -- IO1
118
    X_11 : inout std_logic;  -- IO2
119
    X_12 : inout std_logic;  -- GND
120
    X_13 : inout std_logic;  -- IO3
121
    X_14 : inout std_logic;  -- IO4 
122
    X_15 : inout std_logic;  -- IO5
123
    X_16 : inout std_logic;  -- IO6
124
    X_17 : inout std_logic;  -- IO7
125
    X_18 : in    std_logic;  -- CS\
126
    X_19 : in    std_logic;  -- A10
127
    X_20 : in    std_logic;  -- OE\
128
    X_21 : in    std_logic;  -- WE\
129
    X_22 : in    std_logic;  -- A9
130
    X_23 : in    std_logic;  -- A8
131
    X_24 : inout std_logic   -- Vcc
132
);
133
end component HM6116;
134
 
135
-----------------------------------------------------------------------
136
-- IS61C1024-20: 128K x 8 CMOS static RAM (ISSI)
137
-----------------------------------------------------------------------
138
component IS61C1024 is
139
generic(
140
    fname  : String := "";               -- Name of initialisation file (if any)
141
    -- Read Cycle     Min.  Max. Unit    Parameter                       
142
    tRC    : time :=  20         ns;     -- Read Cycle Time                
143
    tAA    : time :=        20   ns;     -- Address Access Time            
144
    tOHA   : time :=   3         ns;     -- Output Hold Time               
145
    tACE1  : time :=        20   ns;     -- CE1 Access Time                
146
    tACE2  : time :=        20   ns;     -- CE2 Access Time                
147
    tDOE   : time :=         9   ns;     -- Access Time                    
148
    tLZOE  : time :=   0         ns;     -- OE to Low-Z Output             
149
    tHZOE  : time :=         7   ns;     -- OE to High-Z Output            
150
    tLZCE1 : time :=   3         ns;     -- CE1 to Low-Z Output            
151
    tLZCE2 : time :=   3         ns;     -- CE2 to Low-Z Output            
152
    tHZCE  : time :=         9   ns;     -- CE1 or CE2 to High-Z Output    
153
    tPU    : time :=   0         ns;     -- CE1 or CE2 to Power-Up         
154
    tPD    : time :=        18   ns;     -- CE1 or CE2 to Power-Down       
155
 
156
    -- Write Cycle    Min.  Max. Unit    Parameter                       
157
    tWC    : time :=  20         ns;     -- Write Cycle Time               
158
    tSCE1  : time :=  15         ns;     -- CE1 to Write End               
159
    tSCE2  : time :=  15         ns;     -- CE2 to Write End               
160
    tAW    : time :=  15         ns;     -- Address Setup Time to Write End
161
    tHA    : time :=   0         ns;     -- Address Hold from Write End    
162
    tSA    : time :=   0         ns;     -- Address Setup Time             
163
    tPWE   : time :=  12         ns;     -- WE Pulse Width                 
164
    tSD    : time :=  10         ns;     -- Data Setup to Write End        
165
    tHD    : time :=   0         ns;     -- Data Hold from Write End       
166
    tHZWE  : time :=        10   ns;     -- WE LOW to High-Z Output        
167
    tLZWE  : time :=   2         ns      -- WE HIGH to Low-Z Output        
168
);
169
port(
170
--  X_1
171
    X_2  : in    std_logic;  -- A16
172
    X_3  : in    std_logic;  -- A14
173
    X_4  : in    std_logic;  -- A12
174
    X_5  : in    std_logic;  -- A7
175
    X_6  : in    std_logic;  -- A6
176
    X_7  : in    std_logic;  -- A5
177
    X_8  : in    std_logic;  -- A4
178
    X_9  : in    std_logic;  -- A3
179
    X_10 : in    std_logic;  -- A2
180
    X_11 : in    std_logic;  -- A1
181
    X_12 : in    std_logic;  -- A0
182
    X_13 : inout std_logic;  -- IO0
183
    X_14 : inout std_logic;  -- IO1 
184
    X_15 : inout std_logic;  -- IO2
185
    X_16 : inout std_logic;  -- GND
186
    X_17 : inout std_logic;  -- IO3
187
    X_18 : inout std_logic;  -- IO4
188
    X_19 : inout std_logic;  -- IO5
189
    X_20 : inout std_logic;  -- IO6
190
    X_21 : inout std_logic;  -- IO7
191
    X_22 : in    std_logic;  -- CE1\
192
    X_23 : in    std_logic;  -- A10
193
    X_24 : in    std_logic;  -- OE\
194
    X_25 : in    std_logic;  -- A11
195
    X_26 : in    std_logic;  -- A9
196
    X_27 : in    std_logic;  -- A8
197
    X_28 : in    std_logic;  -- A13
198
    X_29 : in    std_logic;  -- WE\
199
    X_30 : in    std_logic;  -- CE2
200
    X_31 : in    std_logic;  -- A15
201
    X_32 : inout std_logic   -- Vcc
202
);
203
end component IS61C1024;
204
 
205
-----------------------------------------------------------------------
206
-- MB84256A-10LL : 2K x 8 CMOS static RAM (Fujitsu, 100 ns)
207
-----------------------------------------------------------------------
208
component MB84256 is
209
generic(
210
    fname   : String := "";             -- Name of initialisation file (if any)
211
    -- Read Cycle     Min   Max
212
    tRC     : time := 100       ns;     -- Read cycle time
213
    tAA     : time :=       100 ns;     -- Address access time
214
    tACS    : time :=       100 ns;     -- nCS1 access time
215
    tOE     : time :=        40 ns;     -- Output enable to output valid
216
    tOH     : time :=  20       ns;     -- Output hold from address change
217
    tCLZ    : time :=  10       ns;     -- Chip select to output Lo-Z
218
    tOLZ    : time :=   5       ns;     -- Output enable to output Lo-Z
219
    tCHZ    : time :=        40 ns;     -- Chip select to output Hi-Z
220
    tOHZ    : time :=        40 ns;     -- Output enable to output Hi-Z
221
    -- Write Cycle    Min   Max
222
    tWC     : time := 100       ns;     -- Write cycle time
223
    tAW     : time :=  80       ns;     -- Address valid to end of write
224
    tCW     : time :=  80       ns;     -- Chip select to end of write
225
    tDW     : time :=  40       ns;     -- Data valid to end of write
226
    tDH     : time :=   0       ns;     -- Data hold time
227
    tWP     : time :=  60       ns;     -- Write pulse width
228
    tAS     : time :=   0       ns;     -- Address setup time
229
    tWR     : time :=   5       ns;     -- Write recovery time
230
    tWLZ    : time :=   5       ns;     -- nWE to output Lo-Z
231
    tWHZ    : time :=        40 ns      -- nWE to output Hi-Z
232
);
233
port(
234
    X_1  : in    std_logic;  -- A14
235
    X_2  : in    std_logic;  -- A12
236
    X_3  : in    std_logic;  -- A7
237
    X_4  : in    std_logic;  -- A6
238
    X_5  : in    std_logic;  -- A5
239
    X_6  : in    std_logic;  -- A4
240
    X_7  : in    std_logic;  -- A3
241
    X_8  : in    std_logic;  -- A2
242
    X_9  : in    std_logic;  -- A1
243
    X_10 : in    std_logic;  -- A0
244
    X_11 : inout std_logic;  -- IO0
245
    X_12 : inout std_logic;  -- IO1
246
    X_13 : inout std_logic;  -- IO2
247
    X_14 : inout std_logic;  -- GND
248
    X_15 : inout std_logic;  -- IO3
249
    X_16 : inout std_logic;  -- IO4 
250
    X_17 : inout std_logic;  -- IO5
251
    X_18 : inout std_logic;  -- IO6
252
    X_19 : inout std_logic;  -- IO7
253
    X_20 : in    std_logic;  -- CS\
254
    X_21 : in    std_logic;  -- A10
255
    X_22 : in    std_logic;  -- OE\
256
    X_23 : in    std_logic;  -- A11
257
    X_24 : in    std_logic;  -- A9
258
    X_25 : in    std_logic;  -- A8
259
    X_26 : inout std_logic;  -- A13
260
    X_27 : in    std_logic;  -- WE\
261
    X_28 : inout std_logic   -- Vcc
262
);
263
end component MB84256;
264
 
265
-----------------------------------------------------------------------
266
-- CY7C1021-V33: 64K x 16 CMOS static RAM (Cypress)
267
-----------------------------------------------------------------------
268
component CY7C1021 is
269
generic(
270
    fnevn : String := "";           -- Name of even-byte initialisation file (if any)
271
    fnodd : String := "";           -- Name of odd-byte  initialisation file (if any)
272
    --               min    max
273
    tRC   : time   := 20        ns; -- Read cycle
274
    tAA   : time   :=        20 ns; -- Address access
275
    tACS  : time   :=        20 ns; -- Chip select access
276
    tAOE  : time   :=         9 ns; -- OE\ to output valid
277
    tCLZ  : time   :=  5        ns; -- CS\ to output valid
278
    tOLZ  : time   :=  5        ns; -- OE\ to output valid
279
    tCHZ  : time   :=        20 ns; -- CS  to output Hi-Z
280
    tOHZR : time   :=        20 ns; -- OE  to output Hi-Z
281
    tOH   : time   :=  3        ns; -- OP hold from addr change
282
 
283
    tWC   : time   := 20        ns; -- Write cycle
284
    tCW   : time   := 15        ns; -- CS to end of write
285
--    tAW   : time   := 70        ns; -- Address valid to end of write
286
    tAS   : time   := 15        ns; -- Address setup time
287
    tDS   : time   := 10        ns; -- Data setup time
288
    tWP   : time   := 12        ns; -- Write pulse width
289
    tWR   : time   :=  0        ns; -- Write recovery time
290
    tDW   : time   := 30        ns; -- Data valid to end of write
291
    tDH   : time   :=  0        ns; -- Data hold from end of write
292
    tWHZ  : time   :=        25 ns; -- Write to OP Hi-Z
293
--  tWLZ  : time   :=  5        ns; -- Write to OP Lo-Z    
294
    tOHZW : time   :=        30 ns; -- OE to OP Hi-Z
295
    tOW   : time   :=  5        ns  -- OP active from end of write
296
);
297
port(
298
    X_1  : in    std_logic;  -- A4
299
    X_2  : in    std_logic;  -- A3
300
    X_3  : in    std_logic;  -- A2
301
    X_4  : in    std_logic;  -- A1
302
    X_5  : in    std_logic;  -- A0
303
    X_6  : in    std_logic;  -- CE\
304
    X_7  : inout std_logic;  -- IO0
305
    X_8  : inout std_logic;  -- IO1
306
    X_9  : inout std_logic;  -- IO2
307
    X_10 : inout std_logic;  -- IO3
308
    X_11 : inout std_logic;  -- Vcc
309
    X_12 : inout std_logic;  -- GND
310
    X_13 : inout std_logic;  -- IO4
311
    X_14 : inout std_logic;  -- IO5 
312
    X_15 : inout std_logic;  -- IO6
313
    X_16 : inout std_logic;  -- IO7
314
    X_17 : in    std_logic;  -- WE\
315
    X_18 : inout std_logic;  -- A15
316
    X_19 : inout std_logic;  -- A14
317
    X_20 : inout std_logic;  -- A13
318
    X_21 : inout std_logic;  -- A12
319
--  X_22
320
--  X_23
321
    X_24 : in    std_logic;  -- A11
322
    X_25 : in    std_logic;  -- A10
323
    X_26 : in    std_logic;  -- A9
324
    X_27 : in    std_logic;  -- A8
325
--  X_28
326
    X_29 : inout std_logic;  -- IO8
327
    X_30 : inout std_logic;  -- IO9
328
    X_31 : inout std_logic;  -- IO10
329
    X_32 : inout std_logic;  -- IO11
330
    X_33 : inout std_logic;  -- VCC
331
    X_34 : inout std_logic;  -- GND 
332
    X_35 : inout std_logic;  -- IO12
333
    X_36 : inout std_logic;  -- IO13
334
    X_37 : inout std_logic;  -- IO14
335
    X_38 : inout std_logic;  -- IO15
336
    X_39 : in    std_logic;  -- BLE\
337
    X_40 : in    std_logic;  -- BHE\
338
    X_41 : in    std_logic;  -- OE\
339
    X_42 : in    std_logic;  -- A7
340
    X_43 : in    std_logic;  -- A6
341
    X_44 : in    std_logic   -- A5
342
);
343
end component CY7C1021;
344
 
345
end package MEMORIES;

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