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david237 |
-- ======================================================================================
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-- A generic VHDL entity for a typical SRAM with complete timing parameters
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--
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-- Static memory, version 1.3 9. August 1996
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-- Changes by D. R. Brooks, see below
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-- ======================================================================================
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--
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-- (C) Andre' Klindworth, Dept. of Computer Science
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-- University of Hamburg
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-- Vogt-Koelln-Str. 30
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-- 22527 Hamburg
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-- klindwor@informatik.uni-hamburg.de
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--
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-- This VHDL code may be freely copied as long as the copyright note isn't removed from
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-- its header. Full affiliation of anybody modifying this file shall be added to the
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-- header prior to further distribution.
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-- The download procedure originates from DLX memory-behaviour.vhdl:
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-- Copyright (C) 1993, Peter J. Ashenden
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-- Mail: Dept. Computer Science
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-- University of Adelaide, SA 5005, Australia
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-- e-mail: petera@cs.adelaide.edu.au
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--
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-- Changes by D. R. Brooks, Perth, Australia. <daveb@iinet.net.au>
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-- 1. Changed file statements to suit VHDL-2008
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-- 2. Removed references to obsolete package "IEEE.std_logic_unsigned"
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-- 3. Array initialisation is by specifying the value, not a boolean.
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-- 4. Cleaned up tabbing.
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-- 5. Array size is inferred from the connected address & data busses.
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-- 6. IO is split into IN & OUT ports, to facilitate higher-level connections.
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--
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-- Features:
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--
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-- o generic memory size, width and timing parameters
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--
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-- o 18 typical SRAM timing parameters supported
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--
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-- o clear-on-power-up and/or download-on-power-up if requested by generic
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--
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-- o RAM dump into or download from an ASCII-file at any time possible
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-- (requested by signal)
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--
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-- o pair of active-low and active-high Chip-Enable signals
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--
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-- o nWE-only memory access control
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--
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-- o many (but not all) timing and access control violations reported by assertions
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--
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--
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--
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-- RAM data file format:
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--
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-- The format of the ASCII-files for RAM download or dump is very simple:
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-- Each line of the file consists of the memory address (given as a decimal number).
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-- and the corresponding RAM data at this address (given as a binary number).
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-- Any text in a line following the width-th digit of the binary number is ignored.
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-- Please notice that address and data have to be seperated by a SINGLE blank,
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-- that the binary number must have as many digits as specified by the generic width,
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-- and that no additional blanks or blank lines are tolerated. Example:
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--
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-- 0 0111011010111101 This text is interpreted as a comment
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-- 1 1011101010110010
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-- 17 0010001001000100
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--
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--
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-- Hints & traps:
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--
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-- If you have problems using this model, please feel free to to send me an e-mail.
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-- Here are some potential problems which have been reported to me:
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--
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-- o There's a potential problem with passing the filenames for RAM download or
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-- dump via port signals of type string. E.g. for Synopsys VSS, the string
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-- assigned to a filename-port should have the same length as its default value.
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-- If you are sure that you need a download or dump only once during a single
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-- simulation run, you may remove the filename-ports from the interface list
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-- and replace the constant string in the corresponding file declarations.
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--
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-- o Some simulators do not implement all of the standard TEXTIO-functions as
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-- specified by the IEEE Std 1076-87 and IEEE Std 1076-93. Check it out.
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-- If any of the (multiple overloaded) writeline, write, readline or
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-- read functions that are used in this model is missing, you have to
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-- write your own version and you should complain at your simulator tool
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-- vendor for this deviation from the standard.
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--
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-- o If you are about to simulate a large RAM e.g. 4M * 32 Bit, representing
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-- the RAM with a static array variable of 4 * 32 std_logic values uses a large
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-- amount of memory and may result in an out-of-memory error. A potential remedy
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-- for this is to use a dynamic data type, allocating memory for small blocks of
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-- RAM data (e.g. a single word) only if they are actually referenced during a
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-- simulation run. A version of the SRAM model with dynamic memory allocation
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-- shall be available at the same WWW-site were you obtained this file or at:
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-- http://tech-www.informatik.uni-hamburg.de/vhdl/models/sram/sram.html
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--
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--
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-- Bugs:
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--
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-- No severe bugs have been found so far. Please report any bugs:
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-- e-mail: klindwor@informatik.uni-hamburg.de
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--
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-- Bug Observed: ModelSim SE-64 vcom 10.1c crashes with Code 211 (segmentation fault), when
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-- 'DELAYED is applied to a std_logic_vector. 'DELAYED works on single std_logic, but
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-- fails when used on an array element (Attribute "DELAYED" requires a static signal prefix).
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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ENTITY sram IS
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GENERIC (
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value_on_power_up : std_logic := 'U'; -- Memory array is filled with this at start
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download_on_power_up : boolean := TRUE; -- if TRUE, RAM is downloaded at start of simulation
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trace_ram_load : boolean := TRUE; -- Echoes the data downloaded to the RAM on the screen
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-- (included for debugging purposes)
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enable_nWE_only_control: boolean := TRUE; -- Read-/write access controlled by nWE only
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-- nOE may be kept active all the time
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-- READ-cycle timing parameters
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tAA_max : TIME := 20 NS; -- Address Access Time
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tOHA_min : TIME := 3 NS; -- Output Hold Time
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tACE_max : TIME := 20 NS; -- nCE/CE2 Access Time
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tDOE_max : TIME := 8 NS; -- nOE Access Time
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tLZOE_min : TIME := 0 NS; -- nOE to Low-Z Output
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tHZOE_max : TIME := 8 NS; -- OE to High-Z Output
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tLZCE_min : TIME := 3 NS; -- nCE/CE2 to Low-Z Output
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tHZCE_max : TIME := 10 NS; -- CE/nCE2 to High Z Output
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-- WRITE-cycle timing parameters
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tWC_min : TIME := 20 NS; -- Write Cycle Time
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tSCE_min : TIME := 18 NS; -- nCE/CE2 to Write End
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tAW_min : TIME := 15 NS; -- tAW Address Set-up Time to Write End
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tHA_min : TIME := 0 NS; -- tHA Address Hold from Write End
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tSA_min : TIME := 0 NS; -- Address Set-up Time
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tPWE_min : TIME := 13 NS; -- nWE Pulse Width
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tSD_min : TIME := 10 NS; -- Data Set-up to Write End
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tHD_min : TIME := 0 NS; -- Data Hold from Write End
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tHZWE_max : TIME := 10 NS; -- nWE Low to High-Z Output
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tLZWE_min : TIME := 0 NS -- nWE High to Low-Z Output
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);
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PORT (
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nCE : IN std_logic := '1'; -- low-active Chip-Enable of the SRAM device; defaults to '1' (inactive)
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nOE : IN std_logic := '1'; -- low-active Output-Enable of the SRAM device; defaults to '1' (inactive)
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nWE : IN std_logic := '1'; -- low-active Write-Enable of the SRAM device; defaults to '1' (inactive)
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A : IN std_logic_vector; -- address bus of the SRAM device
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D : IN std_logic_vector; -- data bus to the SRAM device
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Q : OUT std_logic_vector; -- data bus from the SRAM device
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CE2 : IN std_logic := '1'; -- high-active Chip-Enable of the SRAM device; defaults to '1' (active)
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download : IN boolean := FALSE; -- A FALSE-to-TRUE transition on this signal downloads the data
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-- in file specified by download_filename to the RAM
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download_filename: IN string := "sram_load.dat"; -- name of the download source file
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-- Passing the filename via a port of type
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-- ********** string may cause a problem with some
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-- WATCH OUT! simulators. The string signal assigned
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-- ********** to the port at least should have the
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-- same length as the default value.
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dump : IN boolean := FALSE; -- A FALSE-to-TRUE transition on this signal dumps
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-- the current content of the memory to the file
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-- specified by dump_filename.
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dump_start : IN natural := 0; -- Written to the dump-file are the memory words from memory address
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dump_end : IN natural := 0; -- dump_start to address dump_end (default: all addresses)
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dump_filename:IN string := "sram_dump.dat" -- name of the dump destination file
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-- (See note at port download_filename)
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);
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END entity sram;
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ARCHITECTURE behavior OF sram IS
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subtype ibyte is integer range 0 to 255; -- 8-bit integer
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type iline is array(0 to 299) of ibyte;
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constant dwidth : positive := D'length;
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constant awidth : positive := A'length;
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constant nwords : positive := 2**awidth;
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-----------------------------------------------------------------------
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-- Return TRUE if all bits are '0' or '1'
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-----------------------------------------------------------------------
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FUNCTION Check_For_Valid_Data (a: std_logic_vector) RETURN BOOLEAN IS
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VARIABLE result: BOOLEAN;
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BEGIN
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result := TRUE;
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FOR i IN a'RANGE LOOP
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result := (a(i) = '0') OR (a(i) = '1');
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IF NOT result THEN
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EXIT;
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END IF;
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END LOOP;
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RETURN result;
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END Check_For_Valid_Data;
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-----------------------------------------------------------------------
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-- Return TRUE if all bits are 'Z'
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-----------------------------------------------------------------------
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FUNCTION Check_For_Tristate (a: std_logic_vector) RETURN BOOLEAN IS
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VARIABLE result: BOOLEAN;
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BEGIN
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result := TRUE;
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FOR i IN a'RANGE LOOP
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result := (a(i) = 'Z');
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IF NOT result THEN
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EXIT;
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END IF;
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END LOOP;
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RETURN result;
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END Check_For_Tristate;
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-----------------------------------------------------------------------
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-- Global signals
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-----------------------------------------------------------------------
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constant tristate_vec : std_logic_vector(D'RANGE) := (others=> 'Z');
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constant undef_vec : std_logic_vector(D'RANGE) := (others=> 'X');
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constant init_vec : std_logic_vector(D'RANGE) := (others=> value_on_power_up);
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constant undef_adr_vec : std_logic_vector(A'RANGE) := (others=> 'X');
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SIGNAL read_active : BOOLEAN := FALSE; -- Indicates whether the SRAM is sending on the D bus
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SIGNAL read_valid : BOOLEAN := FALSE; -- If TRUE, the data output by the RAM is valid
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SIGNAL read_data : std_logic_vector(D'RANGE); -- content of the memory location addressed by A
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SIGNAL do_write : std_logic := '0'; -- A '0'->'1' transition on this signal marks
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-- the moment when the data on D is stored in the
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-- addressed memory location
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SIGNAL adr_setup : std_logic_vector(A'RANGE); -- delayed value of A to model the Address Setup Time
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SIGNAL adr_hold : std_logic_vector(A'RANGE); -- delayed value of A to model the Address Hold Time
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SIGNAL valid_adr : std_logic_vector(A'RANGE); -- valid memory address derived from A after
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-- considering Address Setup and Hold Times
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signal DD1, DD2 : std_logic_vector(D'range); -- Delayed versions of D
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BEGIN
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-- vsim fails on std_logic_vector'DELAYED, so create explicit delayed versions here
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-- See body of process "memory"
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DD1 <= D; -- D'DELAYED
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DD2 <= D after tHD_min; -- D'DELAYED(tHD_min)
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-----------------------------------------------------------------------
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-- The main task. The memory array is a private variable of this
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-- process.
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-----------------------------------------------------------------------
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memory: PROCESS
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CONSTANT low_address : natural := 0;
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CONSTANT high_address : natural := nwords -1;
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TYPE memory_array IS
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ARRAY (natural RANGE low_address TO high_address) OF std_logic_vector(D'range);
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type memptr is access memory_array;
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variable memp : memptr := null; -- Ptr. to memory array
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VARIABLE address : natural;
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VARIABLE write_data : std_logic_vector(D'range);
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-------------------------------------------------------------------
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-- Initialise array at start: this happens before any file-load
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-------------------------------------------------------------------
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PROCEDURE power_up (memp: inout memptr) IS
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BEGIN
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if memp = null then
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memp := new memory_array;
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end if;
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FOR add IN memp.all'range LOOP
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memp.all(add) := init_vec;
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END LOOP;
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END power_up;
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-------------------------------------------------------------------
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-- Load binary file (see above for format) into array
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-------------------------------------------------------------------
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PROCEDURE load (memp: INOUT memptr; download_filename: IN string) IS
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FILE source : text;
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VARIABLE inline, outline : line;
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VARIABLE add : natural;
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VARIABLE c : character;
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VARIABLE source_line_nr : integer := 1;
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VARIABLE init_value : std_logic := 'U';
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BEGIN
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write(output, string'("Loading SRAM from file ") & download_filename & string'(" ... ") );
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file_open(source, download_filename, READ_MODE);
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WHILE NOT endfile(source) LOOP
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readline(source, inline);
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read(inline, add);
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read(inline, c);
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IF (c /= ' ') THEN
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write(outline, string'("Syntax error in file '"));
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write(outline, download_filename);
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write(outline, string'("', line "));
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write(outline, source_line_nr);
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writeline(output, outline);
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ASSERT FALSE
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REPORT "RAM loader aborted."
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SEVERITY FAILURE;
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END IF;
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FOR i IN D'range LOOP
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read(inline, c);
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case c is
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when '0' => memp.all(add)(i) := '0';
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when '1' => memp.all(add)(i) := '1';
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when others =>
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write(outline, string'("-W- Invalid character '"));
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write(outline, c);
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write(outline, string'("' in Bitstring in '"));
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write(outline, download_filename);
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write(outline, '(');
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write(outline, source_line_nr);
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write(outline, string'(") is set to '0'"));
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writeline(output, outline);
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memp.all(add)(i) := '0';
|
| 307 |
|
|
end case;
|
| 308 |
|
|
END LOOP;
|
| 309 |
|
|
IF (trace_ram_load) THEN
|
| 310 |
|
|
write(outline, string'("RAM["));
|
| 311 |
|
|
write(outline, add);
|
| 312 |
|
|
write(outline, string'("] := "));
|
| 313 |
|
|
write(outline, memp.all(add));
|
| 314 |
|
|
writeline(output, outline );
|
| 315 |
|
|
END IF;
|
| 316 |
|
|
source_line_nr := source_line_nr +1;
|
| 317 |
|
|
END LOOP; -- WHILE
|
| 318 |
|
|
file_close(source);
|
| 319 |
|
|
END PROCEDURE load;
|
| 320 |
|
|
|
| 321 |
|
|
-------------------------------------------------------------------
|
| 322 |
|
|
-- Write out the array (see above for format)
|
| 323 |
|
|
-------------------------------------------------------------------
|
| 324 |
|
|
PROCEDURE do_dump (memp: INOUT memptr;
|
| 325 |
|
|
dump_start, dump_end: IN natural;
|
| 326 |
|
|
dump_filename: IN string) IS
|
| 327 |
|
|
FILE dest : text;
|
| 328 |
|
|
VARIABLE l : line;
|
| 329 |
|
|
VARIABLE c : character;
|
| 330 |
|
|
variable d_top : natural;
|
| 331 |
|
|
BEGIN
|
| 332 |
|
|
if dump_end = 0 then
|
| 333 |
|
|
d_top := nwords-1;
|
| 334 |
|
|
else
|
| 335 |
|
|
d_top := dump_end;
|
| 336 |
|
|
end if;
|
| 337 |
|
|
IF (dump_start > d_top) OR (d_top >= nwords) THEN
|
| 338 |
|
|
ASSERT FALSE
|
| 339 |
|
|
REPORT "Invalid addresses for memory dump. Cancelled."
|
| 340 |
|
|
SEVERITY ERROR;
|
| 341 |
|
|
ELSE
|
| 342 |
|
|
file_open(dest, dump_filename, READ_MODE);
|
| 343 |
|
|
FOR add IN dump_start TO d_top LOOP
|
| 344 |
|
|
write(l, add);
|
| 345 |
|
|
write(l, ' ');
|
| 346 |
|
|
FOR i IN D'range LOOP
|
| 347 |
|
|
write(l, memp.all(add)(i));
|
| 348 |
|
|
END LOOP;
|
| 349 |
|
|
writeline(dest, l);
|
| 350 |
|
|
END LOOP;
|
| 351 |
|
|
file_close(dest);
|
| 352 |
|
|
END IF;
|
| 353 |
|
|
END PROCEDURE do_dump;
|
| 354 |
|
|
|
| 355 |
|
|
-----------------------------------------------------------------------
|
| 356 |
|
|
-- Main process body
|
| 357 |
|
|
-----------------------------------------------------------------------
|
| 358 |
|
|
BEGIN
|
| 359 |
|
|
power_up(memp);
|
| 360 |
|
|
IF download_on_power_up THEN
|
| 361 |
|
|
load(memp, download_filename);
|
| 362 |
|
|
END IF;
|
| 363 |
|
|
LOOP -- Forever (see WAIT at the end)
|
| 364 |
|
|
IF do_write'EVENT and (do_write = '1') then -- End of write: latch in the data
|
| 365 |
|
|
IF NOT Check_For_Valid_Data(D) THEN
|
| 366 |
|
|
-- D'DELAYED crashes VSIM (Code 211): apparently 'DELAYED only works on a single signal,
|
| 367 |
|
|
-- not a vector (although it compiles OK.)
|
| 368 |
|
|
-- So delayed versions of D are explicitly created, & used for these checks.
|
| 369 |
|
|
IF D'EVENT AND Check_For_Valid_Data(DD1) THEN -- should be D'DELAYED
|
| 370 |
|
|
write(output, "-W- Data changes exactly at end-of-write to SRAM.");
|
| 371 |
|
|
write_data := DD1; -- should be D'delayed
|
| 372 |
|
|
ELSE
|
| 373 |
|
|
write(output, "-E- Data not valid at end-of-write to SRAM.");
|
| 374 |
|
|
write_data := undef_vec;
|
| 375 |
|
|
END IF;
|
| 376 |
|
|
ELSIF NOT DD2'STABLE(tSD_min) THEN -- should be D'DELAYED(tHD_min)
|
| 377 |
|
|
-- End of failing block
|
| 378 |
|
|
write(output, "-E- tSD violation: Data input changes within setup-time at end-of-write to SRAM.");
|
| 379 |
|
|
write_data := undef_vec;
|
| 380 |
|
|
ELSIF NOT D'STABLE(tHD_min) THEN
|
| 381 |
|
|
write(output, "-E- tHD violation: Data input changes within hold-time at end-of-write to SRAM.");
|
| 382 |
|
|
write_data := undef_vec;
|
| 383 |
|
|
ELSIF nWE'DELAYED(tHD_min)'STABLE(tPWE_min) THEN
|
| 384 |
|
|
write(output, "-E- tPWE violation: Pulse width of nWE too short at SRAM.");
|
| 385 |
|
|
write_data := undef_vec;
|
| 386 |
|
|
ELSE
|
| 387 |
|
|
write_data := D;
|
| 388 |
|
|
END IF;
|
| 389 |
|
|
memp.all(TO_INTEGER(unsigned(valid_adr))) := write_data;
|
| 390 |
|
|
END IF;
|
| 391 |
|
|
IF Check_For_Valid_Data(valid_adr) THEN
|
| 392 |
|
|
read_data <= memp.all(TO_INTEGER(unsigned(valid_adr)));
|
| 393 |
|
|
ELSE
|
| 394 |
|
|
read_data <= undef_vec;
|
| 395 |
|
|
END IF;
|
| 396 |
|
|
IF dump AND dump'EVENT THEN
|
| 397 |
|
|
do_dump(memp, dump_start, dump_end, dump_filename);
|
| 398 |
|
|
END IF;
|
| 399 |
|
|
IF download AND download'EVENT THEN
|
| 400 |
|
|
load(memp, download_filename);
|
| 401 |
|
|
END IF;
|
| 402 |
|
|
WAIT ON do_write, valid_adr, dump, download;
|
| 403 |
|
|
END LOOP;
|
| 404 |
|
|
END PROCESS memory;
|
| 405 |
|
|
|
| 406 |
|
|
-----------------------------------------------------------------------
|
| 407 |
|
|
-- Signal delays
|
| 408 |
|
|
-----------------------------------------------------------------------
|
| 409 |
|
|
adr_setup <= TRANSPORT A AFTER tAA_max;
|
| 410 |
|
|
adr_hold <= TRANSPORT A AFTER tOHA_min;
|
| 411 |
|
|
|
| 412 |
|
|
valid_adr <= adr_setup WHEN Check_For_Valid_Data(adr_setup)
|
| 413 |
|
|
AND (adr_setup = adr_hold)
|
| 414 |
|
|
AND adr_hold'STABLE(tAA_max - tOHA_min) ELSE
|
| 415 |
|
|
undef_adr_vec;
|
| 416 |
|
|
|
| 417 |
|
|
read_active <= ((nOE = '0') AND (nOE'DELAYED(tLZOE_min) = '0') AND nOE'STABLE(tLZOE_min)
|
| 418 |
|
|
AND ((nWE = '1') OR (nWE'DELAYED(tHZWE_max) = '0'))
|
| 419 |
|
|
AND (nCE = '0') AND (CE2 = '1') AND nCE'STABLE(tLZCE_min) AND CE2'STABLE(tLZCE_min))
|
| 420 |
|
|
OR (read_active AND (nOE'DELAYED(tHZOE_max) = '0')
|
| 421 |
|
|
AND (nWE'DELAYED(tHZWE_max) = '1')
|
| 422 |
|
|
AND (nCE'DELAYED(tHZCE_max) = '0') AND (CE2'DELAYED(tHZCE_max) = '1'));
|
| 423 |
|
|
|
| 424 |
|
|
read_valid <= ((nOE = '0') AND nOE'STABLE(tDOE_max)
|
| 425 |
|
|
AND (nWE = '1') AND (nWE'DELAYED(tHZWE_max) = '1')
|
| 426 |
|
|
AND (nCE = '0') AND (CE2 = '1') AND nCE'STABLE(tACE_max) AND CE2'STABLE(tACE_max))
|
| 427 |
|
|
OR (read_valid AND read_active);
|
| 428 |
|
|
|
| 429 |
|
|
Q <= read_data WHEN read_valid and read_active ELSE
|
| 430 |
|
|
undef_vec WHEN not read_valid and read_active ELSE
|
| 431 |
|
|
tristate_vec;
|
| 432 |
|
|
|
| 433 |
|
|
-----------------------------------------------------------------------
|
| 434 |
|
|
-- Decode write command
|
| 435 |
|
|
-----------------------------------------------------------------------
|
| 436 |
|
|
PROCESS (nWE, nCE, CE2)
|
| 437 |
|
|
BEGIN
|
| 438 |
|
|
IF ((nCE = '1') OR (nWE = '1') OR (CE2 = '0'))
|
| 439 |
|
|
AND (nCE'DELAYED = '0') AND (CE2'DELAYED = '1') AND (nWE'DELAYED = '0') -- End of Write
|
| 440 |
|
|
THEN
|
| 441 |
|
|
do_write <= '1' AFTER tHD_min;
|
| 442 |
|
|
ELSE
|
| 443 |
|
|
IF (Now > 10 NS) AND (nCE = '0') AND (CE2 = '1') AND (nWE = '0') -- Start of Write
|
| 444 |
|
|
THEN
|
| 445 |
|
|
ASSERT Check_For_Valid_Data(A)
|
| 446 |
|
|
REPORT "Address not valid at start-of-write to RAM."
|
| 447 |
|
|
SEVERITY FAILURE;
|
| 448 |
|
|
|
| 449 |
|
|
ASSERT A'STABLE(tSA_min)
|
| 450 |
|
|
REPORT "tSA violation: Address changed within setup-time at start-of-write to SRAM."
|
| 451 |
|
|
SEVERITY ERROR;
|
| 452 |
|
|
|
| 453 |
|
|
ASSERT enable_nWE_only_control OR ((nOE = '1') AND nOE'STABLE(tSA_min))
|
| 454 |
|
|
REPORT "tSA violation: nOE not inactive at start-of-write to RAM."
|
| 455 |
|
|
SEVERITY ERROR;
|
| 456 |
|
|
END IF;
|
| 457 |
|
|
do_write <= '0';
|
| 458 |
|
|
END IF;
|
| 459 |
|
|
END PROCESS;
|
| 460 |
|
|
|
| 461 |
|
|
-----------------------------------------------------------------------
|
| 462 |
|
|
-- The following processes check for validity of the control signals at the
|
| 463 |
|
|
-- SRAM interface. Removing them to speed up simulation will not affect the
|
| 464 |
|
|
-- functionality of the SRAM model.
|
| 465 |
|
|
-----------------------------------------------------------------------
|
| 466 |
|
|
-- Checks that an address change is allowed
|
| 467 |
|
|
-----------------------------------------------------------------------
|
| 468 |
|
|
PROCESS (A)
|
| 469 |
|
|
BEGIN
|
| 470 |
|
|
IF (Now > 0 NS) THEN -- suppress obsolete error message at time 0
|
| 471 |
|
|
ASSERT (nCE = '1') OR (CE2 = '0') OR (nWE = '1')
|
| 472 |
|
|
REPORT "Address not stable while write-to-SRAM active"
|
| 473 |
|
|
SEVERITY FAILURE;
|
| 474 |
|
|
|
| 475 |
|
|
ASSERT (nCE = '1') OR (CE2 = '0') OR (nWE = '1')
|
| 476 |
|
|
OR (nCE'DELAYED(tHA_min) = '1') OR (CE2'DELAYED(tHA_min) = '0')
|
| 477 |
|
|
OR (nWE'DELAYED(tHA_min) = '1')
|
| 478 |
|
|
REPORT "tHA violation: Address changed within hold-time at end-of-write to SRAM."
|
| 479 |
|
|
SEVERITY FAILURE;
|
| 480 |
|
|
END IF;
|
| 481 |
|
|
END PROCESS;
|
| 482 |
|
|
|
| 483 |
|
|
-----------------------------------------------------------------------
|
| 484 |
|
|
-- Checks that control signals at RAM are valid all the time
|
| 485 |
|
|
-----------------------------------------------------------------------
|
| 486 |
|
|
PROCESS (nOE, nWE, nCE, CE2)
|
| 487 |
|
|
BEGIN
|
| 488 |
|
|
IF (Now > 0 NS) AND (nCE /= '1') AND (CE2 /= '0') THEN
|
| 489 |
|
|
IF (nCE = '0') AND (CE2 = '1') THEN
|
| 490 |
|
|
ASSERT (nWE = '0') OR (nWE = '1')
|
| 491 |
|
|
REPORT "Invalid nWE-signal at SRAM while nCE is active"
|
| 492 |
|
|
SEVERITY WARNING;
|
| 493 |
|
|
ELSE
|
| 494 |
|
|
IF (nCE /= '0') THEN
|
| 495 |
|
|
ASSERT (nOE = '1')
|
| 496 |
|
|
REPORT "Invalid nCE-signal at SRAM while nOE not inactive"
|
| 497 |
|
|
SEVERITY WARNING;
|
| 498 |
|
|
|
| 499 |
|
|
ASSERT (nWE = '1')
|
| 500 |
|
|
REPORT "Invalid nCE-signal at SRAM while nWE not inactive"
|
| 501 |
|
|
SEVERITY ERROR;
|
| 502 |
|
|
END IF;
|
| 503 |
|
|
IF (CE2 /= '1') THEN
|
| 504 |
|
|
ASSERT (nOE = '1')
|
| 505 |
|
|
REPORT "Invalid CE2-signal at SRAM while nOE not inactive"
|
| 506 |
|
|
SEVERITY WARNING;
|
| 507 |
|
|
|
| 508 |
|
|
ASSERT (nWE = '1')
|
| 509 |
|
|
REPORT "Invalid CE2-signal at SRAM while nWE not inactive"
|
| 510 |
|
|
SEVERITY ERROR;
|
| 511 |
|
|
END IF;
|
| 512 |
|
|
END IF;
|
| 513 |
|
|
END IF;
|
| 514 |
|
|
END PROCESS;
|
| 515 |
|
|
|
| 516 |
|
|
END behavior;
|
