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1 13 david237 
-----------------------------------------------------------------------
2 
-- Bipolar TTL models (VHDL)                                         --
3 
-- David R Brooks                                                    --
4 
-- May, 2016.  Perth, Australia                                      --
5 
-- Compliance: VHDL 2008                                             --
6 
-- NB Simulation only: they are NOT synthesizable.                   --
7 
-- Based on: Fairchild TTL Data Book (see for pinouts)               --
8 
--           Signetics Low-Power Schottky Pocket Guide, 1978         --
9 
-- Part names are in Texas format, ie SN74LSxxN                      --
10 
-- The LS part is given when available, else the basic 74 part.      --
11 
-- Pinouts & naming agree with Altium libraries & VHDL netlister.    --
12 
-----------------------------------------------------------------------
13 
library ieee;
14 
    use ieee.std_logic_1164.all;
15 
 
16 
package LSTTL is
17 
 
18 
-----------------------------------------------------------------------
19 
-- SN74LS00N: Quad 2-input NAND gate (Pinout A)
20 
-----------------------------------------------------------------------
21 
component SN74LS00N is
22 
generic(
23 
    tPLH : time := 10 ns;
24 
    tPHL : time := 10 ns
25 
);
26 
port(
27 
    X_1  : in    std_logic;  -- 1A
28 
    X_2  : in    std_logic;  -- 1B
29 
    X_3  : out   std_logic;  -- 1Y\
30 
    X_4  : in    std_logic;  -- 2A
31 
    X_5  : in    std_logic;  -- 2B
32 
    X_6  : out   std_logic;  -- 2Y\
33 
    X_7  : inout std_logic;  -- GND
34 
    X_8  : out   std_logic;  -- 3Y\
35 
    X_9  : in    std_logic;  -- 3B
36 
    X_10 : in    std_logic;  -- 3A
37 
    X_11 : out   std_logic;  -- 4Y\
38 
    X_12 : in    std_logic;  -- 4B
39 
    X_13 : in    std_logic;  -- 4A
40 
    X_14 : inout std_logic   -- Vcc
41 
);
42 
end component SN74LS00N;
43 
 
44 
-----------------------------------------------------------------------
45 
-- SN7401N: Quad 2-input NAND gate (open collector) (Pinout A)
46 
-----------------------------------------------------------------------
47 
component SN7401N is
48 
generic(
49 
    tPLH : time := 15 ns;
50 
    tPHL : time := 15 ns
51 
);
52 
port(
53 
    X_1  : out   std_logic;  -- 1Y\
54 
    X_2  : in    std_logic;  -- 1A
55 
    X_3  : in    std_logic;  -- 1B
56 
    X_4  : out   std_logic;  -- 2Y\
57 
    X_5  : in    std_logic;  -- 2A
58 
    X_6  : in    std_logic;  -- 2B
59 
    X_7  : inout std_logic;  -- GND
60 
    X_8  : in    std_logic;  -- 3B
61 
    X_9  : in    std_logic;  -- 3A
62 
    X_10 : out   std_logic;  -- 3Y\
63 
    X_11 : in    std_logic;  -- 4B
64 
    X_12 : in    std_logic;  -- 4A
65 
    X_13 : out   std_logic;  -- 4Y\
66 
    X_14 : inout std_logic   -- Vcc
67 
);
68 
end component SN7401N;
69 
 
70 
-----------------------------------------------------------------------
71 
-- SN74LS02N: Quad 2-input NOR gate (Pinout A)
72 
-----------------------------------------------------------------------
73 
component SN74LS02N is
74 
generic(
75 
    tPLH : time := 15 ns;
76 
    tPHL : time := 15 ns
77 
);
78 
port(
79 
    X_1  : out   std_logic;  -- 1Y\
80 
    X_2  : in    std_logic;  -- 1A
81 
    X_3  : in    std_logic;  -- 1B
82 
    X_4  : out   std_logic;  -- 2Y\
83 
    X_5  : in    std_logic;  -- 2A
84 
    X_6  : in    std_logic;  -- 2B
85 
    X_7  : inout std_logic;  -- GND
86 
    X_8  : in    std_logic;  -- 3B
87 
    X_9  : in    std_logic;  -- 3A
88 
    X_10 : out   std_logic;  -- 3Y\
89 
    X_11 : in    std_logic;  -- 4B
90 
    X_12 : in    std_logic;  -- 4A
91 
    X_13 : out   std_logic;  -- 4Y\
92 
    X_14 : inout std_logic   -- Vcc
93 
);
94 
end component SN74LS02N;
95 
 
96 
-----------------------------------------------------------------------
97 
-- SN74LS03N: Quad 2-input NAND gate (open collector)
98 
-----------------------------------------------------------------------
99 
component SN74LS03N is
100 
generic(
101 
    tPLH : time := 22 ns;
102 
    tPHL : time := 18 ns
103 
);
104 
port(
105 
    X_1  : in    std_logic;  -- 1A
106 
    X_2  : in    std_logic;  -- 1B
107 
    X_3  : out   std_logic;  -- 1Y\
108 
    X_4  : in    std_logic;  -- 2A
109 
    X_5  : in    std_logic;  -- 2B
110 
    X_6  : out   std_logic;  -- 2Y\
111 
    X_7  : inout std_logic;  -- GND
112 
    X_8  : out   std_logic;  -- 3Y\
113 
    X_9  : in    std_logic;  -- 3B
114 
    X_10 : in    std_logic;  -- 3A
115 
    X_11 : out   std_logic;  -- 4Y\
116 
    X_12 : in    std_logic;  -- 4B
117 
    X_13 : in    std_logic;  -- 4A
118 
    X_14 : inout std_logic   -- Vcc
119 
);
120 
end component SN74LS03N;
121 
 
122 
-----------------------------------------------------------------------
123 
-- SN74LS04N: Hex inverter (Pinout A)
124 
-----------------------------------------------------------------------
125 
component SN74LS04N is
126 
generic(
127 
    tPLH : time := 10 ns;
128 
    tPHL : time := 10 ns
129 
);
130 
port(
131 
    X_1  : in    std_logic;  -- 1A
132 
    X_2  : out   std_logic;  -- 1Y\
133 
    X_3  : in    std_logic;  -- 2A
134 
    X_4  : out   std_logic;  -- 2Y\
135 
    X_5  : in    std_logic;  -- 3A
136 
    X_6  : out   std_logic;  -- 3Y\
137 
    X_7  : inout std_logic;  -- GND
138 
    X_8  : out   std_logic;  -- 4Y\
139 
    X_9  : in    std_logic;  -- 4A
140 
    X_10 : out   std_logic;  -- 5Y\
141 
    X_11 : in    std_logic;  -- 5A
142 
    X_12 : out   std_logic;  -- 6Y\
143 
    X_13 : in    std_logic;  -- 6A
144 
    X_14 : inout std_logic   -- Vcc
145 
);
146 
end component SN74LS04N;
147 
 
148 
-----------------------------------------------------------------------
149 
-- SN74LS05N: Hex inverter (open collector) (Pinout A)
150 
-----------------------------------------------------------------------
151 
component SN74LS05N is
152 
generic(
153 
    tPLH : time := 32 ns;
154 
    tPHL : time := 28 ns
155 
);
156 
port(
157 
    X_1  : in    std_logic;  -- 1A
158 
    X_2  : out   std_logic;  -- 1Y\
159 
    X_3  : in    std_logic;  -- 2A
160 
    X_4  : out   std_logic;  -- 2Y\
161 
    X_5  : in    std_logic;  -- 3A
162 
    X_6  : out   std_logic;  -- 3Y\
163 
    X_7  : inout std_logic;  -- GND
164 
    X_8  : out   std_logic;  -- 4Y\
165 
    X_9  : in    std_logic;  -- 4A
166 
    X_10 : out   std_logic;  -- 5Y\
167 
    X_11 : in    std_logic;  -- 5A
168 
    X_12 : out   std_logic;  -- 6Y\
169 
    X_13 : in    std_logic;  -- 6A
170 
    X_14 : inout std_logic   -- Vcc
171 
);
172 
end component SN74LS05N;
173 
 
174 
-----------------------------------------------------------------------
175 
-- SN7406N: Hex inverter (high voltage open collector)
176 
-----------------------------------------------------------------------
177 
component SN7406N is
178 
generic(
179 
    tPLH : time := 15 ns;
180 
    tPHL : time := 23 ns
181 
);
182 
port(
183 
    X_1  : in    std_logic;  -- 1A
184 
    X_2  : out   std_logic;  -- 1Y\
185 
    X_3  : in    std_logic;  -- 2A
186 
    X_4  : out   std_logic;  -- 2Y\
187 
    X_5  : in    std_logic;  -- 3A
188 
    X_6  : out   std_logic;  -- 3Y\
189 
    X_7  : inout std_logic;  -- GND
190 
    X_8  : out   std_logic;  -- 4Y\
191 
    X_9  : in    std_logic;  -- 4A
192 
    X_10 : out   std_logic;  -- 5Y\
193 
    X_11 : in    std_logic;  -- 5A
194 
    X_12 : out   std_logic;  -- 6Y\
195 
    X_13 : in    std_logic;  -- 6A
196 
    X_14 : inout std_logic   -- Vcc
197 
);
198 
end component SN7406N;
199 
 
200 
-----------------------------------------------------------------------
201 
-- SN7407N: Hex buffer (high voltage open collector)
202 
-----------------------------------------------------------------------
203 
component SN7407N is
204 
generic(
205 
    tPLH : time := 10 ns;
206 
    tPHL : time := 30 ns
207 
);
208 
port(
209 
    X_1  : in    std_logic;  -- 1A
210 
    X_2  : out   std_logic;  -- 1Y\
211 
    X_3  : in    std_logic;  -- 2A
212 
    X_4  : out   std_logic;  -- 2Y\
213 
    X_5  : in    std_logic;  -- 3A
214 
    X_6  : out   std_logic;  -- 3Y\
215 
    X_7  : inout std_logic;  -- GND
216 
    X_8  : out   std_logic;  -- 4Y\
217 
    X_9  : in    std_logic;  -- 4A
218 
    X_10 : out   std_logic;  -- 5Y\
219 
    X_11 : in    std_logic;  -- 5A
220 
    X_12 : out   std_logic;  -- 6Y\
221 
    X_13 : in    std_logic;  -- 6A
222 
    X_14 : inout std_logic   -- Vcc
223 
);
224 
end component SN7407N;
225 
 
226 
-----------------------------------------------------------------------
227 
-- SN74LS08N: Quad 2-input AND gate (Pinout A)
228 
-----------------------------------------------------------------------
229 
component SN74LS08N is
230 
port(
231 
    X_1  : in    std_logic;  -- 1A
232 
    X_2  : in    std_logic;  -- 1B
233 
    X_3  : out   std_logic;  -- 1Y
234 
    X_4  : in    std_logic;  -- 2A
235 
    X_5  : in    std_logic;  -- 2B
236 
    X_6  : out   std_logic;  -- 2Y
237 
    X_7  : inout std_logic;  -- GND
238 
    X_8  : out   std_logic;  -- 3Y
239 
    X_9  : in    std_logic;  -- 3B
240 
    X_10 : in    std_logic;  -- 3A
241 
    X_11 : out   std_logic;  -- 4Y
242 
    X_12 : in    std_logic;  -- 4B
243 
    X_13 : in    std_logic;  -- 4A
244 
    X_14 : inout std_logic   -- Vcc
245 
);
246 
end component SN74LS08N;
247 
 
248 
-----------------------------------------------------------------------
249 
-- SN74LS09N: Quad 2-input AND gate (open collector)
250 
-----------------------------------------------------------------------
251 
component SN74LS09N is
252 
port(
253 
    X_1  : in    std_logic;  -- 1A
254 
    X_2  : in    std_logic;  -- 1B
255 
    X_3  : out   std_logic;  -- 1Y
256 
    X_4  : in    std_logic;  -- 2A
257 
    X_5  : in    std_logic;  -- 2B
258 
    X_6  : out   std_logic;  -- 2Y
259 
    X_7  : inout std_logic;  -- GND
260 
    X_8  : out   std_logic;  -- 3Y
261 
    X_9  : in    std_logic;  -- 3B
262 
    X_10 : in    std_logic;  -- 3A
263 
    X_11 : out   std_logic;  -- 4Y
264 
    X_12 : in    std_logic;  -- 4B
265 
    X_13 : in    std_logic;  -- 4A
266 
    X_14 : inout std_logic   -- Vcc
267 
);
268 
end component SN74LS09N;
269 
 
270 
-----------------------------------------------------------------------
271 
-- SN74LS10N: Triple 3-input NAND gate (Pinout A)
272 
-----------------------------------------------------------------------
273 
component SN74LS10N is
274 
generic(
275 
    tPLH : time := 15 ns;
276 
    tPHL : time := 15 ns
277 
);
278 
port(
279 
    X_1  : in    std_logic;  -- 1A
280 
    X_2  : in    std_logic;  -- 1B
281 
    X_3  : in    std_logic;  -- 2A
282 
    X_4  : in    std_logic;  -- 2B
283 
    X_5  : in    std_logic;  -- 2C
284 
    X_6  : out   std_logic;  -- 2Y\
285 
    X_7  : inout std_logic;  -- GND
286 
    X_8  : out   std_logic;  -- 3Y\
287 
    X_9  : in    std_logic;  -- 3C
288 
    X_10 : in    std_logic;  -- 3B
289 
    X_11 : in    std_logic;  -- 3A
290 
    X_12 : out   std_logic;  -- 1Y\
291 
    X_13 : in    std_logic;  -- 1C
292 
    X_14 : inout std_logic   -- Vcc
293 
);
294 
end component SN74LS10N;
295 
 
296 
-----------------------------------------------------------------------
297 
-- SN74LS11N: Triple 3-input AND gate (Pinout A)
298 
-----------------------------------------------------------------------
299 
component SN74LS11N is
300 
generic(
301 
    tPLH : time := 15 ns;
302 
    tPHL : time := 20 ns
303 
);
304 
port(
305 
    X_1  : in    std_logic;  -- 1A
306 
    X_2  : in    std_logic;  -- 1B
307 
    X_3  : in    std_logic;  -- 2A
308 
    X_4  : in    std_logic;  -- 2B
309 
    X_5  : in    std_logic;  -- 2C
310 
    X_6  : out   std_logic;  -- 2Y\
311 
    X_7  : inout std_logic;  -- GND
312 
    X_8  : out   std_logic;  -- 3Y\
313 
    X_9  : in    std_logic;  -- 3C
314 
    X_10 : in    std_logic;  -- 3B
315 
    X_11 : in    std_logic;  -- 3A
316 
    X_12 : out   std_logic;  -- 1Y\
317 
    X_13 : in    std_logic;  -- 1C
318 
    X_14 : inout std_logic   -- Vcc
319 
);
320 
end component SN74LS11N;
321 
 
322 
-----------------------------------------------------------------------
323 
-- SN74LS12N: Triple 3-input NAND gate (open collector)
324 
-----------------------------------------------------------------------
325 
component SN74LS12N is
326 
generic(
327 
    tPLH : time := 32 ns;
328 
    tPHL : time := 28 ns
329 
);
330 
port(
331 
    X_1  : in    std_logic;  -- 1A
332 
    X_2  : in    std_logic;  -- 1B
333 
    X_3  : in    std_logic;  -- 2A
334 
    X_4  : in    std_logic;  -- 2B
335 
    X_5  : in    std_logic;  -- 2C
336 
    X_6  : out   std_logic;  -- 2Y\
337 
    X_7  : inout std_logic;  -- GND
338 
    X_8  : out   std_logic;  -- 3Y\
339 
    X_9  : in    std_logic;  -- 3C
340 
    X_10 : in    std_logic;  -- 3B
341 
    X_11 : in    std_logic;  -- 3A
342 
    X_12 : out   std_logic;  -- 1Y\
343 
    X_13 : in    std_logic;  -- 1C
344 
    X_14 : inout std_logic   -- Vcc
345 
);
346 
end component SN74LS12N;
347 
 
348 
-----------------------------------------------------------------------
349 
-- SN74LS13N: Dual 4-input NAND Schmitt trigger
350 
-----------------------------------------------------------------------
351 
component SN74LS13N is
352 
generic(
353 
    tPLH : time := 22 ns;
354 
    tPHL : time := 27 ns
355 
);
356 
port(
357 
    X_1  : in    std_logic;  -- 1A
358 
    X_2  : in    std_logic;  -- 1B
359 
                             --
360 
    X_4  : in    std_logic;  -- 1C
361 
    X_5  : in    std_logic;  -- 1D
362 
    X_6  : out   std_logic;  -- 1Y\
363 
    X_7  : inout std_logic;  -- GND
364 
    X_8  : out   std_logic;  -- 2Y\
365 
    X_9  : in    std_logic;  -- 2D
366 
    X_10 : in    std_logic;  -- 2C
367 
                             --
368 
    X_12 : in    std_logic;  -- 2B
369 
    X_13 : in    std_logic;  -- 2A
370 
    X_14 : inout std_logic   -- Vcc
371 
);
372 
end component SN74LS13N;
373 
 
374 
-----------------------------------------------------------------------
375 
-- SN74LS14N: Hex Schmitt trigger inverter
376 
-----------------------------------------------------------------------
377 
component SN74LS14N is
378 
generic(
379 
    tPLH : time := 22 ns;
380 
    tPHL : time := 22 ns
381 
);
382 
port(
383 
    X_1  : in    std_logic;  -- 1A
384 
    X_2  : out   std_logic;  -- 1Y\
385 
    X_3  : in    std_logic;  -- 2A
386 
    X_4  : out   std_logic;  -- 2Y\
387 
    X_5  : in    std_logic;  -- 3A
388 
    X_6  : out   std_logic;  -- 3Y\
389 
    X_7  : inout std_logic;  -- GND
390 
    X_8  : out   std_logic;  -- 4Y\
391 
    X_9  : in    std_logic;  -- 4A
392 
    X_10 : out   std_logic;  -- 5Y\
393 
    X_11 : in    std_logic;  -- 5A
394 
    X_12 : out   std_logic;  -- 6Y\
395 
    X_13 : in    std_logic;  -- 6A
396 
    X_14 : inout std_logic   -- Vcc
397 
);
398 
end component SN74LS14N;
399 
 
400 
-----------------------------------------------------------------------
401 
-- SN74LS15N: Triple 3-input AND gate (open collector)
402 
-----------------------------------------------------------------------
403 
component SN74LS15N is
404 
generic(
405 
    tPLH : time := 35 ns;
406 
    tPHL : time := 35 ns
407 
);
408 
port(
409 
    X_1  : in    std_logic;  -- 1A
410 
    X_2  : in    std_logic;  -- 1B
411 
    X_3  : in    std_logic;  -- 2A
412 
    X_4  : in    std_logic;  -- 2B
413 
    X_5  : in    std_logic;  -- 2C
414 
    X_6  : out   std_logic;  -- 2Y\
415 
    X_7  : inout std_logic;  -- GND
416 
    X_8  : out   std_logic;  -- 3Y\
417 
    X_9  : in    std_logic;  -- 3C
418 
    X_10 : in    std_logic;  -- 3B
419 
    X_11 : in    std_logic;  -- 3A
420 
    X_12 : out   std_logic;  -- 1Y\
421 
    X_13 : in    std_logic;  -- 1C
422 
    X_14 : inout std_logic   -- Vcc
423 
);
424 
end component SN74LS15N;
425 
 
426 
-----------------------------------------------------------------------
427 
-- SN7416N: Hex inverter/driver (high voltage open collector)
428 
-----------------------------------------------------------------------
429 
component SN7416N is
430 
generic(
431 
    tPLH : time := 15 ns;
432 
    tPHL : time := 23 ns
433 
);
434 
port(
435 
    X_1  : in    std_logic;  -- 1A
436 
    X_2  : out   std_logic;  -- 1Y\
437 
    X_3  : in    std_logic;  -- 2A
438 
    X_4  : out   std_logic;  -- 2Y\
439 
    X_5  : in    std_logic;  -- 3A
440 
    X_6  : out   std_logic;  -- 3Y\
441 
    X_7  : inout std_logic;  -- GND
442 
    X_8  : out   std_logic;  -- 4Y\
443 
    X_9  : in    std_logic;  -- 4A
444 
    X_10 : out   std_logic;  -- 5Y\
445 
    X_11 : in    std_logic;  -- 5A
446 
    X_12 : out   std_logic;  -- 6Y\
447 
    X_13 : in    std_logic;  -- 6A
448 
    X_14 : inout std_logic   -- Vcc
449 
);
450 
end component SN7416N;
451 
 
452 
-----------------------------------------------------------------------
453 
-- SN7417N: Hex buffer/driver (high voltage open collector)
454 
-----------------------------------------------------------------------
455 
component SN7417N is
456 
generic(
457 
    tPLH : time := 10 ns;
458 
    tPHL : time := 30 ns
459 
);
460 
port(
461 
    X_1  : in    std_logic;  -- 1A
462 
    X_2  : out   std_logic;  -- 1Y\
463 
    X_3  : in    std_logic;  -- 2A
464 
    X_4  : out   std_logic;  -- 2Y\
465 
    X_5  : in    std_logic;  -- 3A
466 
    X_6  : out   std_logic;  -- 3Y\
467 
    X_7  : inout std_logic;  -- GND
468 
    X_8  : out   std_logic;  -- 4Y\
469 
    X_9  : in    std_logic;  -- 4A
470 
    X_10 : out   std_logic;  -- 5Y\
471 
    X_11 : in    std_logic;  -- 5A
472 
    X_12 : out   std_logic;  -- 6Y\
473 
    X_13 : in    std_logic;  -- 6A
474 
    X_14 : inout std_logic   -- Vcc
475 
);
476 
end component SN7417N;
477 
 
478 
-- SN74LS19AN: Schmitt trigger inverters
479 
 
480 
-----------------------------------------------------------------------
481 
-- SN74LS20N: Dual 4-input NAND gate (Pinout A)
482 
-----------------------------------------------------------------------
483 
component SN74LS20N is
484 
generic(
485 
    tPLH : time := 15 ns;
486 
    tPHL : time := 15 ns
487 
);
488 
port(
489 
    X_1  : in    std_logic;  -- 1A
490 
    X_2  : in    std_logic;  -- 1B
491 
                             --
492 
    X_4  : in    std_logic;  -- 1C
493 
    X_5  : in    std_logic;  -- 1D
494 
    X_6  : out   std_logic;  -- 1Y\
495 
    X_7  : inout std_logic;  -- GND
496 
    X_8  : out   std_logic;  -- 2Y\
497 
    X_9  : in    std_logic;  -- 2D
498 
    X_10 : in    std_logic;  -- 2C
499 
                             --
500 
    X_12 : in    std_logic;  -- 2B
501 
    X_13 : in    std_logic;  -- 2A
502 
    X_14 : inout std_logic   -- Vcc
503 
);
504 
end component SN74LS20N;
505 
 
506 
-----------------------------------------------------------------------
507 
-- SN74LS21N: Dual 4-input AND gate (Pinout A)
508 
-----------------------------------------------------------------------
509 
component SN74LS21N is
510 
generic(
511 
    tPLH : time := 15 ns;
512 
    tPHL : time := 20 ns
513 
);
514 
port(
515 
    X_1  : in    std_logic;  -- 1A
516 
    X_2  : in    std_logic;  -- 1B
517 
                             --
518 
    X_4  : in    std_logic;  -- 1C
519 
    X_5  : in    std_logic;  -- 1D
520 
    X_6  : out   std_logic;  -- 1Y\
521 
    X_7  : inout std_logic;  -- GND
522 
    X_8  : out   std_logic;  -- 2Y\
523 
    X_9  : in    std_logic;  -- 2D
524 
    X_10 : in    std_logic;  -- 2C
525 
                             --
526 
    X_12 : in    std_logic;  -- 2B
527 
    X_13 : in    std_logic;  -- 2A
528 
    X_14 : inout std_logic   -- Vcc
529 
);
530 
end component SN74LS21N;
531 
 
532 
-----------------------------------------------------------------------
533 
-- SN74LS22N: Dual 4-input NAND gate (open collector) (Pinout A)
534 
-----------------------------------------------------------------------
535 
component SN74LS22N is
536 
generic(
537 
    tPLH : time := 22 ns;
538 
    tPHL : time := 18 ns
539 
);
540 
port(
541 
    X_1  : in    std_logic;  -- 1A
542 
    X_2  : in    std_logic;  -- 1B
543 
                             --
544 
    X_4  : in    std_logic;  -- 1C
545 
    X_5  : in    std_logic;  -- 1D
546 
    X_6  : out   std_logic;  -- 1Y\
547 
    X_7  : inout std_logic;  -- GND
548 
    X_8  : out   std_logic;  -- 2Y\
549 
    X_9  : in    std_logic;  -- 2D
550 
    X_10 : in    std_logic;  -- 2C
551 
                             --
552 
    X_12 : in    std_logic;  -- 2B
553 
    X_13 : in    std_logic;  -- 2A
554 
    X_14 : inout std_logic   -- Vcc
555 
);
556 
end component SN74LS22N;
557 
 
558 
-- SN74LS24AN: Schmitt trigger positive NAND gates
559 
-- SN7425N: Dual 4-input NOR gate (with strobe)
560 
 
561 
-----------------------------------------------------------------------
562 
-- SN74LS26N: Quad 2-input NAND buffer (open collector)
563 
-----------------------------------------------------------------------
564 
component SN74LS26N is
565 
port(
566 
    X_1  : in    std_logic;  -- 1A
567 
    X_2  : in    std_logic;  -- 1B
568 
    X_3  : out   std_logic;  -- 1Y\
569 
    X_4  : in    std_logic;  -- 2A
570 
    X_5  : in    std_logic;  -- 2B
571 
    X_6  : out   std_logic;  -- 2Y\
572 
    X_7  : inout std_logic;  -- GND
573 
    X_8  : out   std_logic;  -- 3Y\
574 
    X_9  : in    std_logic;  -- 3B
575 
    X_10 : in    std_logic;  -- 3A
576 
    X_11 : out   std_logic;  -- 4Y\
577 
    X_12 : in    std_logic;  -- 4B
578 
    X_13 : in    std_logic;  -- 4A
579 
    X_14 : inout std_logic   -- Vcc
580 
);
581 
end component SN74LS26N;
582 
 
583 
-----------------------------------------------------------------------
584 
-- SN74LS27N: Triple 3-input NOR gate
585 
-----------------------------------------------------------------------
586 
component SN74LS27N is
587 
generic(
588 
    tPLH : time := 13 ns;
589 
    tPHL : time := 13 ns
590 
);
591 
port(
592 
    X_1  : in    std_logic;  -- 1A
593 
    X_2  : in    std_logic;  -- 1B
594 
    X_3  : in    std_logic;  -- 2A
595 
    X_4  : in    std_logic;  -- 2B
596 
    X_5  : in    std_logic;  -- 2C
597 
    X_6  : out   std_logic;  -- 2Y\
598 
    X_7  : inout std_logic;  -- GND
599 
    X_8  : out   std_logic;  -- 3Y\
600 
    X_9  : in    std_logic;  -- 3C
601 
    X_10 : in    std_logic;  -- 3B
602 
    X_11 : in    std_logic;  -- 3A
603 
    X_12 : out   std_logic;  -- 1Y\
604 
    X_13 : in    std_logic;  -- 1C
605 
    X_14 : inout std_logic   -- Vcc
606 
);
607 
end component SN74LS27N;
608 
 
609 
-----------------------------------------------------------------------
610 
-- SN74LS28N: Quad 2-input NOR buffer
611 
-----------------------------------------------------------------------
612 
component SN74LS28N is
613 
generic(
614 
    tPLH : time := 20 ns;
615 
    tPHL : time := 20 ns
616 
);
617 
port(
618 
    X_1  : out   std_logic;  -- 1Y\
619 
    X_2  : in    std_logic;  -- 1A
620 
    X_3  : in    std_logic;  -- 1B
621 
    X_4  : out   std_logic;  -- 2Y\
622 
    X_5  : in    std_logic;  -- 2A
623 
    X_6  : in    std_logic;  -- 2B
624 
    X_7  : inout std_logic;  -- GND
625 
    X_8  : in    std_logic;  -- 3B
626 
    X_9  : in    std_logic;  -- 3A
627 
    X_10 : out   std_logic;  -- 3Y\
628 
    X_11 : in    std_logic;  -- 4B
629 
    X_12 : in    std_logic;  -- 4A
630 
    X_13 : out   std_logic;  -- 4Y\
631 
    X_14 : inout std_logic   -- Vcc
632 
);
633 
end component SN74LS28N;
634 
 
635 
-----------------------------------------------------------------------
636 
-- SN74LS30N: 8-input NAND gate (Pinout A)
637 
-----------------------------------------------------------------------
638 
component SN74LS30N is
639 
generic(
640 
    tPLH : time := 15 ns;
641 
    tPHL : time := 20 ns
642 
);
643 
port(
644 
    X_1  : in    std_logic;  -- 1A
645 
    X_2  : in    std_logic;  -- 1B
646 
    X_3  : in    std_logic;  -- 1C
647 
    X_4  : in    std_logic;  -- 1D
648 
    X_5  : in    std_logic;  -- 1E
649 
    X_6  : in    std_logic;  -- 1F
650 
    X_7  : inout std_logic;  -- GND
651 
    X_8  : out   std_logic;  -- 1Y\
652 
                             --
653 
                             --
654 
    X_11 : in    std_logic;  -- 1G
655 
    X_12 : in    std_logic;  -- 1H
656 
                             --
657 
    X_14 : inout std_logic   -- Vcc
658 
);
659 
end component SN74LS30N;
660 
 
661 
-- SN74LS31N: delay element
662 
 
663 
-----------------------------------------------------------------------
664 
-- SN74LS32N: Quad 2-input OR gate
665 
-----------------------------------------------------------------------
666 
component SN74LS32N is
667 
port(
668 
    X_1  : in    std_logic;  -- 1A
669 
    X_2  : in    std_logic;  -- 1B
670 
    X_3  : out   std_logic;  -- 1Y
671 
    X_4  : in    std_logic;  -- 2A
672 
    X_5  : in    std_logic;  -- 2B
673 
    X_6  : out   std_logic;  -- 2Y
674 
    X_7  : inout std_logic;  -- GND
675 
    X_8  : out   std_logic;  -- 3Y
676 
    X_9  : in    std_logic;  -- 3B
677 
    X_10 : in    std_logic;  -- 3A
678 
    X_11 : out   std_logic;  -- 4Y
679 
    X_12 : in    std_logic;  -- 4B
680 
    X_13 : in    std_logic;  -- 4A
681 
    X_14 : inout std_logic   -- Vcc
682 
);
683 
end component SN74LS32N;
684 
 
685 
-----------------------------------------------------------------------
686 
-- SN74LS33N: Quad 2-input NOR buffer (open collector)
687 
-----------------------------------------------------------------------
688 
component SN74LS33N is
689 
generic(
690 
    tPLH : time := 32 ns;
691 
    tPHL : time := 28 ns
692 
);
693 
port(
694 
    X_1  : out   std_logic;  -- 1Y\
695 
    X_2  : in    std_logic;  -- 1A
696 
    X_3  : in    std_logic;  -- 1B
697 
    X_4  : out   std_logic;  -- 2Y\
698 
    X_5  : in    std_logic;  -- 2A
699 
    X_6  : in    std_logic;  -- 2B
700 
    X_7  : inout std_logic;  -- GND
701 
    X_8  : in    std_logic;  -- 3B
702 
    X_9  : in    std_logic;  -- 3A
703 
    X_10 : out   std_logic;  -- 3Y\
704 
    X_11 : in    std_logic;  -- 4B
705 
    X_12 : in    std_logic;  -- 4A
706 
    X_13 : out   std_logic;  -- 4Y\
707 
    X_14 : inout std_logic   -- Vcc
708 
);
709 
end component SN74LS33N;
710 
 
711 
-----------------------------------------------------------------------
712 
-- SN74LS37N: Quad 2-input NAND buffer
713 
-----------------------------------------------------------------------
714 
component SN74LS37N is
715 
port(
716 
    X_1  : in    std_logic;  -- 1A
717 
    X_2  : in    std_logic;  -- 1B
718 
    X_3  : out   std_logic;  -- 1Y\
719 
    X_4  : in    std_logic;  -- 2A
720 
    X_5  : in    std_logic;  -- 2B
721 
    X_6  : out   std_logic;  -- 2Y\
722 
    X_7  : inout std_logic;  -- GND
723 
    X_8  : out   std_logic;  -- 3Y\
724 
    X_9  : in    std_logic;  -- 3B
725 
    X_10 : in    std_logic;  -- 3A
726 
    X_11 : out   std_logic;  -- 4Y\
727 
    X_12 : in    std_logic;  -- 4B
728 
    X_13 : in    std_logic;  -- 4A
729 
    X_14 : inout std_logic   -- Vcc
730 
);
731 
end component SN74LS37N;
732 
 
733 
-----------------------------------------------------------------------
734 
-- SN74LS38N: Quad 2-input NAND buffer (open collector)
735 
-----------------------------------------------------------------------
736 
component SN74LS38N is
737 
port(
738 
    X_1  : in    std_logic;  -- 1A
739 
    X_2  : in    std_logic;  -- 1B
740 
    X_3  : out   std_logic;  -- 1Y\
741 
    X_4  : in    std_logic;  -- 2A
742 
    X_5  : in    std_logic;  -- 2B
743 
    X_6  : out   std_logic;  -- 2Y\
744 
    X_7  : inout std_logic;  -- GND
745 
    X_8  : out   std_logic;  -- 3Y\
746 
    X_9  : in    std_logic;  -- 3B
747 
    X_10 : in    std_logic;  -- 3A
748 
    X_11 : out   std_logic;  -- 4Y\
749 
    X_12 : in    std_logic;  -- 4B
750 
    X_13 : in    std_logic;  -- 4A
751 
    X_14 : inout std_logic   -- Vcc
752 
);
753 
end component SN74LS38N;
754 
 
755 
-----------------------------------------------------------------------
756 
-- SN74LS39N: Quad 2-input NAND buffer (open collector) (Pinout A)
757 
-----------------------------------------------------------------------
758 
component SN74LS39N is
759 
generic(
760 
    tPLH : time := 22 ns;
761 
    tPHL : time := 18 ns
762 
);
763 
port(
764 
    X_1  : out   std_logic;  -- 1Y\
765 
    X_2  : in    std_logic;  -- 1A
766 
    X_3  : in    std_logic;  -- 1B
767 
    X_4  : out   std_logic;  -- 2Y\
768 
    X_5  : in    std_logic;  -- 2A
769 
    X_6  : in    std_logic;  -- 2B
770 
    X_7  : inout std_logic;  -- GND
771 
    X_8  : in    std_logic;  -- 3B
772 
    X_9  : in    std_logic;  -- 3A
773 
    X_10 : out   std_logic;  -- 3Y\
774 
    X_11 : in    std_logic;  -- 4B
775 
    X_12 : in    std_logic;  -- 4A
776 
    X_13 : out   std_logic;  -- 4Y\
777 
    X_14 : inout std_logic   -- Vcc
778 
);
779 
end component SN74LS39N;
780 
 
781 
-----------------------------------------------------------------------
782 
-- SN74LS40N: Dual 4-input NAND buffer (Pinout A)
783 
-----------------------------------------------------------------------
784 
component SN74LS40N is
785 
generic(
786 
    tPLH : time := 24 ns;
787 
    tPHL : time := 24 ns
788 
);
789 
port(
790 
    X_1  : in    std_logic;  -- 1A
791 
    X_2  : in    std_logic;  -- 1B
792 
                             --
793 
    X_4  : in    std_logic;  -- 1C
794 
    X_5  : in    std_logic;  -- 1D
795 
    X_6  : out   std_logic;  -- 1Y\
796 
    X_7  : inout std_logic;  -- GND
797 
    X_8  : out   std_logic;  -- 2Y\
798 
    X_9  : in    std_logic;  -- 2D
799 
    X_10 : in    std_logic;  -- 2C
800 
                             --
801 
    X_12 : in    std_logic;  -- 2B
802 
    X_13 : in    std_logic;  -- 2A
803 
    X_14 : inout std_logic   -- Vcc
804 
);
805 
end component SN74LS40N;
806 
 
807 
-----------------------------------------------------------------------
808 
-- SN74LS42N: 1-of-10 decoder
809 
-----------------------------------------------------------------------
810 
component SN74LS42N is
811 
generic(
812 
    tPLH : time := 20 ns;
813 
    tPHL : time := 27 ns
814 
);
815 
port(
816 
    X_1  : out   std_logic;  -- Q0\
817 
    X_2  : out   std_logic;  -- Q1\
818 
    X_3  : out   std_logic;  -- Q2\
819 
    X_4  : out   std_logic;  -- Q3\
820 
    X_5  : out   std_logic;  -- Q4\
821 
    X_6  : out   std_logic;  -- Q5\
822 
    X_7  : out   std_logic;  -- Q6\
823 
    X_8  : inout std_logic;  -- GND
824 
    X_9  : out   std_logic;  -- Q7\
825 
    X_10 : out   std_logic;  -- Q8\
826 
    X_11 : out   std_logic;  -- Q9\
827 
    X_12 : in    std_logic;  -- A3
828 
    X_13 : in    std_logic;  -- A2
829 
    X_14 : in    std_logic;  -- A1
830 
    X_15 : in    std_logic;  -- A0
831 
    X_16 : inout std_logic   -- Vcc
832 
);
833 
end component SN74LS42N;
834 
 
835 
-----------------------------------------------------------------------
836 
-- SN7445N: 1-of-10 decoder/driver (open collector)
837 
-----------------------------------------------------------------------
838 
component SN7445N is
839 
generic(
840 
    tPLH : time := 50 ns;
841 
    tPHL : time := 50 ns
842 
);
843 
port(
844 
    X_1  : out   std_logic;  -- Q0\
845 
    X_2  : out   std_logic;  -- Q1\
846 
    X_3  : out   std_logic;  -- Q2\
847 
    X_4  : out   std_logic;  -- Q3\
848 
    X_5  : out   std_logic;  -- Q4\
849 
    X_6  : out   std_logic;  -- Q5\
850 
    X_7  : out   std_logic;  -- Q6\
851 
    X_8  : inout std_logic;  -- GND
852 
    X_9  : out   std_logic;  -- Q7\
853 
    X_10 : out   std_logic;  -- Q8\
854 
    X_11 : out   std_logic;  -- Q9\
855 
    X_12 : in    std_logic;  -- A3
856 
    X_13 : in    std_logic;  -- A2
857 
    X_14 : in    std_logic;  -- A1
858 
    X_15 : in    std_logic;  -- A0
859 
    X_16 : inout std_logic   -- Vcc
860 
);
861 
end component SN7445N;
862 
 
863 
-- SN74LS47N: BCD to 7-segment decoder/driver
864 
-- SN74LS48N: BCD to 7-segment decoder
865 
-- SN74LS49N: BCD to 7-segment decoder
866 
-- SN7450P: Expandable dual 2-wide 2-input and-or-invert gate
867 
 
868 
-----------------------------------------------------------------------
869 
-- SN74LS51N: Dual 2-wide, 2/3-input AND-OR-Invert gate (Pinout B)
870 
-----------------------------------------------------------------------
871 
component SN74LS51N is
872 
generic(
873 
    tPLH : time := 20 ns;
874 
    tPHL : time := 20 ns
875 
);
876 
port(
877 
    X_1  : in    std_logic;  -- 2A1
878 
    X_2  : in    std_logic;  -- 1A1
879 
    X_3  : in    std_logic;  -- 1A2
880 
    X_4  : in    std_logic;  -- 1B1
881 
    X_5  : in    std_logic;  -- 1B2
882 
    X_6  : out   std_logic;  -- 1Y\
883 
    X_7  : inout std_logic;  -- GND
884 
    X_8  : out   std_logic;  -- 2Y\
885 
    X_9  : in    std_logic;  -- 2B3
886 
    X_10 : in    std_logic;  -- 2B2
887 
    X_11 : in    std_logic;  -- 2B1
888 
    X_12 : in    std_logic;  -- 2A3
889 
    X_13 : in    std_logic;  -- 2A2
890 
    X_14 : inout std_logic   -- Vcc
891 
);
892 
end component SN74LS51N;
893 
 
894 
-- SN74H52: Expandable 2-2-2-3-input and-or gate
895 
-- SN7453:  Expandable 4-wide 2-input and-or-invert gate
896 
-- SN74H53: Expandable 2-2-2-3-input and-or-invert gate
897 
 
898 
-----------------------------------------------------------------------
899 
-- SN74LS54N: 4-wide 2-input AND-OR-Invert gate (Pinout C)
900 
-----------------------------------------------------------------------
901 
component SN74LS54N is
902 
generic(
903 
    tPLH : time := 20 ns;
904 
    tPHL : time := 20 ns
905 
);
906 
port(
907 
    X_1  : in    std_logic;  -- 1A1
908 
    X_2  : in    std_logic;  -- 1A2
909 
    X_3  : in    std_logic;  -- 1B1
910 
    X_4  : in    std_logic;  -- 1B2
911 
    X_5  : in    std_logic;  -- 1B3
912 
    X_6  : out   std_logic;  -- 1Y\
913 
    X_7  : inout std_logic;  -- GND
914 
                             --
915 
    X_9  : in    std_logic;  -- 1D3
916 
    X_10 : in    std_logic;  -- 1D2
917 
    X_11 : in    std_logic;  -- 1D1
918 
    X_12 : in    std_logic;  -- 1C2
919 
    X_13 : in    std_logic;  -- 1C1
920 
    X_14 : inout std_logic   -- Vcc
921 
);
922 
end component SN74LS54N;
923 
 
924 
-----------------------------------------------------------------------
925 
-- SN74LS55N: 2-wide 4-input AND-OR-Invert gate (Pinout B)
926 
-----------------------------------------------------------------------
927 
component SN74LS55N is
928 
generic(
929 
    tPLH : time := 15 ns;
930 
    tPHL : time := 15 ns
931 
);
932 
port(
933 
    X_1  : in    std_logic;  -- 1A1
934 
    X_2  : in    std_logic;  -- 1A2
935 
    X_3  : in    std_logic;  -- 1A3
936 
    X_4  : in    std_logic;  -- 1A4
937 
                             --
938 
                             --
939 
    X_7  : inout std_logic;  -- GND
940 
    X_8  : out   std_logic;  -- 1Y\
941 
                             --
942 
    X_10 : in    std_logic;  -- 1B4
943 
    X_11 : in    std_logic;  -- 1B3
944 
    X_12 : in    std_logic;  -- 1B2
945 
    X_13 : in    std_logic;  -- 1B1
946 
    X_14 : inout std_logic   -- Vcc
947 
);
948 
end component SN74LS55N;
949 
 
950 
-- SN74LS56P: frequency divider
951 
-- SN74LS57P: frequency divider
952 
-- SN7460: Dual 4-input expander
953 
-- SN74H60: Dual 4-input expander
954 
-- SN74H61: Triple 3-input expander
955 
-- SN74H62: 3-2-2-3-input and-or expander
956 
 
957 
-----------------------------------------------------------------------
958 
-- SN74S64N: 4-2-3-2 input AND-OR-Invert gate
959 
-----------------------------------------------------------------------
960 
component SN74S64N is
961 
generic(
962 
    tPLH : time := 5.5 ns;
963 
    tPHL : time := 5.5 ns
964 
);
965 
port(
966 
    X_1  : in    std_logic;  -- 1D1
967 
    X_2  : in    std_logic;  -- 1A1
968 
    X_3  : in    std_logic;  -- 1A2
969 
    X_4  : in    std_logic;  -- 1B1
970 
    X_5  : in    std_logic;  -- 1B2
971 
    X_6  : in    std_logic;  -- 1B3
972 
    X_7  : inout std_logic;  -- GND
973 
    X_8  : out   std_logic;  -- 1Y\
974 
    X_9  : in    std_logic;  -- 1C2
975 
    X_10 : in    std_logic;  -- 1C1
976 
    X_11 : in    std_logic;  -- 1D4
977 
    X_12 : in    std_logic;  -- 1D3
978 
    X_13 : in    std_logic;  -- 1D2
979 
    X_14 : inout std_logic   -- Vcc
980 
);
981 
end component SN74S64N;
982 
 
983 
-----------------------------------------------------------------------
984 
-- SN74S65N: 4-2-3-2 input AND-OR-Invert gate (open collector)
985 
-----------------------------------------------------------------------
986 
component SN74S65N is
987 
generic(
988 
    tPLH : time := 7.5 ns;
989 
    tPHL : time := 8.5 ns
990 
);
991 
port(
992 
    X_1  : in    std_logic;  -- 1D1
993 
    X_2  : in    std_logic;  -- 1A1
994 
    X_3  : in    std_logic;  -- 1A2
995 
    X_4  : in    std_logic;  -- 1B1
996 
    X_5  : in    std_logic;  -- 1B2
997 
    X_6  : in    std_logic;  -- 1B3
998 
    X_7  : inout std_logic;  -- GND
999 
    X_8  : out   std_logic;  -- 1Y\
1000 
    X_9  : in    std_logic;  -- 1C2
1001 
    X_10 : in    std_logic;  -- 1C1
1002 
    X_11 : in    std_logic;  -- 1D4
1003 
    X_12 : in    std_logic;  -- 1D3
1004 
    X_13 : in    std_logic;  -- 1D2
1005 
    X_14 : inout std_logic   -- Vcc
1006 
);
1007 
end component SN74S65N;
1008 
 
1009 
-----------------------------------------------------------------------
1010 
-- SN74LS68N: Dual 4-bit decade counter
1011 
-----------------------------------------------------------------------
1012 
component SN74LS68N is
1013 
generic(
1014 
    tPLH10 : time := 11 ns;
1015 
    tPHL10 : time := 21 ns;
1016 
    tPLH11 : time := 12 ns;
1017 
    tPHL11 : time := 18 ns;
1018 
    tPLH12 : time := 23 ns;
1019 
    tPHL12 : time := 32 ns;
1020 
    tPLH13 : time := 12 ns;
1021 
    tPHL13 : time := 20 ns;
1022 
    tPLH20 : time := 11 ns;
1023 
    tPHL20 : time := 21 ns;
1024 
    tPLH21 : time := 24 ns;
1025 
    tPHL21 : time := 29 ns;
1026 
    tPLH22 : time := 35 ns;
1027 
    tPHL22 : time := 40 ns;
1028 
    tPLH23 : time := 24 ns;
1029 
    tPHL23 : time := 29 ns
1030 
);
1031 
port(
1032 
    X_1  : in    std_logic;  -- 1CLKA
1033 
    X_2  : out   std_logic;  -- 1QB
1034 
    X_3  : out   std_logic;  -- 1QD
1035 
    X_4  : in    std_logic;  -- \1CLR
1036 
    X_5  : out   std_logic;  -- 2QC
1037 
                             --
1038 
    X_7  : out   std_logic;  -- 2QA
1039 
    X_8  : inout std_logic;  -- GND
1040 
    X_9  : in    std_logic;  -- 2CLK
1041 
    X_10 : out   std_logic;  -- 2QB
1042 
    X_11 : in    std_logic;  -- \2CLR
1043 
    X_12 : out   std_logic;  -- 2QD
1044 
    X_13 : out   std_logic;  -- 1QC
1045 
    X_14 : out   std_logic;  -- 1QA
1046 
    X_15 : in    std_logic;  -- 1CLKB
1047 
    X_16 : inout std_logic   -- Vcc
1048 
);
1049 
end component SN74LS68N;
1050 
 
1051 
-----------------------------------------------------------------------
1052 
-- SN74LS69N: Dual 4-bit binary counter
1053 
-----------------------------------------------------------------------
1054 
component SN74LS69N is
1055 
generic(
1056 
    tPLH10 : time := 11 ns;
1057 
    tPHL10 : time := 21 ns;
1058 
    tPLH11 : time := 11 ns;
1059 
    tPHL11 : time := 21 ns;
1060 
    tPLH12 : time := 24 ns;
1061 
    tPHL12 : time := 32 ns;
1062 
    tPLH13 : time := 38 ns;
1063 
    tPHL13 : time := 45 ns;
1064 
    tPLH20 : time := 11 ns;
1065 
    tPHL20 : time := 21 ns;
1066 
    tPLH21 : time := 21 ns;
1067 
    tPHL21 : time := 29 ns;
1068 
    tPLH22 : time := 35 ns;
1069 
    tPHL22 : time := 40 ns;
1070 
    tPLH23 : time := 54 ns;
1071 
    tPHL23 : time := 30 ns
1072 
);
1073 
port(
1074 
    X_1  : in    std_logic;  -- 1CLKA
1075 
    X_2  : out   std_logic;  -- 1QB
1076 
    X_3  : out   std_logic;  -- 1QD
1077 
    X_4  : in    std_logic;  -- \1CLR
1078 
    X_5  : out   std_logic;  -- 2QC
1079 
                             --
1080 
    X_7  : out   std_logic;  -- 2QA
1081 
    X_8  : inout std_logic;  -- GND
1082 
    X_9  : in    std_logic;  -- 2CLK
1083 
    X_10 : out   std_logic;  -- 2QB
1084 
    X_11 : in    std_logic;  -- \2CLR
1085 
    X_12 : out   std_logic;  -- 2QD
1086 
    X_13 : out   std_logic;  -- 1QC
1087 
    X_14 : out   std_logic;  -- 1QA
1088 
    X_15 : in    std_logic;  -- 1CLKB
1089 
    X_16 : inout std_logic   -- Vcc
1090 
);
1091 
end component SN74LS69N;
1092 
 
1093 
-----------------------------------------------------------------------
1094 
-- SN74LS70N: JK edge-triggered flipflop (Pinout A)
1095 
-----------------------------------------------------------------------
1096 
component SN74LS70N is
1097 
generic(
1098 
    tSETUP : time := 20 ns;     -- Setup time before clock
1099 
    tPLHCP : time := 50 ns;     -- Clock rising
1100 
    tPHLCP : time := 50 ns;     -- Clock falling
1101 
    tPLHSC : time := 50 ns;     -- S/C rising
1102 
    tPHLSC : time := 50 ns      -- S/C falling
1103 
);
1104 
port(
1105 
                             --
1106 
    X_2  : in    std_logic;  -- CD\
1107 
    X_3  : in    std_logic;  -- J1
1108 
    X_4  : in    std_logic;  -- J2
1109 
    X_5  : in    std_logic;  -- J3\
1110 
    X_6  : out   std_logic;  -- Q\
1111 
    X_7  : inout std_logic;  -- GND
1112 
    X_8  : out   std_logic;  -- Q
1113 
    X_9  : in    std_logic;  -- K3\
1114 
    X_10 : in    std_logic;  -- K1
1115 
    X_11 : in    std_logic;  -- K2
1116 
    X_12 : in    std_logic;  -- CP
1117 
    X_13 : in    std_logic;  -- SD\
1118 
    X_14 : inout std_logic   -- Vcc
1119 
);
1120 
end component SN74LS70N;
1121 
 
1122 
-----------------------------------------------------------------------
1123 
-- SN74LS71N: JK master-slave flipflop (with AND/OR inputs)
1124 
-----------------------------------------------------------------------
1125 
component SN74LS71N is
1126 
generic(
1127 
    tSETUP : time :=  0 ns;     -- Setup time before clock
1128 
    tPLHCP : time := 21 ns;     -- Clock rising
1129 
    tPHLCP : time := 27 ns;     -- Clock falling
1130 
    tPLHSC : time := 13 ns;     -- S/C rising
1131 
    tPHLSC : time := 24 ns      -- S/C falling
1132 
);
1133 
port(
1134 
    X_1  : in    std_logic;  -- J1A
1135 
    X_2  : in    std_logic;  -- J1B
1136 
    X_3  : in    std_logic;  -- J2A
1137 
    X_4  : in    std_logic;  -- J2B
1138 
    X_5  : in    std_logic;  -- SD\
1139 
    X_6  : out   std_logic;  -- Q
1140 
    X_7  : inout std_logic;  -- GND
1141 
    X_8  : out   std_logic;  -- Q\
1142 
    X_9  : in    std_logic;  -- K1A
1143 
    X_10 : in    std_logic;  -- K1B
1144 
    X_11 : in    std_logic;  -- K2A
1145 
    X_12 : in    std_logic;  -- K2B
1146 
    X_13 : in    std_logic;  -- CP
1147 
    X_14 : inout std_logic   -- Vcc
1148 
);
1149 
end component SN74LS71N;
1150 
 
1151 
-----------------------------------------------------------------------
1152 
-- SN74LS72N: JK master-slave flipflop (with AND inputs) (Pinout A)
1153 
-----------------------------------------------------------------------
1154 
component SN74LS72N is
1155 
generic(
1156 
    tSETUP : time :=  0 ns;     -- Setup time before clock
1157 
    tPLHCP : time := 21 ns;     -- Clock rising
1158 
    tPHLCP : time := 27 ns;     -- Clock falling
1159 
    tPLHSC : time := 13 ns;     -- S/C rising
1160 
    tPHLSC : time := 24 ns      -- S/C falling
1161 
);
1162 
port(
1163 
                             --
1164 
    X_2  : in    std_logic;  -- CD\
1165 
    X_3  : in    std_logic;  -- J1
1166 
    X_4  : in    std_logic;  -- J2
1167 
    X_5  : in    std_logic;  -- J3
1168 
    X_6  : out   std_logic;  -- Q\
1169 
    X_7  : inout std_logic;  -- GND
1170 
    X_8  : out   std_logic;  -- Q
1171 
    X_9  : in    std_logic;  -- K1
1172 
    X_10 : in    std_logic;  -- K2
1173 
    X_11 : in    std_logic;  -- K3
1174 
    X_12 : in    std_logic;  -- CP\
1175 
    X_13 : in    std_logic;  -- SD\
1176 
    X_14 : inout std_logic   -- Vcc
1177 
 );
1178 
end component SN74LS72N;
1179 
 
1180 
-----------------------------------------------------------------------
1181 
-- SN74LS73N: Dual JK flipflop
1182 
-----------------------------------------------------------------------
1183 
component SN74LS73N is
1184 
generic(
1185 
    tSETUP : time := 20 ns;     -- Setup time before clock
1186 
    tPLHCP : time := 20 ns;     -- Clock rising
1187 
    tPHLCP : time := 30 ns;     -- Clock falling
1188 
    tPLHSC : time := 20 ns;     -- S/C rising
1189 
    tPHLSC : time := 30 ns      -- S/C falling
1190 
);
1191 
port(
1192 
    X_1  : in    std_logic;  -- CP1\
1193 
    X_2  : in    std_logic;  -- CD1\
1194 
    X_3  : in    std_logic;  -- K1
1195 
    X_4  : inout std_logic;  -- Vcc
1196 
    X_5  : in    std_logic;  -- CP2\
1197 
    X_6  : in    std_logic;  -- CD2\
1198 
    X_7  : in    std_logic;  -- J2
1199 
    X_8  : out   std_logic;  -- Q2\
1200 
    X_9  : out   std_logic;  -- Q2
1201 
    X_10 : in    std_logic;  -- K2
1202 
    X_11 : inout std_logic;  -- GND
1203 
    X_12 : out   std_logic;  -- Q1
1204 
    X_13 : out   std_logic;  -- Q1\
1205 
    X_14 : in    std_logic   -- J1
1206 
);
1207 
end component SN74LS73N;
1208 
 
1209 
-----------------------------------------------------------------------
1210 
-- SN74LS74N: Dual D-type +ve edge-triggered flipflop (Pinout A)
1211 
-----------------------------------------------------------------------
1212 
component SN74LS74N is
1213 
generic(
1214 
    tSETUP : time := 20 ns;     -- Setup time before clock
1215 
    tPLHCP : time := 25 ns;     -- Clock rising
1216 
    tPHLCP : time := 35 ns;     -- Clock falling
1217 
    tPLHSC : time := 15 ns;     -- S/C rising
1218 
    tPHLSC : time := 35 ns      -- S/C falling
1219 
);
1220 
port(
1221 
    X_1  : in    std_logic;  -- CD1\
1222 
    X_2  : in    std_logic;  -- D1
1223 
    X_3  : in    std_logic;  -- CP1
1224 
    X_4  : in    std_logic;  -- SD1\
1225 
    X_5  : out   std_logic;  -- Q1
1226 
    X_6  : out   std_logic;  -- Q1\
1227 
    X_7  : inout std_logic;  -- GND
1228 
    X_8  : out   std_logic;  -- Q2\
1229 
    X_9  : out   std_logic;  -- Q2
1230 
    X_10 : in    std_logic;  -- SD2\
1231 
    X_11 : in    std_logic;  -- CP2
1232 
    X_12 : in    std_logic;  -- D2
1233 
    X_13 : in    std_logic;  -- CD2\
1234 
    X_14 : inout std_logic   -- Vcc
1235 
);
1236 
end component SN74LS74N;
1237 
 
1238 
-----------------------------------------------------------------------
1239 
-- SN74LS75N: 4-bit bistable latch
1240 
-----------------------------------------------------------------------
1241 
component SN74LS75N is
1242 
generic(
1243 
    tSETUP : time := 20 ns;     -- Setup time before clock
1244 
    tPLHCP : time := 40 ns;     -- Rising
1245 
    tPHLCP : time := 25 ns      -- Ralling
1246 
);
1247 
port(
1248 
    X_1  : out   std_logic;  -- Q1\
1249 
    X_2  : in    std_logic;  -- D1
1250 
    X_3  : in    std_logic;  -- D2
1251 
    X_4  : in    std_logic;  -- E34
1252 
    X_5  : inout std_logic;  -- Vcc
1253 
    X_6  : in    std_logic;  -- D3
1254 
    X_7  : in    std_logic;  -- D4
1255 
    X_8  : out   std_logic;  -- Q4\
1256 
    X_9  : out   std_logic;  -- Q4
1257 
    X_10 : out   std_logic;  -- Q3\
1258 
    X_11 : out   std_logic;  -- Q3
1259 
    X_12 : inout std_logic;  -- GND
1260 
    X_13 : in    std_logic;  -- E12
1261 
    X_14 : out   std_logic;  -- Q2\
1262 
    X_15 : out   std_logic;  -- Q2
1263 
    X_16 : out   std_logic   -- Q1
1264 
);
1265 
end component SN74LS75N;
1266 
 
1267 
-----------------------------------------------------------------------
1268 
-- SN74LS76N: Dual JK flipflop
1269 
-----------------------------------------------------------------------
1270 
component SN74LS76N is
1271 
generic(
1272 
    tSETUP : time := 20 ns;     -- Setup time before clock
1273 
    tPLHCP : time := 20 ns;     -- Clock rising
1274 
    tPHLCP : time := 30 ns;     -- Clock falling
1275 
    tPLHSC : time := 20 ns;     -- S/C rising
1276 
    tPHLSC : time := 30 ns      -- S/C falling
1277 
);
1278 
port(
1279 
    X_1  : in    std_logic;  -- CP1\
1280 
    X_2  : in    std_logic;  -- SD1\
1281 
    X_3  : in    std_logic;  -- CD1\
1282 
    X_4  : in    std_logic;  -- J1
1283 
    X_5  : inout std_logic;  -- Vcc
1284 
    X_6  : in    std_logic;  -- CP2\
1285 
    X_7  : in    std_logic;  -- SD2\
1286 
    X_8  : in    std_logic;  -- CD2\
1287 
    X_9  : in    std_logic;  -- J2
1288 
    X_10 : out   std_logic;  -- Q2\
1289 
    X_11 : out   std_logic;  -- Q2
1290 
    X_12 : in    std_logic;  -- K2
1291 
    X_13 : inout std_logic;  -- GND
1292 
    X_14 : out   std_logic;  -- Q1\
1293 
    X_15 : out   std_logic;  -- Q1
1294 
    X_16 : in    std_logic   -- K1
1295 
);
1296 
end component SN74LS76N;
1297 
 
1298 
-----------------------------------------------------------------------
1299 
-- SN74LS77N: Quad D-type latch
1300 
-----------------------------------------------------------------------
1301 
component SN74LS77N is
1302 
generic(
1303 
    tSETUP : time := 20 ns;     -- Setup time before clock
1304 
    tPLHCP : time := 40 ns;     -- Rising
1305 
    tPHLCP : time := 25 ns      -- Ralling
1306 
);
1307 
port(
1308 
    X_1  : in    std_logic;  -- D1
1309 
    X_2  : in    std_logic;  -- D2
1310 
    X_3  : in    std_logic;  -- E34
1311 
    X_4  : inout std_logic;  -- Vcc
1312 
    X_5  : in    std_logic;  -- D3
1313 
    X_6  : in    std_logic;  -- D4
1314 
                             --
1315 
    X_8  : out   std_logic;  -- Q4
1316 
    X_9  : out   std_logic;  -- Q3
1317 
                             --
1318 
    X_11 : inout std_logic;  -- GND
1319 
    X_12 : in    std_logic;  -- E12
1320 
    X_13 : out   std_logic;  -- Q2
1321 
    X_14 : out   std_logic   -- Q1
1322 
);
1323 
end component SN74LS77N;
1324 
 
1325 
-----------------------------------------------------------------------
1326 
-- SN74LS78N: Dual JK flipflop (Pinout A)
1327 
-----------------------------------------------------------------------
1328 
component SN74LS78N is
1329 
generic(
1330 
    tSETUP : time := 20 ns;     -- Setup time before clock
1331 
    tPLHCP : time := 20 ns;     -- Clock rising
1332 
    tPHLCP : time := 30 ns;     -- Clock falling
1333 
    tPLHSC : time := 20 ns;     -- S/C rising
1334 
    tPHLSC : time := 30 ns      -- S/C falling
1335 
);
1336 
port(
1337 
    X_1  : in    std_logic;  -- K1
1338 
    X_2  : out   std_logic;  -- Q1
1339 
    X_3  : out   std_logic;  -- Q1\
1340 
    X_4  : in    std_logic;  -- J1
1341 
    X_5  : out   std_logic;  -- Q2\
1342 
    X_6  : out   std_logic;  -- Q2
1343 
    X_7  : inout std_logic;  -- GND
1344 
    X_8  : in    std_logic;  -- K2
1345 
    X_9  : in    std_logic;  -- CP\
1346 
    X_10 : in    std_logic;  -- SD2\
1347 
    X_11 : in    std_logic;  -- J2
1348 
    X_12 : in    std_logic;  -- CD\
1349 
    X_13 : in    std_logic;  -- SD1\
1350 
    X_14 : inout std_logic   -- Vcc
1351 
);
1352 
end component SN74LS78N;
1353 
 
1354 
-----------------------------------------------------------------------
1355 
-- SN7480N: Gated full adder (Pinout A)
1356 
--          The expansion inputs are not modelled
1357 
-----------------------------------------------------------------------
1358 
component SN7480N is
1359 
generic(
1360 
    tPLHCC : time := 17 ns;  -- Carry-in to carry-out
1361 
    tPHLCC : time := 12 ns;
1362 
    tPLHBC : time := 25 ns;  -- Data to carry-out
1363 
    tPHLBC : time := 55 ns;
1364 
    tPLHS  : time := 70 ns;  -- Data* to S
1365 
    tPHLS  : time := 80 ns;
1366 
    tPLHSB : time := 55 ns;  -- Data* to S\
1367 
    tPHLSB : time := 75 ns;
1368 
    tPLHX  : time := 65 ns;  -- Data to Data*
1369 
    tPHLX  : time := 25 ns
1370 
);
1371 
port(
1372 
                             -- BX
1373 
    X_2  : in    std_logic;  -- BC
1374 
    X_3  : in    std_logic;  -- CN
1375 
    X_4  : out   std_logic;  -- CNP1\
1376 
    X_5  : out   std_logic;  -- S
1377 
    X_6  : out   std_logic;  -- S\
1378 
    X_7  : inout std_logic;  -- GND
1379 
    X_8  : in    std_logic;  -- A1
1380 
    X_9  : in    std_logic;  -- A2
1381 
                             -- AX
1382 
    X_11 : in    std_logic;  -- AC
1383 
    X_12 : in    std_logic;  -- B1
1384 
    X_13 : in    std_logic;  -- B2
1385 
    X_14 : inout std_logic   -- Vcc
1386 
);
1387 
end component SN7480N;
1388 
 
1389 
-----------------------------------------------------------------------
1390 
-- SN7482N: 2-bit full adder
1391 
-----------------------------------------------------------------------
1392 
component SN7482N is
1393 
generic(
1394 
    tPLHS1 : time := 34 ns;
1395 
    tPHLS1 : time := 40 ns;
1396 
    tPLHS2 : time := 40 ns;
1397 
    tPHLS2 : time := 42 ns;
1398 
    tPLHC  : time := 19 ns;
1399 
    tPHLC  : time := 27 ns
1400 
);
1401 
port(
1402 
    X_1  : out   std_logic;  -- S1
1403 
    X_2  : in    std_logic;  -- A1
1404 
    X_3  : in    std_logic;  -- B1
1405 
    X_4  : inout std_logic;  -- Vcc
1406 
    X_5  : in    std_logic;  -- CIN
1407 
                             --
1408 
                             --
1409 
                             --
1410 
                             --
1411 
    X_10 : out   std_logic;  -- C2
1412 
    X_11 : inout std_logic;  -- GND
1413 
    X_12 : out   std_logic;  -- S2
1414 
    X_13 : in    std_logic;  -- B2
1415 
    X_14 : in    std_logic   -- A2
1416 
);
1417 
end component SN7482N;
1418 
 
1419 
-----------------------------------------------------------------------
1420 
-- SN74LS83AN: 4-bit binary full adder (fast carry)
1421 
-----------------------------------------------------------------------
1422 
component SN74LS83AN is
1423 
generic(
1424 
    tPLHS  : time := 24 ns;
1425 
    tPHLS  : time := 24 ns;
1426 
    tPLHC  : time := 17 ns;
1427 
    tPHLC  : time := 17 ns
1428 
);
1429 
port(
1430 
    X_1  : in    std_logic;  -- A3
1431 
    X_2  : out   std_logic;  -- S2
1432 
    X_3  : in    std_logic;  -- A2
1433 
    X_4  : in    std_logic;  -- B2
1434 
    X_5  : inout std_logic;  -- Vcc
1435 
    X_6  : out   std_logic;  -- S1
1436 
    X_7  : in    std_logic;  -- B1
1437 
    X_8  : in    std_logic;  -- A1
1438 
    X_9  : out   std_logic;  -- S0
1439 
    X_10 : in    std_logic;  -- A0
1440 
    X_11 : in    std_logic;  -- B0
1441 
    X_12 : inout std_logic;  -- GND
1442 
    X_13 : in    std_logic;  -- C0
1443 
    X_14 : out   std_logic;  -- C4
1444 
    X_15 : out   std_logic;  -- S3
1445 
    X_16 : in    std_logic   -- B3
1446 
);
1447 
end component SN74LS83AN;
1448 
 
1449 
-----------------------------------------------------------------------
1450 
-- SN74LS85N: 4-bit magnitude comparator
1451 
-----------------------------------------------------------------------
1452 
component SN74LS85N is
1453 
generic(
1454 
    tPLH : time := 45 ns;
1455 
    tPHL : time := 45 ns
1456 
);
1457 
port(
1458 
    X_1  : in    std_logic;  -- B3
1459 
    X_2  : in    std_logic;  -- IA<B
1460 
    X_3  : in    std_logic;  -- IA=B
1461 
    X_4  : in    std_logic;  -- IA>B
1462 
    X_5  : out   std_logic;  -- OA>B
1463 
    X_6  : out   std_logic;  -- OA=B
1464 
    X_7  : out   std_logic;  -- OA<B
1465 
    X_8  : inout std_logic;  -- GND
1466 
    X_9  : in    std_logic;  -- B0
1467 
    X_10 : in    std_logic;  -- A0
1468 
    X_11 : in    std_logic;  -- B1
1469 
    X_12 : in    std_logic;  -- A1
1470 
    X_13 : in    std_logic;  -- A2
1471 
    X_14 : in    std_logic;  -- B2
1472 
    X_15 : in    std_logic;  -- A3
1473 
    X_16 : inout std_logic   -- Vcc
1474 
);
1475 
end component SN74LS85N;
1476 
 
1477 
-----------------------------------------------------------------------
1478 
-- SN74LS86N: Quad 2-input XOR gate
1479 
-----------------------------------------------------------------------
1480 
component SN74LS86N is
1481 
generic(
1482 
    tPLH : time := 30 ns;
1483 
    tPHL : time := 22 ns
1484 
);
1485 
port(
1486 
    X_1  : in    std_logic;  -- 1A
1487 
    X_2  : in    std_logic;  -- 1B
1488 
    X_3  : out   std_logic;  -- 1Y
1489 
    X_4  : in    std_logic;  -- 2A
1490 
    X_5  : in    std_logic;  -- 2B
1491 
    X_6  : out   std_logic;  -- 2Y
1492 
    X_7  : inout std_logic;  -- GND
1493 
    X_8  : out   std_logic;  -- 3Y
1494 
    X_9  : in    std_logic;  -- 3B
1495 
    X_10 : in    std_logic;  -- 3A
1496 
    X_11 : out   std_logic;  -- 4Y
1497 
    X_12 : in    std_logic;  -- 4B
1498 
    X_13 : in    std_logic;  -- 4A
1499 
    X_14 : inout std_logic   -- Vcc
1500 
);
1501 
end component SN74LS86N;
1502 
 
1503 
-----------------------------------------------------------------------
1504 
-- SN74H87N: 4-bit true/complement, zero-one element
1505 
-----------------------------------------------------------------------
1506 
component SN74H87N is
1507 
generic(
1508 
    tPLHI : time := 20 ns;
1509 
    tPHLI : time := 19 ns;
1510 
    tPLHS : time := 25 ns;
1511 
    tPHLS : time := 25 ns
1512 
);
1513 
port(
1514 
    X_1  :       std_logic;  -- S2
1515 
    X_2  :       std_logic;  -- I1
1516 
    X_3  : out   std_logic;  -- Q1
1517 
                             --
1518 
    X_5  :       std_logic;  -- I2
1519 
    X_6  : out   std_logic;  -- Q2
1520 
    X_7  : inout std_logic;  -- GND
1521 
    X_8  :       std_logic;  -- S1
1522 
    X_9  : out   std_logic;  -- Q3
1523 
    X_10 :       std_logic;  -- I3
1524 
                             --
1525 
    X_12 : out   std_logic;  -- Q4
1526 
    X_13 :       std_logic;  -- I4
1527 
    X_14 : inout std_logic   -- Vcc
1528 
);
1529 
end component SN74H87N;
1530 
 
1531 
-----------------------------------------------------------------------
1532 
-- SN74LS89N: 64-bit random-access memory (open collector)
1533 
-----------------------------------------------------------------------
1534 
component SN74LS89N is
1535 
generic(
1536 
    tPLC  : time     := 10 ns;
1537 
    tPLA  : time     := 37 ns;
1538 
    tREC  : time     := 30 ns;
1539 
    tSUD  : time     := 25 ns;
1540 
    tSUA  : time     := 10 ns
1541 
);
1542 
port(
1543 
    X_1   : in    std_logic;  -- A0
1544 
    X_2   : in    std_logic;  -- CS\
1545 
    X_3   : in    std_logic;  -- WE\
1546 
    X_4   : in    std_logic;  -- D1
1547 
    X_5   : out   std_logic;  -- Q1\
1548 
    X_6   : in    std_logic;  -- D2
1549 
    X_7   : out   std_logic;  -- Q2\
1550 
    X_8   : inout std_logic;  -- GND
1551 
    X_9   : out   std_logic;  -- Q3\
1552 
    X_10  : in    std_logic;  -- D3
1553 
    X_11  : out   std_logic;  -- Q4\
1554 
    X_12  : in    std_logic;  -- D4
1555 
    X_13  : in    std_logic;  -- A3
1556 
    X_14  : in    std_logic;  -- A2
1557 
    X_15  : in    std_logic;  -- A1
1558 
    X_16  : inout std_logic   -- Vcc
1559 
);
1560 
end component SN74LS89N;
1561 
 
1562 
-----------------------------------------------------------------------
1563 
-- SN74LS90AN: Decade counter (ripple)
1564 
-----------------------------------------------------------------------
1565 
component SN74LS90AN is
1566 
generic(
1567 
    tPLH0 : time := 16 ns;
1568 
    tPHL0 : time := 18 ns;
1569 
    tPLH1 : time := 16 ns;
1570 
    tPHL1 : time := 21 ns;
1571 
    tPLH2 : time := 32 ns;
1572 
    tPHL2 : time := 35 ns;
1573 
    tPLH3 : time := 32 ns;
1574 
    tPHL3 : time := 35 ns
1575 
);
1576 
port(
1577 
    X_1  : in    std_logic;  -- CP1\
1578 
    X_2  : in    std_logic;  -- MR1
1579 
    X_3  : in    std_logic;  -- MR2
1580 
                             --
1581 
    X_5  : inout std_logic;  -- Vcc
1582 
    X_6  : in    std_logic;  -- MS1
1583 
    X_7  : in    std_logic;  -- MS2
1584 
    X_8  : out   std_logic;  -- Q2
1585 
    X_9  : out   std_logic;  -- Q1
1586 
    X_10 : inout std_logic;  -- GND
1587 
    X_11 : out   std_logic;  -- Q3
1588 
    X_12 : out   std_logic;  -- Q0
1589 
                             --
1590 
    X_14 : in    std_logic   -- CP0\
1591 
);
1592 
end component SN74LS90AN;
1593 
 
1594 
-----------------------------------------------------------------------
1595 
-- SN74LS91AN: 8-bit shift register (Pinout A)
1596 
-----------------------------------------------------------------------
1597 
component SN74LS91AN is
1598 
generic(
1599 
    tPLH : time := 40 ns;
1600 
    tPHL : time := 40 ns;
1601 
    tSU  : time := 25 ns
1602 
);
1603 
port(
1604 
                             --
1605 
                             --
1606 
                             --
1607 
                             --
1608 
    X_5  : inout std_logic;  -- Vcc
1609 
                             --
1610 
                             --
1611 
                             --
1612 
    X_9  : in    std_logic;  -- CP
1613 
    X_10 : inout std_logic;  -- GND
1614 
    X_11 : in    std_logic;  -- B
1615 
    X_12 : in    std_logic;  -- A
1616 
    X_13 : out   std_logic;  -- Q
1617 
    X_14 : out   std_logic   -- Q\
1618 
);
1619 
end component SN74LS91AN;
1620 
 
1621 
-----------------------------------------------------------------------
1622 
-- SN74LS92N: Divide-by-12 counter (ripple)
1623 
-----------------------------------------------------------------------
1624 
component SN74LS92N is
1625 
generic(
1626 
    tPLH0 : time := 16 ns;
1627 
    tPHL0 : time := 18 ns;
1628 
    tPLH1 : time := 16 ns;
1629 
    tPHL1 : time := 21 ns;
1630 
    tPLH2 : time := 16 ns;
1631 
    tPHL2 : time := 21 ns;
1632 
    tPLH3 : time := 32 ns;
1633 
    tPHL3 : time := 35 ns
1634 
);
1635 
port(
1636 
    X_1  : in    std_logic;  -- CP1\
1637 
                             --
1638 
                             --
1639 
                             --
1640 
    X_5  : inout std_logic;  -- Vcc
1641 
    X_6  : in    std_logic;  -- MR1
1642 
    X_7  : in    std_logic;  -- MR2
1643 
    X_8  : out   std_logic;  -- Q3
1644 
    X_9  : out   std_logic;  -- Q2
1645 
    X_10 : inout std_logic;  -- GND
1646 
    X_11 : out   std_logic;  -- Q1
1647 
    X_12 : out   std_logic;  -- Q0
1648 
                             --
1649 
    X_14 : in    std_logic   -- CP0\
1650 
);
1651 
end component SN74LS92N;
1652 
 
1653 
-----------------------------------------------------------------------
1654 
-- SN74LS93N: Divide-by-16 (binary) counter (ripple)
1655 
-----------------------------------------------------------------------
1656 
component SN74LS93N is
1657 
generic(
1658 
    tPLH0 : time := 16 ns;
1659 
    tPHL0 : time := 18 ns;
1660 
    tPLH1 : time := 16 ns;
1661 
    tPHL1 : time := 21 ns;
1662 
    tPLH2 : time := 32 ns;
1663 
    tPHL2 : time := 35 ns;
1664 
    tPLH3 : time := 51 ns;
1665 
    tPHL3 : time := 51 ns
1666 
);
1667 
port(
1668 
    X_1  : in    std_logic;  -- CP1\
1669 
    X_2  : in    std_logic;  -- MR1
1670 
    X_3  : in    std_logic;  -- MR2
1671 
                             --
1672 
    X_5  : inout std_logic;  -- Vcc
1673 
                             --
1674 
                             --
1675 
    X_8  : out   std_logic;  -- Q2
1676 
    X_9  : out   std_logic;  -- Q1
1677 
    X_10 : inout std_logic;  -- GND
1678 
    X_11 : out   std_logic;  -- Q3
1679 
    X_12 : out   std_logic;  -- Q0
1680 
                             --
1681 
    X_14 : in    std_logic   -- CP0\
1682 
);
1683 
end component SN74LS93N;
1684 
 
1685 
-----------------------------------------------------------------------
1686 
-- SN74LS94N: 4-bit shift register
1687 
-----------------------------------------------------------------------
1688 
component SN74LS94N is
1689 
generic(
1690 
    tPLH : time := 40 ns;
1691 
    tPHL : time := 40 ns;
1692 
    tSU  : time := 35 ns
1693 
);
1694 
port(
1695 
    X_1  : in    std_logic;  -- P1A
1696 
    X_2  : in    std_logic;  -- P1B
1697 
    X_3  : in    std_logic;  -- P1C
1698 
    X_4  : in    std_logic;  -- P1D
1699 
    X_5  : inout std_logic;  -- Vcc
1700 
    X_6  : in    std_logic;  -- PL1
1701 
    X_7  : in    std_logic;  -- DS
1702 
    X_8  : in    std_logic;  -- CP
1703 
    X_9  : out   std_logic;  -- QD
1704 
    X_10 : in    std_logic;  -- CL
1705 
    X_11 : in    std_logic;  -- P2D
1706 
    X_12 : inout std_logic;  -- GND
1707 
    X_13 : in    std_logic;  -- P2C
1708 
    X_14 : in    std_logic;  -- P2B
1709 
    X_15 : in    std_logic;  -- PL2
1710 
    X_16 : in    std_logic   -- P2A
1711 
);
1712 
end component SN74LS94N;
1713 
 
1714 
-----------------------------------------------------------------------
1715 
-- SN74LS95N: 4-bit right/left shift register
1716 
-----------------------------------------------------------------------
1717 
component SN74LS95N is
1718 
generic(
1719 
    tPLH : time := 27 ns;
1720 
    tPHL : time := 27 ns;
1721 
    tSU  : time := 20 ns
1722 
);
1723 
port(
1724 
    X_1  : in    std_logic;  -- DS
1725 
    X_2  : in    std_logic;  -- P0
1726 
    X_3  : in    std_logic;  -- P1
1727 
    X_4  : in    std_logic;  -- P2
1728 
    X_5  : in    std_logic;  -- P3
1729 
    X_6  : in    std_logic;  -- PE
1730 
    X_7  : inout std_logic;  -- GND
1731 
    X_8  : in    std_logic;  -- CP2\
1732 
    X_9  : in    std_logic;  -- CP1\
1733 
    X_10 : out   std_logic;  -- Q3
1734 
    X_11 : out   std_logic;  -- Q2
1735 
    X_12 : out   std_logic;  -- Q1
1736 
    X_13 : out   std_logic;  -- Q0
1737 
    X_14 : inout std_logic   -- Vcc
1738 
);
1739 
end component SN74LS95N;
1740 
 
1741 
-----------------------------------------------------------------------
1742 
-- SN74LS96N: 5-bit shift register
1743 
-----------------------------------------------------------------------
1744 
component SN74LS96N is
1745 
generic(
1746 
    tPLH : time := 40 ns;
1747 
    tPHL : time := 40 ns;
1748 
    tSU  : time := 30 ns
1749 
);
1750 
port(
1751 
    X_1  : in    std_logic;  -- CP
1752 
    X_2  : in    std_logic;  -- P0
1753 
    X_3  : in    std_logic;  -- P1
1754 
    X_4  : in    std_logic;  -- P2
1755 
    X_5  : inout std_logic;  -- Vcc
1756 
    X_6  : in    std_logic;  -- P3
1757 
    X_7  : in    std_logic;  -- P4
1758 
    X_8  : in    std_logic;  -- PL
1759 
    X_9  : in    std_logic;  -- DS
1760 
    X_10 : out   std_logic;  -- Q4
1761 
    X_11 : out   std_logic;  -- Q3
1762 
    X_12 : inout std_logic;  -- GND
1763 
    X_13 : out   std_logic;  -- Q2
1764 
    X_14 : out   std_logic;  -- Q1
1765 
    X_15 : out   std_logic;  -- Q0
1766 
    X_16 : in    std_logic   -- CL\
1767 
);
1768 
end component SN74LS96N;
1769 
 
1770 
-- SN74LS97N: Synchronous modulo-64 bit-rate multiplier
1771 
 
1772 
-----------------------------------------------------------------------
1773 
-- SN74100N: Dual 4-bit latch
1774 
-----------------------------------------------------------------------
1775 
component SN74100N is
1776 
generic(
1777 
    tPLH : time := 30 ns;
1778 
    tPHL : time := 25 ns
1779 
);
1780 
port(
1781 
                             --
1782 
    X_2  : in    std_logic;  -- 1D1
1783 
    X_3  : in    std_logic;  -- 1D2
1784 
    X_4  : out   std_logic;  -- 1Q2
1785 
    X_5  : out   std_logic;  -- 1Q1
1786 
                             --
1787 
    X_7  : inout std_logic;  -- GND
1788 
    X_8  : out   std_logic;  -- 2Q1
1789 
    X_9  : out   std_logic;  -- 2Q2
1790 
    X_10 : in    std_logic;  -- 2D2
1791 
    X_11 : in    std_logic;  -- 2D1
1792 
    X_12 : in    std_logic;  -- 2G
1793 
                             --
1794 
                             --
1795 
    X_15 : in    std_logic;  -- 2D3
1796 
    X_16 : in    std_logic;  -- 2D4
1797 
    X_17 : out   std_logic;  -- 2Q4
1798 
    X_18 : out   std_logic;  -- 2Q3
1799 
    X_19 : out   std_logic;  -- 1Q3
1800 
    X_20 : out   std_logic;  -- 1Q4
1801 
    X_21 : in    std_logic;  -- 1D4
1802 
    X_22 : in    std_logic;  -- 1D3
1803 
    X_23 : in    std_logic;  -- 1G
1804 
    X_24 : inout std_logic   -- Vcc
1805 
);
1806 
end component SN74100N;
1807 
 
1808 
-----------------------------------------------------------------------
1809 
-- SN74H101N: JK edge-triggered flipflop (with AND-OR inputs) (Pinout A)
1810 
-----------------------------------------------------------------------
1811 
component SN74H101N is
1812 
generic(
1813 
    tSETUP : time := 13 ns;     -- Setup time before clock
1814 
    tPLHCP : time := 15 ns;     -- Clock rising
1815 
    tPHLCP : time := 20 ns;     -- Clock falling
1816 
    tPLHSC : time := 12 ns;     -- S/C rising
1817 
    tPHLSC : time := 20 ns      -- S/C falling
1818 
);
1819 
port(
1820 
    X_1  : in    std_logic;  -- J1A
1821 
    X_2  : in    std_logic;  -- J1B
1822 
    X_3  : in    std_logic;  -- J2A
1823 
    X_4  : in    std_logic;  -- J2B
1824 
    X_5  : in    std_logic;  -- SD\
1825 
    X_6  : out   std_logic;  -- Q
1826 
    X_7  : inout std_logic;  -- GND
1827 
    X_8  : out   std_logic;  -- Q\
1828 
    X_9  : in    std_logic;  -- K1A
1829 
    X_10 : in    std_logic;  -- K1B
1830 
    X_11 : in    std_logic;  -- K2A
1831 
    X_12 : in    std_logic;  -- K2B
1832 
    X_13 : in    std_logic;  -- CP
1833 
    X_14 : inout std_logic   -- Vcc
1834 
);
1835 
end component SN74H101N;
1836 
 
1837 
-----------------------------------------------------------------------
1838 
-- SN74H102N: JK edge-triggered flipflop (with AND inputs) (Pinout A)
1839 
-----------------------------------------------------------------------
1840 
component SN74H102N is
1841 
generic(
1842 
    tSETUP : time := 13 ns;     -- Setup time before clock
1843 
    tPLHCP : time := 15 ns;     -- Clock rising
1844 
    tPHLCP : time := 20 ns;     -- Clock falling
1845 
    tPLHSC : time := 12 ns;     -- S/C rising
1846 
    tPHLSC : time := 20 ns      -- S/C falling
1847 
);
1848 
port(
1849 
                             --
1850 
    X_2  : in    std_logic;  -- CD\
1851 
    X_3  : in    std_logic;  -- J1
1852 
    X_4  : in    std_logic;  -- J2
1853 
    X_5  : in    std_logic;  -- J3
1854 
    X_6  : out   std_logic;  -- Q\
1855 
    X_7  : inout std_logic;  -- GND
1856 
    X_8  : out   std_logic;  -- Q
1857 
    X_9  : in    std_logic;  -- K1
1858 
    X_10 : in    std_logic;  -- K2
1859 
    X_11 : in    std_logic;  -- K3
1860 
    X_12 : in    std_logic;  -- CP\
1861 
    X_13 : in    std_logic;  -- SD\
1862 
    X_14 : inout std_logic   -- Vcc
1863 
);
1864 
end component SN74H102N;
1865 
 
1866 
-----------------------------------------------------------------------
1867 
-- SN74H103N: Dual JK edge-triggered flipflop
1868 
-----------------------------------------------------------------------
1869 
component SN74H103N is
1870 
generic(
1871 
    tSETUP : time := 13 ns;     -- Setup time before clock
1872 
    tPLHCP : time := 15 ns;     -- Clock rising
1873 
    tPHLCP : time := 20 ns;     -- Clock falling
1874 
    tPLHSC : time := 12 ns;     -- S/C rising
1875 
    tPHLSC : time := 35 ns      -- S/C falling
1876 
);
1877 
port(
1878 
    X_1  : in    std_logic;  -- CP1\
1879 
    X_2  : in    std_logic;  -- CD1\
1880 
    X_3  : in    std_logic;  -- K1
1881 
    X_4  : inout std_logic;  -- Vcc
1882 
    X_5  : in    std_logic;  -- CP2\
1883 
    X_6  : in    std_logic;  -- CD2\
1884 
    X_7  : in    std_logic;  -- J2
1885 
    X_8  : out   std_logic;  -- Q2\
1886 
    X_9  : out   std_logic;  -- Q2
1887 
    X_10 : in    std_logic;  -- K2
1888 
    X_11 : inout std_logic;  -- GND
1889 
    X_12 : out   std_logic;  -- Q1
1890 
    X_13 : out   std_logic;  -- Q1\
1891 
    X_14 : in    std_logic   -- J1
1892 
);
1893 
end component SN74H103N;
1894 
 
1895 
-- SN74105N: JK flipflop with extra gating
1896 
 
1897 
-----------------------------------------------------------------------
1898 
-- SN74H106N: Dual JK edge-triggered flipflop
1899 
-----------------------------------------------------------------------
1900 
component SN74H106N is
1901 
generic(
1902 
    tSETUP : time := 13 ns;     -- Setup time before clock
1903 
    tPLHCP : time := 15 ns;     -- Clock rising
1904 
    tPHLCP : time := 20 ns;     -- Clock falling
1905 
    tPLHSC : time := 12 ns;     -- S/C rising
1906 
    tPHLSC : time := 35 ns      -- S/C falling
1907 
);
1908 
port(
1909 
    X_1  : in    std_logic;  -- CP1\
1910 
    X_2  : in    std_logic;  -- SD1\
1911 
    X_3  : in    std_logic;  -- CD1\
1912 
    X_4  : in    std_logic;  -- J1
1913 
    X_5  : inout std_logic;  -- Vcc
1914 
    X_6  : in    std_logic;  -- CP2\
1915 
    X_7  : in    std_logic;  -- SD2\
1916 
    X_8  : in    std_logic;  -- CD2\
1917 
    X_9  : in    std_logic;  -- J2
1918 
    X_10 : out   std_logic;  -- Q2\
1919 
    X_11 : out   std_logic;  -- Q2
1920 
    X_12 : in    std_logic;  -- K2
1921 
    X_13 : inout std_logic;  -- GND
1922 
    X_14 : out   std_logic;  -- Q1\
1923 
    X_15 : out   std_logic;  -- Q1
1924 
    X_16 : in    std_logic   -- K1
1925 
);
1926 
end component SN74H106N;
1927 
 
1928 
-----------------------------------------------------------------------
1929 
-- SN74LS107N: Dual JK flipflop
1930 
-----------------------------------------------------------------------
1931 
component SN74LS107N is
1932 
generic(
1933 
    tSETUP : time := 20 ns;     -- Setup time before clock
1934 
    tPLHCP : time := 20 ns;     -- Clock rising
1935 
    tPHLCP : time := 30 ns;     -- Clock falling
1936 
    tPLHSC : time := 20 ns;     -- S/C rising
1937 
    tPHLSC : time := 30 ns      -- S/C falling
1938 
);
1939 
port(
1940 
    X_1  : in    std_logic;  -- J1
1941 
    X_2  : out   std_logic;  -- Q1\
1942 
    X_3  : out   std_logic;  -- Q1
1943 
    X_4  : in    std_logic;  -- K1
1944 
    X_5  : out   std_logic;  -- Q2
1945 
    X_6  : out   std_logic;  -- Q2\
1946 
    X_7  : inout std_logic;  -- GND
1947 
    X_8  : in    std_logic;  -- J2
1948 
    X_9  : in    std_logic;  -- CP2\
1949 
    X_10 : in    std_logic;  -- CD2\
1950 
    X_11 : in    std_logic;  -- K2
1951 
    X_12 : in    std_logic;  -- CP1\
1952 
    X_13 : in    std_logic;  -- CD2\
1953 
    X_14 : inout std_logic   -- Vcc
1954 
);
1955 
end component SN74LS107N;
1956 
 
1957 
-----------------------------------------------------------------------
1958 
-- SN74H108N: Dual JK edge-triggered flipflop
1959 
-----------------------------------------------------------------------
1960 
component SN74H108N is
1961 
generic(
1962 
    tSETUP : time := 13 ns;     -- Setup time before clock
1963 
    tPLHCP : time := 15 ns;     -- Clock rising
1964 
    tPHLCP : time := 20 ns;     -- Clock falling
1965 
    tPLHSC : time := 12 ns;     -- S/C rising
1966 
    tPHLSC : time := 35 ns      -- S/C falling
1967 
);
1968 
port(
1969 
    X_1  : in    std_logic;  -- K1
1970 
    X_2  : out   std_logic;  -- Q1
1971 
    X_3  : out   std_logic;  -- Q1\
1972 
    X_4  : in    std_logic;  -- J1
1973 
    X_5  : out   std_logic;  -- Q2\
1974 
    X_6  : out   std_logic;  -- Q2
1975 
    X_7  : inout std_logic;  -- GND
1976 
    X_8  : in    std_logic;  -- K2
1977 
    X_9  : in    std_logic;  -- CP\
1978 
    X_10 : in    std_logic;  -- SD2\
1979 
    X_11 : in    std_logic;  -- J2
1980 
    X_12 : in    std_logic;  -- CD\
1981 
    X_13 : in    std_logic;  -- SD1\
1982 
    X_14 : inout std_logic   -- Vcc
1983 
);
1984 
end component SN74H108N;
1985 
 
1986 
-----------------------------------------------------------------------
1987 
-- SN74LS109N: Dual JK +ve edge-triggered flipflop
1988 
-----------------------------------------------------------------------
1989 
component SN74LS109N is
1990 
generic(
1991 
    tSETUP : time := 18 ns;     -- Setup time before clock
1992 
    tPLHCP : time := 25 ns;     -- Clock rising
1993 
    tPHLCP : time := 35 ns;     -- Clock falling
1994 
    tPLHSC : time := 15 ns;     -- S/C rising
1995 
    tPHLSC : time := 24 ns      -- S/C falling
1996 
);
1997 
port(
1998 
    X_1  : in    std_logic;  -- CD1\
1999 
    X_2  : in    std_logic;  -- J1
2000 
    X_3  : in    std_logic;  -- K1\
2001 
    X_4  : in    std_logic;  -- CP1
2002 
    X_5  : in    std_logic;  -- SD1\
2003 
    X_6  : out   std_logic;  -- Q1
2004 
    X_7  : out   std_logic;  -- Q1\
2005 
    X_8  : inout std_logic;  -- GND
2006 
    X_9  : out   std_logic;  -- Q2\
2007 
    X_10 : out   std_logic;  -- Q2
2008 
    X_11 : in    std_logic;  -- SD2\
2009 
    X_12 : in    std_logic;  -- CP2
2010 
    X_13 : in    std_logic;  -- K2\
2011 
    X_14 : in    std_logic;  -- J2
2012 
    X_15 : in    std_logic;  -- CD2\
2013 
    X_16 : inout std_logic   -- Vcc
2014 
);
2015 
end component SN74LS109N;
2016 
 
2017 
-----------------------------------------------------------------------
2018 
-- SN74LS112N: Dual JK -ve edge-triggered flipflop
2019 
-----------------------------------------------------------------------
2020 
component SN74LS112N is
2021 
generic(
2022 
    tSETUP : time := 20 ns;     -- Setup time before clock
2023 
    tPLHCP : time := 16 ns;     -- Clock rising
2024 
    tPHLCP : time := 24 ns;     -- Clock falling
2025 
    tPLHSC : time := 16 ns;     -- S/C rising
2026 
    tPHLSC : time := 24 ns      -- S/C falling
2027 
);
2028 
port(
2029 
    X_1  : in    std_logic;  -- CP1\
2030 
    X_2  : in    std_logic;  -- K1
2031 
    X_3  : in    std_logic;  -- J1
2032 
    X_4  : in    std_logic;  -- SD1\
2033 
    X_5  : out   std_logic;  -- Q1
2034 
    X_6  : out   std_logic;  -- Q1\
2035 
    X_7  : out   std_logic;  -- Q2\
2036 
    X_8  : inout std_logic;  -- GND
2037 
    X_9  : out   std_logic;  -- Q2
2038 
    X_10 : in    std_logic;  -- SD2\
2039 
    X_11 : in    std_logic;  -- J2
2040 
    X_12 : in    std_logic;  -- K2
2041 
    X_13 : in    std_logic;  -- CP2\
2042 
    X_14 : in    std_logic;  -- CD2\
2043 
    X_15 : in    std_logic;  -- CD1\
2044 
    X_16 : inout std_logic   -- Vcc
2045 
);
2046 
end component SN74LS112N;
2047 
 
2048 
-----------------------------------------------------------------------
2049 
-- SN74LS113N: Dual JK edge-triggered flipflop
2050 
-----------------------------------------------------------------------
2051 
component SN74LS113N is
2052 
generic(
2053 
    tSETUP : time := 20 ns;     -- Setup time before clock
2054 
    tPLHCP : time := 16 ns;     -- Clock rising
2055 
    tPHLCP : time := 24 ns;     -- Clock falling
2056 
    tPLHSC : time := 16 ns;     -- S/C rising
2057 
    tPHLSC : time := 24 ns      -- S/C falling
2058 
);
2059 
port(
2060 
    X_1  : in    std_logic;  -- CP1\
2061 
    X_2  : in    std_logic;  -- K1
2062 
    X_3  : in    std_logic;  -- J1
2063 
    X_4  : in    std_logic;  -- SD1\
2064 
    X_5  : out   std_logic;  -- Q1
2065 
    X_6  : out   std_logic;  -- Q1\
2066 
    X_7  : inout std_logic;  -- GND
2067 
    X_8  : out   std_logic;  -- Q2\
2068 
    X_9  : out   std_logic;  -- Q2
2069 
    X_10 : in    std_logic;  -- SD2\
2070 
    X_11 : in    std_logic;  -- J2
2071 
    X_12 : in    std_logic;  -- K2
2072 
    X_13 : in    std_logic;  -- CP2\
2073 
    X_14 : inout std_logic   -- Vcc
2074 
);
2075 
end component SN74LS113N;
2076 
 
2077 
-----------------------------------------------------------------------
2078 
-- SN74LS114N: Dual JK -ve edge-triggered flipflop
2079 
-----------------------------------------------------------------------
2080 
component SN74LS114N is
2081 
generic(
2082 
    tSETUP : time := 20 ns;     -- Setup time before clock
2083 
    tPLHCP : time := 16 ns;     -- Clock rising
2084 
    tPHLCP : time := 24 ns;     -- Clock falling
2085 
    tPLHSC : time := 16 ns;     -- S/C rising
2086 
    tPHLSC : time := 24 ns      -- S/C falling
2087 
);
2088 
port(
2089 
    X_1  : in    std_logic;  -- CD\
2090 
    X_2  : in    std_logic;  -- K1
2091 
    X_3  : in    std_logic;  -- J1
2092 
    X_4  : in    std_logic;  -- SD1\
2093 
    X_5  : out   std_logic;  -- Q1
2094 
    X_6  : out   std_logic;  -- Q1\
2095 
    X_7  : inout std_logic;  -- GND
2096 
    X_8  : out   std_logic;  -- Q2\
2097 
    X_9  : out   std_logic;  -- Q2
2098 
    X_10 : in    std_logic;  -- SD2\
2099 
    X_11 : in    std_logic;  -- J2
2100 
    X_12 : in    std_logic;  -- K2
2101 
    X_13 : in    std_logic;  -- CP\
2102 
    X_14 : inout std_logic   -- Vcc
2103 
);
2104 
end component SN74LS114N;
2105 
 
2106 
-----------------------------------------------------------------------
2107 
-- SN74121N: Monostable multivibrator
2108 
--           Tw = 0.69 * R * C
2109 
-----------------------------------------------------------------------
2110 
component SN74121N is
2111 
generic(
2112 
    W  : time := 100 us      -- Pulse width
2113 
);
2114 
port(
2115 
    X_1  : out   std_logic;  -- Q\
2116 
                             --
2117 
    X_3  : in    std_logic;  -- A1\
2118 
    X_4  : in    std_logic;  -- A2\
2119 
    X_5  : in    std_logic;  -- B
2120 
    X_6  : out   std_logic;  -- Q
2121 
    X_7  : inout std_logic;  -- GND
2122 
                             --
2123 
    X_9  : inout std_logic;  -- Rint (open for simulation)
2124 
    X_10 : inout std_logic;  -- Cx
2125 
    X_11 : inout std_logic;  -- RxCx
2126 
                             --
2127 
                             --
2128 
    X_14 : inout std_logic   -- Vcc
2129 
);
2130 
end component SN74121N;
2131 
 
2132 
-----------------------------------------------------------------------
2133 
-- SN74122N: Retriggerable resettable monostable multivibrator
2134 
--           Tw = 0.32 * R * X * (1.0 + 0.7/R)
2135 
-----------------------------------------------------------------------
2136 
component SN74122N is
2137 
generic(
2138 
    W  : time := 100 us      -- Pulse width
2139 
);
2140 
port(
2141 
    X_1  : in    std_logic;  -- A1\
2142 
    X_2  : in    std_logic;  -- A2\
2143 
    X_3  : in    std_logic;  -- B1
2144 
    X_4  : in    std_logic;  -- B2
2145 
    X_5  : in    std_logic;  -- CD\
2146 
    X_6  : out   std_logic;  -- Q\
2147 
    X_7  : inout std_logic;  -- GND
2148 
    X_8  : out   std_logic;  -- Q
2149 
    X_9  : inout std_logic;  -- Rint
2150 
                             --
2151 
    X_11 : inout std_logic;  -- Cx
2152 
                             --
2153 
    X_13 : inout std_logic;  -- RxCx
2154 
    X_14 : inout std_logic   -- Vcc
2155 
);
2156 
end component SN74122N;
2157 
 
2158 
-----------------------------------------------------------------------
2159 
-- SN74123N: Dual retriggerable resettable monostable multivibrator
2160 
--           Tw = 0.28 * R * C * (1.0 + 0.7/R)
2161 
-----------------------------------------------------------------------
2162 
component SN74123N is
2163 
generic(
2164 
    W1 : time := 100 us;     -- Pulse widths
2165 
    W2 : time := 100 us
2166 
);
2167 
port(
2168 
    X_1  : in    std_logic;  -- A1\
2169 
    X_2  : in    std_logic;  -- B1
2170 
    X_3  : in    std_logic;  -- CD1\
2171 
    X_4  : out   std_logic;  -- Q1\
2172 
    X_5  : out   std_logic;  -- Q2
2173 
    X_6  : inout std_logic;  -- Cx2
2174 
    X_7  : inout std_logic;  -- Rx2Cx2
2175 
    X_8  : inout std_logic;  -- GND
2176 
    X_9  : in    std_logic;  -- A2\
2177 
    X_10 : in    std_logic;  -- B2
2178 
    X_11 : in    std_logic;  -- CD2\
2179 
    X_12 : out   std_logic;  -- Q2\
2180 
    X_13 : out   std_logic;  -- Q1
2181 
    X_14 : inout std_logic;  -- Cx1
2182 
    X_15 : inout std_logic;  -- Rx1Cx1
2183 
    X_16 : inout std_logic   -- Vcc
2184 
);
2185 
end component SN74123N;
2186 
 
2187 
-----------------------------------------------------------------------
2188 
-- SN74LS125N: Quad bus buffer (3-state outputs)
2189 
-----------------------------------------------------------------------
2190 
component SN74LS125N is
2191 
generic(
2192 
    tPLH : time := 15 ns;
2193 
    tPHL : time := 18 ns;
2194 
    tPHZ : time := 25 ns;
2195 
    tPLZ : time := 25 ns;
2196 
    tPHE : time := 16 ns;
2197 
    tPLE : time := 25 ns
2198 
);
2199 
port(
2200 
    X_1  : in    std_logic;  -- E1\
2201 
    X_2  : in    std_logic;  -- D1
2202 
    X_3  : out   std_logic;  -- Q1
2203 
    X_4  : in    std_logic;  -- E2\
2204 
    X_5  : in    std_logic;  -- D2
2205 
    X_6  : out   std_logic;  -- Q2
2206 
    X_7  : inout std_logic;  -- GND
2207 
    X_8  : out   std_logic;  -- Q3
2208 
    X_9  : in    std_logic;  -- D3
2209 
    X_10 : in    std_logic;  -- E3\
2210 
    X_11 : out   std_logic;  -- Q4
2211 
    X_12 : in    std_logic;  -- D4
2212 
    X_13 : in    std_logic;  -- E4\
2213 
    X_14 : inout std_logic   -- Vcc
2214 
);
2215 
end component SN74LS125N;
2216 
 
2217 
-----------------------------------------------------------------------
2218 
-- SN74LS126N: Quad bus buffer (3-state outputs)
2219 
-----------------------------------------------------------------------
2220 
component SN74LS126N is
2221 
generic(
2222 
    tPLH : time := 15 ns;
2223 
    tPHL : time := 18 ns;
2224 
    tPHZ : time := 30 ns;
2225 
    tPLZ : time := 30 ns;
2226 
    tPHE : time := 20 ns;
2227 
    tPLE : time := 30 ns
2228 
);
2229 
port(
2230 
    X_1  : in    std_logic;  -- E1
2231 
    X_2  : in    std_logic;  -- D1
2232 
    X_3  : out   std_logic;  -- Q1
2233 
    X_4  : in    std_logic;  -- E2
2234 
    X_5  : in    std_logic;  -- D2
2235 
    X_6  : out   std_logic;  -- Q2
2236 
    X_7  : inout std_logic;  -- GND
2237 
    X_8  : out   std_logic;  -- Q3
2238 
    X_9  : in    std_logic;  -- D3
2239 
    X_10 : in    std_logic;  -- E3
2240 
    X_11 : out   std_logic;  -- Q4
2241 
    X_12 : in    std_logic;  -- D4
2242 
    X_13 : in    std_logic;  -- E4
2243 
    X_14 : inout std_logic   -- Vcc
2244 
);
2245 
end component SN74LS126N;
2246 
 
2247 
-----------------------------------------------------------------------
2248 
-- SN74LS132N: Quad 2-input Schmitt trigger NAND gate
2249 
-----------------------------------------------------------------------
2250 
component SN74LS132N is
2251 
generic(
2252 
    tPLH : time := 20 ns;
2253 
    tPHL : time := 20 ns
2254 
);
2255 
port(
2256 
    X_1  : in    std_logic;  -- 1A
2257 
    X_2  : in    std_logic;  -- 1B
2258 
    X_3  : out   std_logic;  -- 1Y\
2259 
    X_4  : in    std_logic;  -- 2A
2260 
    X_5  : in    std_logic;  -- 2B
2261 
    X_6  : out   std_logic;  -- 2Y\
2262 
    X_7  : inout std_logic;  -- GND
2263 
    X_8  : out   std_logic;  -- 3Y\
2264 
    X_9  : in    std_logic;  -- 3B
2265 
    X_10 : in    std_logic;  -- 3A
2266 
    X_11 : out   std_logic;  -- 4Y\
2267 
    X_12 : in    std_logic;  -- 4B
2268 
    X_13 : in    std_logic;  -- 4A
2269 
    X_14 : inout std_logic   -- Vcc
2270 
);
2271 
end component SN74LS132N;
2272 
 
2273 
-----------------------------------------------------------------------
2274 
-- SN74LS133N: 13-input NAND gate
2275 
-----------------------------------------------------------------------
2276 
component SN74LS133N is
2277 
generic(
2278 
    tPLH : time := 15 ns;
2279 
    tPHL : time := 38 ns
2280 
);
2281 
port(
2282 
    X_1  : in    std_logic;  -- 1A
2283 
    X_2  : in    std_logic;  -- 1B
2284 
    X_3  : in    std_logic;  -- 1C
2285 
    X_4  : in    std_logic;  -- 1D
2286 
    X_5  : in    std_logic;  -- 1E
2287 
    X_6  : in    std_logic;  -- 1F
2288 
    X_7  : in    std_logic;  -- 1G
2289 
    X_8  : inout std_logic;  -- GND
2290 
    X_9  : out   std_logic;  -- 1Y\
2291 
    X_10 : in    std_logic;  -- 1H
2292 
    X_11 : in    std_logic;  -- 1J
2293 
    X_12 : in    std_logic;  -- 1K
2294 
    X_13 : in    std_logic;  -- 1L
2295 
    X_14 : in    std_logic;  -- 1M
2296 
    X_15 : in    std_logic;  -- 1N
2297 
    X_16 : inout std_logic   -- Vcc
2298 
);
2299 
end component SN74LS133N;
2300 
 
2301 
-----------------------------------------------------------------------
2302 
-- SN74S134N: 12-input NAND gate (3-state output)
2303 
-----------------------------------------------------------------------
2304 
component SN74S134N is
2305 
generic(
2306 
    tPLH : time :=  6.0 ns;
2307 
    tPHL : time :=  7.5 ns;
2308 
    tPZH : time := 19.5 ns;
2309 
    tPZL : time := 21.0 ns;
2310 
    tPHZ : time :=  8.5 ns;
2311 
    tPLZ : time := 14.0 ns
2312 
);
2313 
port(
2314 
    X_1  : in    std_logic;  -- 1A
2315 
    X_2  : in    std_logic;  -- 1B
2316 
    X_3  : in    std_logic;  -- 1C
2317 
    X_4  : in    std_logic;  -- 1D
2318 
    X_5  : in    std_logic;  -- 1E
2319 
    X_6  : in    std_logic;  -- 1F
2320 
    X_7  : in    std_logic;  -- 1G
2321 
    X_8  : inout std_logic;  -- GND
2322 
    X_9  : out   std_logic;  -- 1Y\
2323 
    X_10 : in    std_logic;  -- 1H
2324 
    X_11 : in    std_logic;  -- 1J
2325 
    X_12 : in    std_logic;  -- 1K
2326 
    X_13 : in    std_logic;  -- 1L
2327 
    X_14 : in    std_logic;  -- 1M
2328 
    X_15 : in    std_logic;  -- EB
2329 
    X_16 : inout std_logic   -- Vcc
2330 
);
2331 
end component SN74S134N;
2332 
 
2333 
-----------------------------------------------------------------------
2334 
-- SN74S135N: Quad XOR/NOR gate
2335 
-----------------------------------------------------------------------
2336 
component SN74S135N is
2337 
generic(
2338 
    tPXX : time := 13 ns
2339 
);
2340 
port(
2341 
    X_1  : in    std_logic;  -- A1
2342 
    X_2  : in    std_logic;  -- B1
2343 
    X_3  : out   std_logic;  -- Y1
2344 
    X_4  : in    std_logic;  -- C12
2345 
    X_5  : in    std_logic;  -- A2
2346 
    X_6  : in    std_logic;  -- B2
2347 
    X_7  : out   std_logic;  -- Y2
2348 
    X_8  : inout std_logic;  -- GND
2349 
    X_9  : out   std_logic;  -- Y3
2350 
    X_10 : in    std_logic;  -- B3
2351 
    X_11 : in    std_logic;  -- A3
2352 
    X_12 : in    std_logic;  -- C34
2353 
    X_13 : out   std_logic;  -- Y4
2354 
    X_14 : in    std_logic;  -- B4
2355 
    X_15 : in    std_logic;  -- A4
2356 
    X_16 : inout std_logic   -- Vcc
2357 
);
2358 
end component SN74S135N;
2359 
 
2360 
-----------------------------------------------------------------------
2361 
-- SN74LS136N: Quad 2-input XOR gate (open collector)
2362 
-----------------------------------------------------------------------
2363 
component SN74LS136N is
2364 
generic(
2365 
    tPLH : time := 30 ns;
2366 
    tPHL : time := 30 ns
2367 
);
2368 
port(
2369 
    X_1  : in    std_logic;  -- 1A
2370 
    X_2  : in    std_logic;  -- 1B
2371 
    X_3  : out   std_logic;  -- 1Y\
2372 
    X_4  : in    std_logic;  -- 2A
2373 
    X_5  : in    std_logic;  -- 2B
2374 
    X_6  : out   std_logic;  -- 2Y\
2375 
    X_7  : inout std_logic;  -- GND
2376 
    X_8  : out   std_logic;  -- 3Y\
2377 
    X_9  : in    std_logic;  -- 3B
2378 
    X_10 : in    std_logic;  -- 3A
2379 
    X_11 : out   std_logic;  -- 4Y\
2380 
    X_12 : in    std_logic;  -- 4B
2381 
    X_13 : in    std_logic;  -- 4A
2382 
    X_14 : inout std_logic   -- Vcc
2383 
);
2384 
end component SN74LS136N;
2385 
 
2386 
-----------------------------------------------------------------------
2387 
-- SN74LS137N: 1-of-8 decoder/demultiplexer (input latches)
2388 
-----------------------------------------------------------------------
2389 
component SN74LS137N is
2390 
generic(
2391 
    tPLH : time := 12 ns;
2392 
    tPHL : time := 20 ns
2393 
);
2394 
port(
2395 
    X_1  : in    std_logic;  -- A0
2396 
    X_2  : in    std_logic;  -- A1
2397 
    X_3  : in    std_logic;  -- A2
2398 
    X_4  : in    std_logic;  -- LE\
2399 
    X_5  : in    std_logic;  -- E1\
2400 
    X_6  : in    std_logic;  -- E2
2401 
    X_7  : out   std_logic;  -- O7\
2402 
    X_8  : inout std_logic;  -- GND
2403 
    X_9  : out   std_logic;  -- O6\
2404 
    X_10 : out   std_logic;  -- O5\
2405 
    X_11 : out   std_logic;  -- O4\
2406 
    X_12 : out   std_logic;  -- O3\
2407 
    X_13 : out   std_logic;  -- O2\
2408 
    X_14 : out   std_logic;  -- O1\
2409 
    X_15 : out   std_logic;  -- O0\
2410 
    X_16 : inout std_logic   -- Vcc
2411 
);
2412 
end component SN74LS137N;
2413 
 
2414 
-----------------------------------------------------------------------
2415 
-- SN74LS138N: 1-of-8 decoder/demultiplexer
2416 
-----------------------------------------------------------------------
2417 
component SN74LS138N is
2418 
generic(
2419 
    tPLH : time := 18 ns;
2420 
    tPHL : time := 28 ns
2421 
);
2422 
port(
2423 
    X_1  : in    std_logic;  -- A0
2424 
    X_2  : in    std_logic;  -- A1
2425 
    X_3  : in    std_logic;  -- A2
2426 
    X_4  : in    std_logic;  -- E1\
2427 
    X_5  : in    std_logic;  -- E2\
2428 
    X_6  : in    std_logic;  -- E3
2429 
    X_7  : out   std_logic;  -- O7\
2430 
    X_8  : inout std_logic;  -- GND
2431 
    X_9  : out   std_logic;  -- O6\
2432 
    X_10 : out   std_logic;  -- O5\
2433 
    X_11 : out   std_logic;  -- O4\
2434 
    X_12 : out   std_logic;  -- O3\
2435 
    X_13 : out   std_logic;  -- O2\
2436 
    X_14 : out   std_logic;  -- O1\
2437 
    X_15 : out   std_logic;  -- O0\
2438 
    X_16 : inout std_logic   -- Vcc
2439 
);
2440 
end component SN74LS138N;
2441 
 
2442 
-----------------------------------------------------------------------
2443 
-- SN74LS139N: Dual 1-of-4 decoder
2444 
-----------------------------------------------------------------------
2445 
component SN74LS139N is
2446 
generic(
2447 
    tPLH : time := 18 ns;
2448 
    tPHL : time := 28 ns
2449 
);
2450 
port(
2451 
    X_1  : in    std_logic;  -- EA\
2452 
    X_2  : in    std_logic;  -- A0A
2453 
    X_3  : in    std_logic;  -- A1A
2454 
    X_4  : out   std_logic;  -- O0A\
2455 
    X_5  : out   std_logic;  -- O1A\
2456 
    X_6  : out   std_logic;  -- O2A\
2457 
    X_7  : out   std_logic;  -- O3A\
2458 
    X_8  : inout std_logic;  -- GND
2459 
    X_9  : out   std_logic;  -- O3B\
2460 
    X_10 : out   std_logic;  -- O2B\
2461 
    X_11 : out   std_logic;  -- O1B\
2462 
    X_12 : out   std_logic;  -- O0B\
2463 
    X_13 : in    std_logic;  -- A1B
2464 
    X_14 : in    std_logic;  -- A0B
2465 
    X_15 : in    std_logic;  -- EB\
2466 
    X_16 : inout std_logic   -- Vcc
2467 
);
2468 
end component SN74LS139N;
2469 
 
2470 
-----------------------------------------------------------------------
2471 
-- SN74S140N: Dual 4-input NAND line driver
2472 
-----------------------------------------------------------------------
2473 
component SN74S140N is
2474 
generic(
2475 
    tPLH : time := 6.5 ns;
2476 
    tPHL : time := 6.5 ns
2477 
);
2478 
port(
2479 
    X_1  : in    std_logic;  -- 1A
2480 
    X_2  : in    std_logic;  -- 1B
2481 
                             --
2482 
    X_4  : in    std_logic;  -- 1C
2483 
    X_5  : in    std_logic;  -- 1D
2484 
    X_6  : out   std_logic;  -- 1Y\
2485 
    X_7  : inout std_logic;  -- GND
2486 
    X_8  : out   std_logic;  -- 2Y\
2487 
    X_9  : in    std_logic;  -- 2D
2488 
    X_10 : in    std_logic;  -- 2C
2489 
                             --
2490 
    X_12 : in    std_logic;  -- 2B
2491 
    X_13 : in    std_logic;  -- 2A
2492 
    X_14 : inout std_logic   -- Vcc
2493 
);
2494 
end component SN74S140N;
2495 
 
2496 
-- SN74LS141N: 1-of-10 Nixie decoder/driver (open collector)
2497 
 
2498 
-----------------------------------------------------------------------
2499 
-- SN74145N: 1-of-10 decoder/driver (open collector)
2500 
-----------------------------------------------------------------------
2501 
component SN74145N is
2502 
generic(
2503 
    tPLH : time := 50 ns;
2504 
    tPHL : time := 50 ns
2505 
);
2506 
port(
2507 
    X_1  : out   std_logic;  -- Q0\
2508 
    X_2  : out   std_logic;  -- Q1\
2509 
    X_3  : out   std_logic;  -- Q2\
2510 
    X_4  : out   std_logic;  -- Q3\
2511 
    X_5  : out   std_logic;  -- Q4\
2512 
    X_6  : out   std_logic;  -- Q5\
2513 
    X_7  : out   std_logic;  -- Q6\
2514 
    X_8  : inout std_logic;  -- GND
2515 
    X_9  : out   std_logic;  -- Q7\
2516 
    X_10 : out   std_logic;  -- Q8\
2517 
    X_11 : out   std_logic;  -- Q9\
2518 
    X_12 : in    std_logic;  -- A3
2519 
    X_13 : in    std_logic;  -- A2
2520 
    X_14 : in    std_logic;  -- A1
2521 
    X_15 : in    std_logic;  -- A0
2522 
    X_16 : inout std_logic   -- Vcc
2523 
);
2524 
end component SN74145N;
2525 
 
2526 
-- SN74LS147N: 10-to-4 line priority encoder
2527 
-- SN74LS148N: 8-to-3 line priority encoder
2528 
 
2529 
-----------------------------------------------------------------------
2530 
-- SN74150N: 16-input multiplexer
2531 
-----------------------------------------------------------------------
2532 
component SN74150N is
2533 
generic(
2534 
    tPLH : time := 35 ns;
2535 
    tPHL : time := 33 ns
2536 
);
2537 
port(
2538 
    X_1  : in    std_logic;  -- I7
2539 
    X_2  : in    std_logic;  -- I6
2540 
    X_3  : in    std_logic;  -- I5
2541 
    X_4  : in    std_logic;  -- I4
2542 
    X_5  : in    std_logic;  -- I3
2543 
    X_6  : in    std_logic;  -- I2
2544 
    X_7  : in    std_logic;  -- I1
2545 
    X_8  : in    std_logic;  -- I0
2546 
    X_9  : in    std_logic;  -- E\
2547 
    X_10 : out   std_logic;  -- Z\
2548 
    X_11 : in    std_logic;  -- S3
2549 
    X_12 : inout std_logic;  -- GND
2550 
    X_13 : in    std_logic;  -- S2
2551 
    X_14 : in    std_logic;  -- S1
2552 
    X_15 : in    std_logic;  -- S0
2553 
    X_16 : in    std_logic;  -- I15
2554 
    X_17 : in    std_logic;  -- I14
2555 
    X_18 : in    std_logic;  -- I13
2556 
    X_19 : in    std_logic;  -- I12
2557 
    X_20 : in    std_logic;  -- I11
2558 
    X_21 : in    std_logic;  -- I10
2559 
    X_22 : in    std_logic;  -- I9
2560 
    X_23 : in    std_logic;  -- I8
2561 
    X_24 : inout std_logic   -- Vcc
2562 
);
2563 
end component SN74150N;
2564 
 
2565 
-----------------------------------------------------------------------
2566 
-- SN74LS151N: 8-input multiplexer
2567 
-----------------------------------------------------------------------
2568 
component SN74LS151N is
2569 
generic(
2570 
    tPLHZ  : time := 48 ns;
2571 
    tPHLZ  : time := 32 ns;
2572 
    tPLHZB : time := 24 ns;
2573 
    tPHLZB : time := 34 ns
2574 
);
2575 
port(
2576 
    X_1  : in    std_logic;  -- I3
2577 
    X_2  : in    std_logic;  -- I2
2578 
    X_3  : in    std_logic;  -- I1
2579 
    X_4  : in    std_logic;  -- I0
2580 
    X_5  : out   std_logic;  -- Z
2581 
    X_6  : out   std_logic;  -- Z\
2582 
    X_7  : in    std_logic;  -- E\
2583 
    X_8  : inout std_logic;  -- GND
2584 
    X_9  : in    std_logic;  -- S2
2585 
    X_10 : in    std_logic;  -- S1
2586 
    X_11 : in    std_logic;  -- S0
2587 
    X_12 : in    std_logic;  -- I7
2588 
    X_13 : in    std_logic;  -- I6
2589 
    X_14 : in    std_logic;  -- I5
2590 
    X_15 : in    std_logic;  -- I4
2591 
    X_16 : inout std_logic   -- Vcc
2592 
);
2593 
end component SN74LS151N;
2594 
 
2595 
-- SN74LS152N: 8-input multiplexer (flatpack only, no DIP)
2596 
 
2597 
-----------------------------------------------------------------------
2598 
-- SN74LS153N: Dual 4-input multiplexer (common selects)
2599 
-----------------------------------------------------------------------
2600 
component SN74LS153N is
2601 
generic(
2602 
    tPLH : time := 29 ns;
2603 
    tPHL : time := 32 ns
2604 
);
2605 
port(
2606 
    X_1  : in    std_logic;  -- EA\
2607 
    X_2  : in    std_logic;  -- S1
2608 
    X_3  : in    std_logic;  -- I3A
2609 
    X_4  : in    std_logic;  -- I2A
2610 
    X_5  : in    std_logic;  -- I1A
2611 
    X_6  : in    std_logic;  -- I0A
2612 
    X_7  : out   std_logic;  -- ZA
2613 
    X_8  : inout std_logic;  -- GND
2614 
    X_9  : out   std_logic;  -- ZB
2615 
    X_10 : in    std_logic;  -- I0B
2616 
    X_11 : in    std_logic;  -- I1B
2617 
    X_12 : in    std_logic;  -- I2B
2618 
    X_13 : in    std_logic;  -- I3B
2619 
    X_14 : in    std_logic;  -- S0
2620 
    X_15 : in    std_logic;  -- EB\
2621 
    X_16 : inout std_logic   -- Vcc
2622 
);
2623 
end component SN74LS153N;
2624 
 
2625 
-----------------------------------------------------------------------
2626 
-- SN74154N: 1-of-16 decoder/demultiplexer
2627 
-----------------------------------------------------------------------
2628 
component SN74154N is
2629 
generic(
2630 
    tPLH : time := 31 ns;
2631 
    tPHL : time := 28 ns
2632 
);
2633 
port(
2634 
    X_1  : out   std_logic;  -- O0\
2635 
    X_2  : out   std_logic;  -- O1\
2636 
    X_3  : out   std_logic;  -- O2\
2637 
    X_4  : out   std_logic;  -- O3\
2638 
    X_5  : out   std_logic;  -- O4\
2639 
    X_6  : out   std_logic;  -- O5\
2640 
    X_7  : out   std_logic;  -- O6\
2641 
    X_8  : out   std_logic;  -- O7\
2642 
    X_9  : out   std_logic;  -- O8\
2643 
    X_10 : out   std_logic;  -- O9\
2644 
    X_11 : out   std_logic;  -- O10\
2645 
    X_12 : inout std_logic;  -- GND
2646 
    X_13 : out   std_logic;  -- O11\
2647 
    X_14 : out   std_logic;  -- O12\
2648 
    X_15 : out   std_logic;  -- O13\
2649 
    X_16 : out   std_logic;  -- O14\
2650 
    X_17 : out   std_logic;  -- O15\
2651 
    X_18 : in    std_logic;  -- E0\
2652 
    X_19 : in    std_logic;  -- E1\
2653 
    X_20 : in    std_logic;  -- A3
2654 
    X_21 : in    std_logic;  -- A2
2655 
    X_22 : in    std_logic;  -- A1
2656 
    X_23 : in    std_logic;  -- A0
2657 
    X_24 : inout std_logic   -- Vcc
2658 
);
2659 
end component SN74154N;
2660 
 
2661 
-----------------------------------------------------------------------
2662 
-- SN74LS155N: Dual 1-of-4 decoder/demultiplexer
2663 
-----------------------------------------------------------------------
2664 
component SN74LS155N is
2665 
generic(
2666 
    tPLH : time := 18 ns;
2667 
    tPHL : time := 27 ns
2668 
);
2669 
port(
2670 
    X_1  : in    std_logic;  -- EA
2671 
    X_2  : in    std_logic;  -- EA\
2672 
    X_3  : in    std_logic;  -- A1
2673 
    X_4  : out   std_logic;  -- O3A\
2674 
    X_5  : out   std_logic;  -- O2A\
2675 
    X_6  : out   std_logic;  -- O1A\
2676 
    X_7  : out   std_logic;  -- O0A\
2677 
    X_8  : inout std_logic;  -- GND
2678 
    X_9  : out   std_logic;  -- O0B\
2679 
    X_10 : out   std_logic;  -- O1B\
2680 
    X_11 : out   std_logic;  -- O2B\
2681 
    X_12 : out   std_logic;  -- O3B\
2682 
    X_13 : in    std_logic;  -- A0
2683 
    X_14 : in    std_logic;  -- EB2\
2684 
    X_15 : in    std_logic;  -- EB1\
2685 
    X_16 : inout std_logic   -- Vcc
2686 
);
2687 
end component SN74LS155N;
2688 
 
2689 
-----------------------------------------------------------------------
2690 
-- SN74LS156N: Dual 1-of-4 decoder/demultiplexer (open collector)
2691 
-----------------------------------------------------------------------
2692 
component SN74LS156N is
2693 
generic(
2694 
    tPLH : time := 34 ns;
2695 
    tPHL : time := 34 ns
2696 
);
2697 
port(
2698 
    X_1  : in    std_logic;  -- EA
2699 
    X_2  : in    std_logic;  -- EA\
2700 
    X_3  : in    std_logic;  -- A1
2701 
    X_4  : out   std_logic;  -- O3A\
2702 
    X_5  : out   std_logic;  -- O2A\
2703 
    X_6  : out   std_logic;  -- O1A\
2704 
    X_7  : out   std_logic;  -- O0A\
2705 
    X_8  : inout std_logic;  -- GND
2706 
    X_9  : out   std_logic;  -- O0B\
2707 
    X_10 : out   std_logic;  -- O1B\
2708 
    X_11 : out   std_logic;  -- O2B\
2709 
    X_12 : out   std_logic;  -- O3B\
2710 
    X_13 : in    std_logic;  -- A0
2711 
    X_14 : in    std_logic;  -- EB2\
2712 
    X_15 : in    std_logic;  -- EB1\
2713 
    X_16 : inout std_logic   -- Vcc
2714 
);
2715 
end component SN74LS156N;
2716 
 
2717 
-----------------------------------------------------------------------
2718 
-- SN74LS157N: Quad 2-input multiplexer (common select)
2719 
-----------------------------------------------------------------------
2720 
component SN74LS157N is
2721 
generic(
2722 
    tPLH : time := 26 ns;
2723 
    tPHL : time := 24 ns
2724 
);
2725 
port(
2726 
    X_1  : in    std_logic;  -- S
2727 
    X_2  : in    std_logic;  -- I0A
2728 
    X_3  : in    std_logic;  -- I1A
2729 
    X_4  : out   std_logic;  -- ZA
2730 
    X_5  : in    std_logic;  -- I0B
2731 
    X_6  : in    std_logic;  -- I1B
2732 
    X_7  : out   std_logic;  -- ZB
2733 
    X_8  : inout std_logic;  -- GND
2734 
    X_9  : out   std_logic;  -- ZD
2735 
    X_10 : in    std_logic;  -- I1D
2736 
    X_11 : in    std_logic;  -- I0D
2737 
    X_12 : out   std_logic;  -- ZC
2738 
    X_13 : in    std_logic;  -- I1C
2739 
    X_14 : in    std_logic;  -- I0C
2740 
    X_15 : in    std_logic;  -- E\
2741 
    X_16 : inout std_logic   -- Vcc
2742 
);
2743 
end component SN74LS157N;
2744 
 
2745 
-----------------------------------------------------------------------
2746 
-- SN74LS158N: Quad 2-input multiplexer (common select: inverting)
2747 
-----------------------------------------------------------------------
2748 
component SN74LS158N is
2749 
generic(
2750 
    tPLH : time := 20 ns;
2751 
    tPHL : time := 24 ns
2752 
);
2753 
port(
2754 
    X_1  : in    std_logic;  -- S
2755 
    X_2  : in    std_logic;  -- I0A
2756 
    X_3  : in    std_logic;  -- I1A
2757 
    X_4  : out   std_logic;  -- ZA\
2758 
    X_5  : in    std_logic;  -- I0B
2759 
    X_6  : in    std_logic;  -- I1B
2760 
    X_7  : out   std_logic;  -- ZB\
2761 
    X_8  : inout std_logic;  -- GND
2762 
    X_9  : out   std_logic;  -- ZD\
2763 
    X_10 : in    std_logic;  -- I1D
2764 
    X_11 : in    std_logic;  -- I0D
2765 
    X_12 : out   std_logic;  -- ZC\
2766 
    X_13 : in    std_logic;  -- I1C
2767 
    X_14 : in    std_logic;  -- I0C
2768 
    X_15 : in    std_logic;  -- E\
2769 
    X_16 : inout std_logic   -- Vcc
2770 
);
2771 
end component SN74LS158N;
2772 
 
2773 
-----------------------------------------------------------------------
2774 
-- SN74LS160N: Synchronous presettable BCD decade counter
2775 
-----------------------------------------------------------------------
2776 
component SN74LS160N is
2777 
generic(
2778 
    tPLHT : time := 25 ns;
2779 
    tPHLT : time := 23 ns;
2780 
    tPLHQ : time := 24 ns;
2781 
    tPHLQ : time := 27 ns
2782 
);
2783 
port(
2784 
    X_1  : in    std_logic;  -- R\
2785 
    X_2  : in    std_logic;  -- CP
2786 
    X_3  : in    std_logic;  -- P0
2787 
    X_4  : in    std_logic;  -- P1
2788 
    X_5  : in    std_logic;  -- P2
2789 
    X_6  : in    std_logic;  -- P3
2790 
    X_7  : in    std_logic;  -- CEP
2791 
    X_8  : inout std_logic;  -- GND
2792 
    X_9  : in    std_logic;  -- PE\
2793 
    X_10 : in    std_logic;  -- CET
2794 
    X_11 : out   std_logic;  -- Q3
2795 
    X_12 : out   std_logic;  -- Q2
2796 
    X_13 : out   std_logic;  -- Q1
2797 
    X_14 : out   std_logic;  -- Q0
2798 
    X_15 : out   std_logic;  -- TC
2799 
    X_16 : inout std_logic   -- Vcc
2800 
);
2801 
end component SN74LS160N;
2802 
 
2803 
-----------------------------------------------------------------------
2804 
-- SN74LS161N: Synchronous presettable 4-bit binary counter
2805 
-----------------------------------------------------------------------
2806 
component SN74LS161N is
2807 
generic(
2808 
    tPLHT : time := 25 ns;
2809 
    tPHLT : time := 23 ns;
2810 
    tPLHQ : time := 24 ns;
2811 
    tPHLQ : time := 27 ns
2812 
);
2813 
port(
2814 
    X_1  : in    std_logic;  -- R\
2815 
    X_2  : in    std_logic;  -- CP
2816 
    X_3  : in    std_logic;  -- P0
2817 
    X_4  : in    std_logic;  -- P1
2818 
    X_5  : in    std_logic;  -- P2
2819 
    X_6  : in    std_logic;  -- P3
2820 
    X_7  : in    std_logic;  -- CEP
2821 
    X_8  : inout std_logic;  -- GND
2822 
    X_9  : in    std_logic;  -- PE\
2823 
    X_10 : in    std_logic;  -- CET
2824 
    X_11 : out   std_logic;  -- Q3
2825 
    X_12 : out   std_logic;  -- Q2
2826 
    X_13 : out   std_logic;  -- Q1
2827 
    X_14 : out   std_logic;  -- Q0
2828 
    X_15 : out   std_logic;  -- TC
2829 
    X_16 : inout std_logic   -- Vcc
2830 
);
2831 
end component SN74LS161N;
2832 
 
2833 
-----------------------------------------------------------------------
2834 
-- SN74LS162N: Synchronous presettable BCD decade counter
2835 
-----------------------------------------------------------------------
2836 
component SN74LS162N is
2837 
generic(
2838 
    tPLHT : time := 25 ns;
2839 
    tPHLT : time := 23 ns;
2840 
    tPLHQ : time := 24 ns;
2841 
    tPHLQ : time := 27 ns
2842 
);
2843 
port(
2844 
    X_1  : in    std_logic;  -- R\
2845 
    X_2  : in    std_logic;  -- CP
2846 
    X_3  : in    std_logic;  -- P0
2847 
    X_4  : in    std_logic;  -- P1
2848 
    X_5  : in    std_logic;  -- P2
2849 
    X_6  : in    std_logic;  -- P3
2850 
    X_7  : in    std_logic;  -- CEP
2851 
    X_8  : inout std_logic;  -- GND
2852 
    X_9  : in    std_logic;  -- PE\
2853 
    X_10 : in    std_logic;  -- CET
2854 
    X_11 : out   std_logic;  -- Q3
2855 
    X_12 : out   std_logic;  -- Q2
2856 
    X_13 : out   std_logic;  -- Q1
2857 
    X_14 : out   std_logic;  -- Q0
2858 
    X_15 : out   std_logic;  -- TC
2859 
    X_16 : inout std_logic   -- Vcc
2860 
);
2861 
end component SN74LS162N;
2862 
 
2863 
-----------------------------------------------------------------------
2864 
-- SN74LS163N: Synchronous presettable 4-bit binary counter
2865 
-----------------------------------------------------------------------
2866 
component SN74LS163N is
2867 
generic(
2868 
    tPLHT : time := 25 ns;
2869 
    tPHLT : time := 23 ns;
2870 
    tPLHQ : time := 24 ns;
2871 
    tPHLQ : time := 27 ns
2872 
);
2873 
port(
2874 
    X_1  : in    std_logic;  -- R\
2875 
    X_2  : in    std_logic;  -- CP
2876 
    X_3  : in    std_logic;  -- P0
2877 
    X_4  : in    std_logic;  -- P1
2878 
    X_5  : in    std_logic;  -- P2
2879 
    X_6  : in    std_logic;  -- P3
2880 
    X_7  : in    std_logic;  -- CEP
2881 
    X_8  : inout std_logic;  -- GND
2882 
    X_9  : in    std_logic;  -- PE\
2883 
    X_10 : in    std_logic;  -- CET
2884 
    X_11 : out   std_logic;  -- Q3
2885 
    X_12 : out   std_logic;  -- Q2
2886 
    X_13 : out   std_logic;  -- Q1
2887 
    X_14 : out   std_logic;  -- Q0
2888 
    X_15 : out   std_logic;  -- TC
2889 
    X_16 : inout std_logic   -- Vcc
2890 
);
2891 
end component SN74LS163N;
2892 
 
2893 
-----------------------------------------------------------------------
2894 
-- SN74LS164N: SIPO shift register
2895 
-----------------------------------------------------------------------
2896 
component SN74LS164N is
2897 
generic(
2898 
    tPLH : time := 27 ns;
2899 
    tPHL : time := 32 ns
2900 
);
2901 
port(
2902 
    X_1  : in    std_logic;  -- A
2903 
    X_2  : in    std_logic;  -- B
2904 
    X_3  : out   std_logic;  -- Q0
2905 
    X_4  : out   std_logic;  -- Q1
2906 
    X_5  : out   std_logic;  -- Q2
2907 
    X_6  : out   std_logic;  -- Q3
2908 
    X_7  : inout std_logic;  -- GND
2909 
    X_8  : in    std_logic;  -- CP
2910 
    X_9  : in    std_logic;  -- MR\
2911 
    X_10 : out   std_logic;  -- Q4
2912 
    X_11 : out   std_logic;  -- Q5
2913 
    X_12 : out   std_logic;  -- Q6
2914 
    X_13 : out   std_logic;  -- Q7
2915 
    X_14 : inout std_logic   -- Vcc
2916 
);
2917 
end component SN74LS164N;
2918 
 
2919 
-----------------------------------------------------------------------
2920 
-- SN74LS165N: 8-bit parallel-to-serial converter
2921 
-----------------------------------------------------------------------
2922 
component SN74LS165N is
2923 
generic(
2924 
    tPLH : time := 30 ns;
2925 
    tPHL : time := 30 ns
2926 
);
2927 
port(
2928 
    X_1  : in    std_logic;  -- PL\
2929 
    X_2  : in    std_logic;  -- CP1
2930 
    X_3  : in    std_logic;  -- P4
2931 
    X_4  : in    std_logic;  -- P5
2932 
    X_5  : in    std_logic;  -- P6
2933 
    X_6  : in    std_logic;  -- P7
2934 
    X_7  : out   std_logic;  -- Q7\
2935 
    X_8  : inout std_logic;  -- GND
2936 
    X_9  : out   std_logic;  -- Q7
2937 
    X_10 : in    std_logic;  -- DS
2938 
    X_11 : in    std_logic;  -- P0
2939 
    X_12 : in    std_logic;  -- P1
2940 
    X_13 : in    std_logic;  -- P2
2941 
    X_14 : in    std_logic;  -- P3
2942 
    X_15 : in    std_logic;  -- CP2
2943 
    X_16 : inout std_logic   -- Vcc
2944 
);
2945 
end component SN74LS165N;
2946 
 
2947 
-----------------------------------------------------------------------
2948 
-- SN74LS166N: 8-bit PISO shift register
2949 
-----------------------------------------------------------------------
2950 
component SN74LS166N is
2951 
generic(
2952 
    tPLH : time := 18 ns;
2953 
    tPHL : time := 27 ns;
2954 
    tSU  : time := 20 ns
2955 
);
2956 
port(
2957 
    X_1  : in    std_logic;  -- DS
2958 
    X_2  : in    std_logic;  -- P0
2959 
    X_3  : in    std_logic;  -- P1
2960 
    X_4  : in    std_logic;  -- P2
2961 
    X_5  : in    std_logic;  -- P3
2962 
    X_6  : in    std_logic;  -- CP2
2963 
    X_7  : in    std_logic;  -- CP1
2964 
    X_8  : inout std_logic;  -- GND
2965 
    X_9  : in    std_logic;  -- MR\
2966 
    X_10 : in    std_logic;  -- P4
2967 
    X_11 : in    std_logic;  -- P5
2968 
    X_12 : in    std_logic;  -- P6
2969 
    X_13 : out   std_logic;  -- Q7
2970 
    X_14 : in    std_logic;  -- P7
2971 
    X_15 : in    std_logic;  -- PE\
2972 
    X_16 : inout std_logic   -- Vcc
2973 
);
2974 
end component SN74LS166N;
2975 
 
2976 
-- SN74167N: Synchronous decade rate multiplier
2977 
 
2978 
-----------------------------------------------------------------------
2979 
-- SN74LS168N: Synchronous bidirectional BCD decade counter
2980 
-----------------------------------------------------------------------
2981 
component SN74LS168N is
2982 
generic(
2983 
    tPLHQ : time := 20 ns;
2984 
    tPHLQ : time := 20 ns;
2985 
    tPLHT : time := 30 ns;
2986 
    tPHLT : time := 30 ns;
2987 
    tSU   : time := 15 ns;
2988 
    tSUPE : time := 20 ns
2989 
);
2990 
port(
2991 
    X_1  : in    std_logic;  -- U_D\
2992 
    X_2  : in    std_logic;  -- CP
2993 
    X_3  : in    std_logic;  -- P0
2994 
    X_4  : in    std_logic;  -- P1
2995 
    X_5  : in    std_logic;  -- P2
2996 
    X_6  : in    std_logic;  -- P3
2997 
    X_7  : in    std_logic;  -- CEP\
2998 
    X_8  : inout std_logic;  -- GND
2999 
    X_9  : in    std_logic;  -- PE\
3000 
    X_10 : in    std_logic;  -- CET\
3001 
    X_11 : out   std_logic;  -- Q3
3002 
    X_12 : out   std_logic;  -- Q2
3003 
    X_13 : out   std_logic;  -- Q1
3004 
    X_14 : out   std_logic;  -- Q0
3005 
    X_15 : out   std_logic;  -- TC\
3006 
    X_16 : inout std_logic   -- Vcc
3007 
);
3008 
end component SN74LS168N;
3009 
 
3010 
-----------------------------------------------------------------------
3011 
-- SN74LS169N: Synchronous bidirectional 4-bit binary counter
3012 
-----------------------------------------------------------------------
3013 
component SN74LS169N is
3014 
generic(
3015 
    tPLHQ : time := 20 ns;
3016 
    tPHLQ : time := 20 ns;
3017 
    tPLHT : time := 30 ns;
3018 
    tPHLT : time := 30 ns;
3019 
    tSU   : time := 15 ns;
3020 
    tSUPE : time := 20 ns
3021 
);
3022 
port(
3023 
    X_1  : in    std_logic;  -- U_D\
3024 
    X_2  : in    std_logic;  -- CP
3025 
    X_3  : in    std_logic;  -- P0
3026 
    X_4  : in    std_logic;  -- P1
3027 
    X_5  : in    std_logic;  -- P2
3028 
    X_6  : in    std_logic;  -- P3
3029 
    X_7  : in    std_logic;  -- CEP\
3030 
    X_8  : inout std_logic;  -- GND
3031 
    X_9  : in    std_logic;  -- PE\
3032 
    X_10 : in    std_logic;  -- CET\
3033 
    X_11 : out   std_logic;  -- Q3
3034 
    X_12 : out   std_logic;  -- Q2
3035 
    X_13 : out   std_logic;  -- Q1
3036 
    X_14 : out   std_logic;  -- Q0
3037 
    X_15 : out   std_logic;  -- TC\
3038 
    X_16 : inout std_logic   -- Vcc
3039 
);
3040 
end component SN74LS169N;
3041 
 
3042 
-----------------------------------------------------------------------
3043 
-- SN74LS170N: 4 X 4 register file (open collector)
3044 
-----------------------------------------------------------------------
3045 
component SN74LS170N is
3046 
generic(
3047 
    tPLC : time    := 35 ns;
3048 
    tPLA : time    := 35 ns;
3049 
    tSUD : time    := 10 ns;
3050 
    tSUA : time    := 10 ns
3051 
);
3052 
port(
3053 
    X_1  : in    std_logic;  -- D2
3054 
    X_2  : in    std_logic;  -- D3
3055 
    X_3  : in    std_logic;  -- D4
3056 
    X_4  : in    std_logic;  -- RA1
3057 
    X_5  : in    std_logic;  -- RA0
3058 
    X_6  : out   std_logic;  -- Q4
3059 
    X_7  : out   std_logic;  -- Q3
3060 
    X_8  : inout std_logic;  -- GND
3061 
    X_9  : out   std_logic;  -- Q2
3062 
    X_10 : out   std_logic;  -- Q1
3063 
    X_11 : in    std_logic;  -- RE\
3064 
    X_12 : in    std_logic;  -- WE\
3065 
    X_13 : in    std_logic;  -- WA1
3066 
    X_14 : in    std_logic;  -- WA0
3067 
    X_15 : in    std_logic;  -- D1
3068 
    X_16 : inout std_logic   -- Vcc
3069 
);
3070 
end component SN74LS170N;
3071 
 
3072 
-----------------------------------------------------------------------
3073 
-- SN74LS173N: 4-bit D-type register (3-state outputs)
3074 
-----------------------------------------------------------------------
3075 
component SN74LS173N is
3076 
generic(
3077 
    tSD  : time  := 10 ns;
3078 
    tSE  : time  := 17 ns;
3079 
    tPQ  : time  := 40 ns;
3080 
    tQZ  : time  := 20 ns
3081 
);
3082 
port(
3083 
    X_1  : in    std_logic;  -- OE1\
3084 
    X_2  : in    std_logic;  -- OE2\
3085 
    X_3  : out   std_logic;  -- Q0
3086 
    X_4  : out   std_logic;  -- Q1
3087 
    X_5  : out   std_logic;  -- Q2
3088 
    X_6  : out   std_logic;  -- Q3
3089 
    X_7  : in    std_logic;  -- CP
3090 
    X_8  : inout std_logic;  -- GND
3091 
    X_9  : in    std_logic;  -- IE1\
3092 
    X_10 : in    std_logic;  -- IE2\
3093 
    X_11 : in    std_logic;  -- D3
3094 
    X_12 : in    std_logic;  -- D2
3095 
    X_13 : in    std_logic;  -- D1
3096 
    X_14 : in    std_logic;  -- D0
3097 
    X_15 : in    std_logic;  -- MR
3098 
    X_16 : inout std_logic   -- Vcc
3099 
);
3100 
end component SN74LS173N;
3101 
 
3102 
-----------------------------------------------------------------------
3103 
-- SN74LS174N: Hex D-flipflop
3104 
-----------------------------------------------------------------------
3105 
component SN74LS174N is
3106 
generic(
3107 
    tSU  : time := 10 ns;
3108 
    tPD  : time := 25 ns
3109 
);
3110 
port(
3111 
    X_1  : in    std_logic;  -- MR\
3112 
    X_2  : out   std_logic;  -- Q0
3113 
    X_3  : in    std_logic;  -- D0
3114 
    X_4  : in    std_logic;  -- D1
3115 
    X_5  : out   std_logic;  -- Q1
3116 
    X_6  : in    std_logic;  -- D2
3117 
    X_7  : out   std_logic;  -- Q2
3118 
    X_8  : inout std_logic;  -- GND
3119 
    X_9  : in    std_logic;  -- CP
3120 
    X_10 : out   std_logic;  -- Q3
3121 
    X_11 : in    std_logic;  -- D3
3122 
    X_12 : out   std_logic;  -- Q4
3123 
    X_13 : in    std_logic;  -- D4
3124 
    X_14 : in    std_logic;  -- D5
3125 
    X_15 : out   std_logic;  -- Q5
3126 
    X_16 : inout std_logic   -- Vcc
3127 
);
3128 
end component SN74LS174N;
3129 
 
3130 
-----------------------------------------------------------------------
3131 
-- SN74LS175N: Quad D-flipflop
3132 
-----------------------------------------------------------------------
3133 
component SN74LS175N is
3134 
generic(
3135 
    tSU  : time := 10 ns;
3136 
    tPD  : time := 25 ns
3137 
);
3138 
port(
3139 
    X_1  : in    std_logic;  -- MR\
3140 
    X_2  : out   std_logic;  -- Q0
3141 
    X_3  : out   std_logic;  -- Q0\
3142 
    X_4  : in    std_logic;  -- D0
3143 
    X_5  : in    std_logic;  -- D1
3144 
    X_6  : out   std_logic;  -- Q1\
3145 
    X_7  : out   std_logic;  -- Q1
3146 
    X_8  : inout std_logic;  -- GND
3147 
    X_9  : in    std_logic;  -- CP
3148 
    X_10 : out   std_logic;  -- Q2
3149 
    X_11 : out   std_logic;  -- Q2\
3150 
    X_12 : in    std_logic;  -- D2
3151 
    X_13 : in    std_logic;  -- D3
3152 
    X_14 : out   std_logic;  -- Q3\
3153 
    X_15 : out   std_logic;  -- Q3
3154 
    X_16 : inout std_logic   -- Vcc
3155 
);
3156 
end component SN74LS175N;
3157 
 
3158 
-----------------------------------------------------------------------
3159 
-- SN74176N: Presettable decade counter
3160 
-----------------------------------------------------------------------
3161 
component SN74176N is
3162 
generic(
3163 
    tPLH0 : time := 13 ns;
3164 
    tPHL0 : time := 17 ns;
3165 
    tPLH1 : time := 17 ns;
3166 
    tPHL1 : time := 26 ns;
3167 
    tPLH2 : time := 41 ns;
3168 
    tPHL2 : time := 51 ns;
3169 
    tPLH3 : time := 20 ns;
3170 
    tPHL3 : time := 26 ns
3171 
);
3172 
port(
3173 
    X_1  : in    std_logic;  -- PL\
3174 
    X_2  : out   std_logic;  -- Q2
3175 
    X_3  : in    std_logic;  -- P2
3176 
    X_4  : in    std_logic;  -- P0
3177 
    X_5  : out   std_logic;  -- Q0
3178 
    X_6  : in    std_logic;  -- CP1\
3179 
    X_7  : inout std_logic;  -- GND
3180 
    X_8  : in    std_logic;  -- CP0\
3181 
    X_9  : out   std_logic;  -- Q1
3182 
    X_10 : in    std_logic;  -- P1
3183 
    X_11 : in    std_logic;  -- P3
3184 
    X_12 : out   std_logic;  -- Q3
3185 
    X_13 : in    std_logic;  -- MR\
3186 
    X_14 : inout std_logic   -- Vcc
3187 
);
3188 
end component SN74176N;
3189 
 
3190 
-----------------------------------------------------------------------
3191 
-- SN74177N: Presettable binary counter
3192 
-----------------------------------------------------------------------
3193 
component SN74177N is
3194 
generic(
3195 
    tPLH0 : time := 13 ns;
3196 
    tPHL0 : time := 17 ns;
3197 
    tPLH1 : time := 17 ns;
3198 
    tPHL1 : time := 26 ns;
3199 
    tPLH2 : time := 41 ns;
3200 
    tPHL2 : time := 51 ns;
3201 
    tPLH3 : time := 66 ns;
3202 
    tPHL3 : time := 75 ns
3203 
);
3204 
port(
3205 
    X_1  : in    std_logic;  -- PL\
3206 
    X_2  : out   std_logic;  -- Q2
3207 
    X_3  : in    std_logic;  -- P2
3208 
    X_4  : in    std_logic;  -- P0
3209 
    X_5  : out   std_logic;  -- Q0
3210 
    X_6  : in    std_logic;  -- CP1\
3211 
    X_7  : inout std_logic;  -- GND
3212 
    X_8  : in    std_logic;  -- CP0\
3213 
    X_9  : out   std_logic;  -- Q1
3214 
    X_10 : in    std_logic;  -- P1
3215 
    X_11 : in    std_logic;  -- P3
3216 
    X_12 : out   std_logic;  -- Q3
3217 
    X_13 : in    std_logic;  -- MR\
3218 
    X_14 : inout std_logic   -- Vcc
3219 
);
3220 
end component SN74177N;
3221 
 
3222 
-----------------------------------------------------------------------
3223 
-- SN74178N: 4-bit shift register
3224 
-----------------------------------------------------------------------
3225 
component SN74178N is
3226 
generic(
3227 
    tDL  : time := 36 ns;
3228 
    tSU  : time := 35 ns
3229 
);
3230 
port(
3231 
    X_1  : in    std_logic;  -- P1
3232 
    X_2  : in    std_logic;  -- P0
3233 
    X_3  : in    std_logic;  -- DS
3234 
    X_4  : out   std_logic;  -- Q0
3235 
    X_5  : in    std_logic;  -- CP\
3236 
    X_6  : out   std_logic;  -- Q1
3237 
    X_7  : inout std_logic;  -- GND
3238 
    X_8  : out   std_logic;  -- Q2
3239 
    X_9  : in    std_logic;  -- PE
3240 
    X_10 : out   std_logic;  -- Q3
3241 
    X_11 : in    std_logic;  -- SE
3242 
    X_12 : in    std_logic;  -- P3
3243 
    X_13 : in    std_logic;  -- P2
3244 
    X_14 : inout std_logic   -- Vcc
3245 
);
3246 
end component SN74178N;
3247 
 
3248 
-----------------------------------------------------------------------
3249 
-- SN74179N: 4-bit shift register
3250 
-----------------------------------------------------------------------
3251 
component SN74179N is
3252 
generic(
3253 
    tDL  : time := 36 ns;
3254 
    tSU  : time := 35 ns
3255 
);
3256 
port(
3257 
    X_1  : in    std_logic;  -- MR\
3258 
    X_2  : in    std_logic;  -- P1
3259 
    X_3  : in    std_logic;  -- P0
3260 
    X_4  : in    std_logic;  -- DS
3261 
    X_5  : out   std_logic;  -- Q0
3262 
    X_6  : in    std_logic;  -- CP\
3263 
    X_7  : out   std_logic;  -- Q1
3264 
    X_8  : inout std_logic;  -- GND
3265 
    X_9  : out   std_logic;  -- Q2
3266 
    X_10 : in    std_logic;  -- PE
3267 
    X_11 : out   std_logic;  -- Q3
3268 
    X_12 : out   std_logic;  -- Q3\
3269 
    X_13 : in    std_logic;  -- SE
3270 
    X_14 : in    std_logic;  -- P3
3271 
    X_15 : in    std_logic;  -- P2
3272 
    X_16 : inout std_logic   -- Vcc
3273 
);
3274 
end component SN74179N;
3275 
 
3276 
-----------------------------------------------------------------------
3277 
-- SN74180N: 8-bit parity generator/checker
3278 
-----------------------------------------------------------------------
3279 
component SN74180N is
3280 
generic(
3281 
    tPI  : time  := 68 ns;
3282 
    tPE  : time  := 20 ns
3283 
);
3284 
port(
3285 
    X_1  : in    std_logic;  -- I6
3286 
    X_2  : in    std_logic;  -- I7
3287 
    X_3  : in    std_logic;  -- EI
3288 
    X_4  : in    std_logic;  -- OI
3289 
    X_5  : out   std_logic;  -- SE
3290 
    X_6  : out   std_logic;  -- SO
3291 
    X_7  : inout std_logic;  -- GND
3292 
    X_8  : in    std_logic;  -- I0
3293 
    X_9  : in    std_logic;  -- I1
3294 
    X_10 : in    std_logic;  -- I2
3295 
    X_11 : in    std_logic;  -- I3
3296 
    X_12 : in    std_logic;  -- I4
3297 
    X_13 : in    std_logic;  -- I5
3298 
    X_14 : inout std_logic   -- Vcc
3299 
);
3300 
end component SN74180N;
3301 
 
3302 
-----------------------------------------------------------------------
3303 
-- SN74LS181N: 4-bit arithmetic/logic unit
3304 
-----------------------------------------------------------------------
3305 
component SN74LS181N is
3306 
generic(
3307 
    T1   : time :=  7 ns;
3308 
    T2   : time := 19 ns;
3309 
    T3   : time := 16 ns;
3310 
    T4   : time := 25 ns;
3311 
    T5   : time := 29 ns
3312 
);
3313 
port(
3314 
    X_1  : in    std_logic;  -- B0\
3315 
    X_2  : in    std_logic;  -- A0\
3316 
    X_3  : in    std_logic;  -- S3
3317 
    X_4  : in    std_logic;  -- S2
3318 
    X_5  : in    std_logic;  -- S1
3319 
    X_6  : in    std_logic;  -- S0
3320 
    X_7  : in    std_logic;  -- Cn
3321 
    X_8  : in    std_logic;  -- M
3322 
    X_9  : out   std_logic;  -- F0\
3323 
    X_10 : out   std_logic;  -- F1\
3324 
    X_11 : out   std_logic;  -- F2\
3325 
    X_12 : inout std_logic;  -- GND
3326 
    X_13 : out   std_logic;  -- F3\
3327 
    X_14 : out   std_logic;  -- A=B
3328 
    X_15 : out   std_logic;  -- P\
3329 
    X_16 : out   std_logic;  -- Cn+4
3330 
    X_17 : out   std_logic;  -- G\
3331 
    X_18 : in    std_logic;  -- B3\
3332 
    X_19 : in    std_logic;  -- A3\
3333 
    X_20 : in    std_logic;  -- B2\
3334 
    X_21 : in    std_logic;  -- A2\
3335 
    X_22 : in    std_logic;  -- B1\
3336 
    X_23 : in    std_logic;  -- A1\
3337 
    X_24 : inout std_logic   -- Vcc
3338 
);
3339 
end component SN74LS181N;
3340 
 
3341 
-----------------------------------------------------------------------
3342 
-- SN74LS182N: Fast carry unit for 4 x LS181
3343 
-----------------------------------------------------------------------
3344 
component SN74LS182N is
3345 
generic(
3346 
    tCLH : time := 10   ns;
3347 
    tCHL : time := 11.5 ns;
3348 
    tGLH : time :=  7.5 ns;
3349 
    tGHL : time := 10.5 ns;
3350 
    tPLH : time :=  6.5 ns;
3351 
    tPHL : time := 10   ns
3352 
);
3353 
port(
3354 
    X_1  : in    std_logic;  -- G1
3355 
    X_2  : in    std_logic;  -- P1
3356 
    X_3  : in    std_logic;  -- G0
3357 
    X_4  : in    std_logic;  -- P0
3358 
    X_5  : in    std_logic;  -- G3
3359 
    X_6  : in    std_logic;  -- P3
3360 
    X_7  : out   std_logic;  -- P
3361 
    X_8  : inout std_logic;  -- GND
3362 
    X_9  : out   std_logic;  -- Cz
3363 
    X_10 : out   std_logic;  -- G
3364 
    X_11 : out   std_logic;  -- Cy
3365 
    X_12 : out   std_logic;  -- Cx
3366 
    X_13 : in    std_logic;  -- Cn
3367 
    X_14 : in    std_logic;  -- G2
3368 
    X_15 : in    std_logic;  -- P2
3369 
    X_16 : inout std_logic   -- Vcc
3370 
);
3371 
end component SN74LS182N;
3372 
 
3373 
-----------------------------------------------------------------------
3374 
-- SN74H183N: Dual high-speed adder
3375 
-----------------------------------------------------------------------
3376 
component SN74H183N is
3377 
generic(
3378 
    tPLH : time := 15 ns;
3379 
    tPHL : time := 18 ns
3380 
);
3381 
port(
3382 
    X_1  : in    std_logic;  -- Aa
3383 
                             --
3384 
    X_3  : in    std_logic;  -- Ba
3385 
    X_4  : in    std_logic;  -- CIa
3386 
    X_5  : out   std_logic;  -- COa
3387 
    X_6  : out   std_logic;  -- Sa
3388 
    X_7  : inout std_logic;  -- GND
3389 
    X_8  : out   std_logic;  -- Sb
3390 
                             --
3391 
    X_10 : out   std_logic;  -- COb
3392 
    X_11 : in    std_logic;  -- CIb
3393 
    X_12 : in    std_logic;  -- Bb
3394 
    X_13 : in    std_logic;  -- Ab
3395 
    X_14 : inout std_logic   -- Vcc
3396 
);
3397 
end component SN74H183N;
3398 
 
3399 
-----------------------------------------------------------------------
3400 
-- SN74LS189N: 64-bit random-access memory (3-state outputs)
3401 
-----------------------------------------------------------------------
3402 
component SN74LS189N is
3403 
generic(
3404 
    tPLC  : time     := 10 ns;
3405 
    tPLA  : time     := 37 ns;
3406 
    tSUD  : time     := 25 ns;
3407 
    tSUA  : time     := 10 ns
3408 
);
3409 
port(
3410 
    X_1   : in    std_logic;  -- A0
3411 
    X_2   : in    std_logic;  -- CS\
3412 
    X_3   : in    std_logic;  -- WE\
3413 
    X_4   : in    std_logic;  -- D1
3414 
    X_5   : out   std_logic;  -- Q1\
3415 
    X_6   : in    std_logic;  -- D2
3416 
    X_7   : out   std_logic;  -- Q2\
3417 
    X_8   : inout std_logic;  -- GND
3418 
    X_9   : out   std_logic;  -- Q3\
3419 
    X_10  : in    std_logic;  -- D3
3420 
    X_11  : out   std_logic;  -- Q4\
3421 
    X_12  : in    std_logic;  -- D4
3422 
    X_13  : in    std_logic;  -- A3
3423 
    X_14  : in    std_logic;  -- A2
3424 
    X_15  : in    std_logic;  -- A1
3425 
    X_16  : inout std_logic   -- Vcc
3426 
);
3427 
end component SN74LS189N;
3428 
 
3429 
-----------------------------------------------------------------------
3430 
-- SN74LS190N: Up/down decade counter
3431 
-----------------------------------------------------------------------
3432 
component SN74LS190N is
3433 
generic(
3434 
    MODULUS : positive := 10;
3435 
    tQLH    : time     := 24 ns;
3436 
    tQHL    : time     := 36 ns;
3437 
    tTLH    : time     := 42 ns;
3438 
    tTHL    : time     := 52 ns;
3439 
    tRLH    : time     := 20 ns;
3440 
    tRHL    : time     := 24 ns
3441 
);
3442 
port(
3443 
    X_1  : in    std_logic;  -- P1
3444 
    X_2  : out   std_logic;  -- Q1
3445 
    X_3  : out   std_logic;  -- Q0
3446 
    X_4  : in    std_logic;  -- CE\
3447 
    X_5  : in    std_logic;  -- U\/D
3448 
    X_6  : out   std_logic;  -- Q2
3449 
    X_7  : out   std_logic;  -- Q3
3450 
    X_8  : inout std_logic;  -- GND
3451 
    X_9  : in    std_logic;  -- P3
3452 
    X_10 : in    std_logic;  -- P2
3453 
    X_11 : in    std_logic;  -- PL\
3454 
    X_12 : out   std_logic;  -- TC
3455 
    X_13 : out   std_logic;  -- RC\
3456 
    X_14 : in    std_logic;  -- CP
3457 
    X_15 : in    std_logic;  -- P0
3458 
    X_16 : inout std_logic   -- Vcc
3459 
);
3460 
end component SN74LS190N;
3461 
 
3462 
-----------------------------------------------------------------------
3463 
-- SN74LS191N: Up/down binary counter
3464 
-----------------------------------------------------------------------
3465 
component SN74LS191N is
3466 
generic(
3467 
    MODULUS : positive := 16;
3468 
    tQLH    : time     := 24 ns;
3469 
    tQHL    : time     := 36 ns;
3470 
    tTLH    : time     := 42 ns;
3471 
    tTHL    : time     := 52 ns;
3472 
    tRLH    : time     := 20 ns;
3473 
    tRHL    : time     := 24 ns
3474 
);
3475 
port(
3476 
    X_1  : in    std_logic;  -- P1
3477 
    X_2  : out   std_logic;  -- Q1
3478 
    X_3  : out   std_logic;  -- Q0
3479 
    X_4  : in    std_logic;  -- CE\
3480 
    X_5  : in    std_logic;  -- U\/D
3481 
    X_6  : out   std_logic;  -- Q2
3482 
    X_7  : out   std_logic;  -- Q3
3483 
    X_8  : inout std_logic;  -- GND
3484 
    X_9  : in    std_logic;  -- P3
3485 
    X_10 : in    std_logic;  -- P2
3486 
    X_11 : in    std_logic;  -- PL\
3487 
    X_12 : out   std_logic;  -- TC
3488 
    X_13 : out   std_logic;  -- RC\
3489 
    X_14 : in    std_logic;  -- CP
3490 
    X_15 : in    std_logic;  -- P0
3491 
    X_16 : inout std_logic   -- Vcc
3492 
);
3493 
end component SN74LS191N;
3494 
 
3495 
-----------------------------------------------------------------------
3496 
-- SN74LS192N: Up/down decade counter
3497 
-----------------------------------------------------------------------
3498 
component SN74LS192N is
3499 
generic(
3500 
    MODULUS : positive := 10;
3501 
    tQLH    : time     := 32 ns;
3502 
    tQHL    : time     := 30 ns;
3503 
    tTCULH  : time     := 16 ns;
3504 
    tTCUHL  : time     := 21 ns;
3505 
    tTCDLH  : time     := 16 ns;
3506 
    tTCDHL  : time     := 24 ns
3507 
);
3508 
port(
3509 
    X_1  : in    std_logic;  -- P1
3510 
    X_2  : out   std_logic;  -- Q1
3511 
    X_3  : out   std_logic;  -- Q0
3512 
    X_4  : in    std_logic;  -- CPD
3513 
    X_5  : in    std_logic;  -- CPU
3514 
    X_6  : out   std_logic;  -- Q2
3515 
    X_7  : out   std_logic;  -- Q3
3516 
    X_8  : inout std_logic;  -- GND
3517 
    X_9  : in    std_logic;  -- P3
3518 
    X_10 : in    std_logic;  -- P2
3519 
    X_11 : in    std_logic;  -- PL\
3520 
    X_12 : out   std_logic;  -- TCU\
3521 
    X_13 : out   std_logic;  -- TCD\
3522 
    X_14 : in    std_logic;  -- MR
3523 
    X_15 : in    std_logic;  -- P0
3524 
    X_16 : inout std_logic   -- Vcc
3525 
);
3526 
end component SN74LS192N;
3527 
 
3528 
-----------------------------------------------------------------------
3529 
-- SN74LS193N: Up/down binary counter
3530 
-----------------------------------------------------------------------
3531 
component SN74LS193N is
3532 
generic(
3533 
    MODULUS : positive := 16;
3534 
    tQLH    : time     := 32 ns;
3535 
    tQHL    : time     := 30 ns;
3536 
    tTCULH  : time     := 16 ns;
3537 
    tTCUHL  : time     := 21 ns;
3538 
    tTCDLH  : time     := 16 ns;
3539 
    tTCDHL  : time     := 24 ns
3540 
);
3541 
port(
3542 
    X_1  : in    std_logic;  -- P1
3543 
    X_2  : out   std_logic;  -- Q1
3544 
    X_3  : out   std_logic;  -- Q0
3545 
    X_4  : in    std_logic;  -- CPD
3546 
    X_5  : in    std_logic;  -- CPU
3547 
    X_6  : out   std_logic;  -- Q2
3548 
    X_7  : out   std_logic;  -- Q3
3549 
    X_8  : inout std_logic;  -- GND
3550 
    X_9  : in    std_logic;  -- P3
3551 
    X_10 : in    std_logic;  -- P2
3552 
    X_11 : in    std_logic;  -- PL\
3553 
    X_12 : out   std_logic;  -- TCU\
3554 
    X_13 : out   std_logic;  -- TCD\
3555 
    X_14 : in    std_logic;  -- MR
3556 
    X_15 : in    std_logic;  -- P0
3557 
    X_16 : inout std_logic   -- Vcc
3558 
);
3559 
end component SN74LS193N;
3560 
 
3561 
-----------------------------------------------------------------------
3562 
-- SN74LS194N: 4-bit bidirectional shift register
3563 
-----------------------------------------------------------------------
3564 
component SN74LS194N is
3565 
generic(
3566 
    tPLH : time := 21 ns;
3567 
    tPHL : time := 24 ns
3568 
);
3569 
port(
3570 
    X_1  : in    std_logic;  -- MR\
3571 
    X_2  : in    std_logic;  -- DSR
3572 
    X_3  : in    std_logic;  -- P0
3573 
    X_4  : in    std_logic;  -- P1
3574 
    X_5  : in    std_logic;  -- P2
3575 
    X_6  : in    std_logic;  -- P3
3576 
    X_7  : in    std_logic;  -- DSL
3577 
    X_8  : inout std_logic;  -- GND
3578 
    X_9  : in    std_logic;  -- S0
3579 
    X_10 : in    std_logic;  -- S1
3580 
    X_11 : in    std_logic;  -- CP
3581 
    X_12 : out   std_logic;  -- Q3
3582 
    X_13 : out   std_logic;  -- Q2
3583 
    X_14 : out   std_logic;  -- Q1
3584 
    X_15 : out   std_logic;  -- Q0
3585 
    X_16 : inout std_logic   -- Vcc
3586 
);
3587 
end component SN74LS194N;
3588 
 
3589 
-----------------------------------------------------------------------
3590 
-- SN74LS195N: Universal 4-bit shift register
3591 
-----------------------------------------------------------------------
3592 
component SN74LS195N is
3593 
generic(
3594 
    tPLH : time := 21 ns;
3595 
    tPHL : time := 24 ns
3596 
);
3597 
port(
3598 
    X_1  : in    std_logic;  -- MR\
3599 
    X_2  : in    std_logic;  -- J
3600 
    X_3  : in    std_logic;  -- K\
3601 
    X_4  : in    std_logic;  -- P0
3602 
    X_5  : in    std_logic;  -- P1
3603 
    X_6  : in    std_logic;  -- P2
3604 
    X_7  : in    std_logic;  -- P3
3605 
    X_8  : inout std_logic;  -- GND
3606 
    X_9  : in    std_logic;  -- PE\
3607 
    X_10 : in    std_logic;  -- CP
3608 
    X_11 : out   std_logic;  -- Q3\
3609 
    X_12 : out   std_logic;  -- Q3
3610 
    X_13 : out   std_logic;  -- Q2
3611 
    X_14 : out   std_logic;  -- Q1
3612 
    X_15 : out   std_logic;  -- Q0
3613 
    X_16 : inout std_logic   -- Vcc
3614 
);
3615 
end component SN74LS195N;
3616 
 
3617 
-----------------------------------------------------------------------
3618 
-- SN74LS196N: Presettable decade counter
3619 
--             Verified 03/08/2016
3620 
-----------------------------------------------------------------------
3621 
component SN74LS196N is
3622 
generic(
3623 
    tPLH0 : time := 12 ns;
3624 
    tPHL0 : time := 12 ns;
3625 
    tPLH1 : time := 14 ns;
3626 
    tPHL1 : time := 14 ns;
3627 
    tPLH2 : time := 34 ns;
3628 
    tPHL2 : time := 32 ns;
3629 
    tPLH3 : time := 18 ns;
3630 
    tPHL3 : time := 18 ns
3631 
);
3632 
port(
3633 
    X_1  : in    std_logic;  -- PL\
3634 
    X_2  : out   std_logic;  -- Q2
3635 
    X_3  : in    std_logic;  -- P2
3636 
    X_4  : in    std_logic;  -- P0
3637 
    X_5  : out   std_logic;  -- Q0
3638 
    X_6  : in    std_logic;  -- CP1\
3639 
    X_7  : inout std_logic;  -- GND
3640 
    X_8  : in    std_logic;  -- CP0\
3641 
    X_9  : out   std_logic;  -- Q1
3642 
    X_10 : in    std_logic;  -- P1
3643 
    X_11 : in    std_logic;  -- P3
3644 
    X_12 : out   std_logic;  -- Q3
3645 
    X_13 : in    std_logic;  -- MR\
3646 
    X_14 : inout std_logic   -- Vcc
3647 
);
3648 
end component SN74LS196N;
3649 
 
3650 
-----------------------------------------------------------------------
3651 
-- SN74LS197N: Presettable binary counter
3652 
-----------------------------------------------------------------------
3653 
component SN74LS197N is
3654 
generic(
3655 
    tPLH0 : time := 12 ns;
3656 
    tPHL0 : time := 12 ns;
3657 
    tPLH1 : time := 14 ns;
3658 
    tPHL1 : time := 14 ns;
3659 
    tPLH2 : time := 36 ns;
3660 
    tPHL2 : time := 34 ns;
3661 
    tPLH3 : time := 50 ns;
3662 
    tPHL3 : time := 55 ns
3663 
);
3664 
port(
3665 
    X_1  : in    std_logic;  -- PL\
3666 
    X_2  : out   std_logic;  -- Q2
3667 
    X_3  : in    std_logic;  -- P2
3668 
    X_4  : in    std_logic;  -- P0
3669 
    X_5  : out   std_logic;  -- Q0
3670 
    X_6  : in    std_logic;  -- CP1\
3671 
    X_7  : inout std_logic;  -- GND
3672 
    X_8  : in    std_logic;  -- CP0\
3673 
    X_9  : out   std_logic;  -- Q1
3674 
    X_10 : in    std_logic;  -- P1
3675 
    X_11 : in    std_logic;  -- P3
3676 
    X_12 : out   std_logic;  -- Q3
3677 
    X_13 : in    std_logic;  -- MR\
3678 
    X_14 : inout std_logic   -- Vcc
3679 
);
3680 
end component SN74LS197N;
3681 
 
3682 
-----------------------------------------------------------------------
3683 
-- SN74LS198N: 8-bit right/left shift register
3684 
-----------------------------------------------------------------------
3685 
component SN74LS198N is
3686 
generic(
3687 
    tPLH : time := 26 ns;
3688 
    tPHL : time := 30 ns
3689 
);
3690 
port(
3691 
    X_1  : in    std_logic;  -- S0
3692 
    X_2  : in    std_logic;  -- DSR
3693 
    X_3  : in    std_logic;  -- P0
3694 
    X_4  : out   std_logic;  -- Q0
3695 
    X_5  : in    std_logic;  -- P1
3696 
    X_6  : out   std_logic;  -- Q1
3697 
    X_7  : in    std_logic;  -- P2
3698 
    X_8  : out   std_logic;  -- Q2
3699 
    X_9  : in    std_logic;  -- P3
3700 
    X_10 : out   std_logic;  -- Q3
3701 
    X_11 : in    std_logic;  -- CP
3702 
    X_12 : inout std_logic;  -- GND
3703 
    X_13 : in    std_logic;  -- MR\
3704 
    X_14 : out   std_logic;  -- Q4
3705 
    X_15 : in    std_logic;  -- P4
3706 
    X_16 : out   std_logic;  -- Q5
3707 
    X_17 : in    std_logic;  -- P5
3708 
    X_18 : out   std_logic;  -- Q6
3709 
    X_19 : in    std_logic;  -- P6
3710 
    X_20 : out   std_logic;  -- Q7
3711 
    X_21 : in    std_logic;  -- P7
3712 
    X_22 : in    std_logic;  -- DSL
3713 
    X_23 : in    std_logic;  -- S1
3714 
    X_24 : inout std_logic   -- Vcc
3715 
);
3716 
end component SN74LS198N;
3717 
 
3718 
-----------------------------------------------------------------------
3719 
-- SN74LS199N: 8-bit parallel IO shift register
3720 
-----------------------------------------------------------------------
3721 
component SN74LS199N is
3722 
generic(
3723 
    tPLH : time := 26 ns;
3724 
    tPHL : time := 30 ns
3725 
);
3726 
port(
3727 
    X_1  : in    std_logic;  -- K\
3728 
    X_2  : in    std_logic;  -- J
3729 
    X_3  : in    std_logic;  -- P0
3730 
    X_4  : out   std_logic;  -- Q0
3731 
    X_5  : in    std_logic;  -- P1
3732 
    X_6  : out   std_logic;  -- Q1
3733 
    X_7  : in    std_logic;  -- P2
3734 
    X_8  : out   std_logic;  -- Q2
3735 
    X_9  : in    std_logic;  -- P3
3736 
    X_10 : out   std_logic;  -- Q3
3737 
    X_11 : in    std_logic;  -- CP1
3738 
    X_12 : inout std_logic;  -- GND
3739 
    X_13 : in    std_logic;  -- CP2
3740 
    X_14 : in    std_logic;  -- MR\
3741 
    X_15 : out   std_logic;  -- Q4
3742 
    X_16 : in    std_logic;  -- P4
3743 
    X_17 : out   std_logic;  -- Q5
3744 
    X_18 : in    std_logic;  -- P5
3745 
    X_19 : out   std_logic;  -- Q6
3746 
    X_20 : in    std_logic;  -- P6
3747 
    X_21 : out   std_logic;  -- Q7
3748 
    X_22 : in    std_logic;  -- P7
3749 
    X_23 : in    std_logic;  -- PE\
3750 
    X_24 : inout std_logic   -- Vcc
3751 
);
3752 
end component SN74LS199N;
3753 
 
3754 
-----------------------------------------------------------------------
3755 
-- SN74LS221N: Dual monostable multivibrator
3756 
-----------------------------------------------------------------------
3757 
component SN74LS221N is
3758 
generic(
3759 
    W1   : time := 100 us;   -- Pulse widths
3760 
    W2   : time := 100 us
3761 
);
3762 
port(
3763 
    X_1  : in    std_logic;  -- A1\
3764 
    X_2  : in    std_logic;  -- B1
3765 
    X_3  : in    std_logic;  -- CD1\
3766 
    X_4  : out   std_logic;  -- Q1\
3767 
    X_5  : out   std_logic;  -- Q2
3768 
    X_6  : inout std_logic;  -- Cx2
3769 
    X_7  : inout std_logic;  -- Rx2Cx2
3770 
    X_8  : inout std_logic;  -- GND
3771 
    X_9  : in    std_logic;  -- A2\
3772 
    X_10 : in    std_logic;  -- B2
3773 
    X_11 : in    std_logic;  -- CD2\
3774 
    X_12 : out   std_logic;  -- Q2\
3775 
    X_13 : out   std_logic;  -- Q1
3776 
    X_14 : inout std_logic;  -- Cx1
3777 
    X_15 : inout std_logic;  -- Rx1Cx1
3778 
    X_16 : inout std_logic   -- Vcc
3779 
);
3780 
end component SN74LS221N;
3781 
 
3782 
-----------------------------------------------------------------------
3783 
-- SN74LS240N: Octal buffer/line driver (3-state outputs)
3784 
-----------------------------------------------------------------------
3785 
component SN74LS240N is
3786 
generic(
3787 
    tPLH : time := 14 ns;
3788 
    tPHL : time := 18 ns;
3789 
    tPZH : time := 23 ns;
3790 
    tPZL : time := 30 ns;
3791 
    tPHZ : time := 25 ns;
3792 
    tPLZ : time := 18 ns
3793 
);
3794 
port(
3795 
    X_1  : in    std_logic;  -- OEA\
3796 
    X_2  : in    std_logic;  -- IA0
3797 
    X_3  : out   std_logic;  -- YB0\
3798 
    X_4  : in    std_logic;  -- IA1
3799 
    X_5  : out   std_logic;  -- YB1\
3800 
    X_6  : in    std_logic;  -- IA2
3801 
    X_7  : out   std_logic;  -- YB2\
3802 
    X_8  : in    std_logic;  -- IA3
3803 
    X_9  : out   std_logic;  -- YB3\
3804 
    X_10 : inout std_logic;  -- GND
3805 
    X_11 : in    std_logic;  -- IB3
3806 
    X_12 : out   std_logic;  -- YA3\
3807 
    X_13 : in    std_logic;  -- IB2
3808 
    X_14 : out   std_logic;  -- YA2\
3809 
    X_15 : in    std_logic;  -- IB1
3810 
    X_16 : out   std_logic;  -- YA1\
3811 
    X_17 : in    std_logic;  -- IB0
3812 
    X_18 : out   std_logic;  -- YA0\
3813 
    X_19 : in    std_logic;  -- OEB\
3814 
    X_20 : inout std_logic   -- Vcc
3815 
);
3816 
end component SN74LS240N;
3817 
 
3818 
-----------------------------------------------------------------------
3819 
-- SN74LS241N: Octal buffer/line driver (3-state outputs)
3820 
-----------------------------------------------------------------------
3821 
component SN74LS241N is
3822 
generic(
3823 
    tPLH : time := 18 ns;
3824 
    tPHL : time := 18 ns;
3825 
    tPZH : time := 23 ns;
3826 
    tPZL : time := 30 ns;
3827 
    tPHZ : time := 25 ns;
3828 
    tPLZ : time := 18 ns
3829 
);
3830 
port(
3831 
    X_1  : in    std_logic;  -- OEA\
3832 
    X_2  : in    std_logic;  -- IA0
3833 
    X_3  : out   std_logic;  -- YB0
3834 
    X_4  : in    std_logic;  -- IA1
3835 
    X_5  : out   std_logic;  -- YB1
3836 
    X_6  : in    std_logic;  -- IA2
3837 
    X_7  : out   std_logic;  -- YB2
3838 
    X_8  : in    std_logic;  -- IA3
3839 
    X_9  : out   std_logic;  -- YB3
3840 
    X_10 : inout std_logic;  -- GND
3841 
    X_11 : in    std_logic;  -- IB3
3842 
    X_12 : out   std_logic;  -- YA3
3843 
    X_13 : in    std_logic;  -- IB2
3844 
    X_14 : out   std_logic;  -- YA2
3845 
    X_15 : in    std_logic;  -- IB1
3846 
    X_16 : out   std_logic;  -- YA1
3847 
    X_17 : in    std_logic;  -- IB0
3848 
    X_18 : out   std_logic;  -- YA0
3849 
    X_19 : in    std_logic;  -- OEB
3850 
    X_20 : inout std_logic   -- Vcc
3851 
);
3852 
end component SN74LS241N;
3853 
 
3854 
-----------------------------------------------------------------------
3855 
-- SN74LS242N: Quad bus transceiver (3-state outputs)
3856 
-----------------------------------------------------------------------
3857 
component SN74LS242N is
3858 
generic(
3859 
    tPLH : time := 14 ns;
3860 
    tPHL : time := 18 ns;
3861 
    tPZH : time := 23 ns;
3862 
    tPZL : time := 30 ns;
3863 
    tPHZ : time := 25 ns;
3864 
    tPLZ : time := 18 ns
3865 
);
3866 
port(
3867 
    X_1  : in    std_logic;  -- A2B\
3868 
                             --
3869 
    X_3  : inout std_logic;  -- A1
3870 
    X_4  : inout std_logic;  -- A2
3871 
    X_5  : inout std_logic;  -- A3
3872 
    X_6  : inout std_logic;  -- A4
3873 
    X_7  : inout std_logic;  -- GND
3874 
    X_8  : inout std_logic;  -- B4\
3875 
    X_9  : inout std_logic;  -- B3\
3876 
    X_10 : inout std_logic;  -- B2\
3877 
    X_11 : inout std_logic;  -- B1\
3878 
                             --
3879 
    X_13 : in    std_logic;  -- B2A
3880 
    X_14 : inout std_logic   -- Vcc
3881 
);
3882 
end component SN74LS242N;
3883 
 
3884 
-----------------------------------------------------------------------
3885 
-- SN74LS243N: Quad bus transceiver (3-state outputs)
3886 
-----------------------------------------------------------------------
3887 
component SN74LS243N is
3888 
generic(
3889 
    tPLH : time := 18 ns;
3890 
    tPHL : time := 18 ns;
3891 
    tPZH : time := 23 ns;
3892 
    tPZL : time := 30 ns;
3893 
    tPHZ : time := 25 ns;
3894 
    tPLZ : time := 18 ns
3895 
);
3896 
port(
3897 
    X_1  : in    std_logic;  -- A2B\
3898 
                             --
3899 
    X_3  : inout std_logic;  -- A1
3900 
    X_4  : inout std_logic;  -- A2
3901 
    X_5  : inout std_logic;  -- A3
3902 
    X_6  : inout std_logic;  -- A4
3903 
    X_7  : inout std_logic;  -- GND
3904 
    X_8  : inout std_logic;  -- B4
3905 
    X_9  : inout std_logic;  -- B3
3906 
    X_10 : inout std_logic;  -- B2
3907 
    X_11 : inout std_logic;  -- B1
3908 
                             --
3909 
    X_13 : in    std_logic;  -- B2A
3910 
    X_14 : inout std_logic   -- Vcc
3911 
);
3912 
end component SN74LS243N;
3913 
 
3914 
-----------------------------------------------------------------------
3915 
-- SN74LS244N: Octal buffer/line driver (3-state outputs)
3916 
-----------------------------------------------------------------------
3917 
component SN74LS244N is
3918 
generic(
3919 
    tPLH : time := 18 ns;
3920 
    tPHL : time := 18 ns;
3921 
    tPZH : time := 23 ns;
3922 
    tPZL : time := 30 ns;
3923 
    tPHZ : time := 25 ns;
3924 
    tPLZ : time := 18 ns
3925 
);
3926 
port(
3927 
    X_1  : in    std_logic;  -- OEA\
3928 
    X_2  : in    std_logic;  -- IA0
3929 
    X_3  : out   std_logic;  -- YB0
3930 
    X_4  : in    std_logic;  -- IA1
3931 
    X_5  : out   std_logic;  -- YB1
3932 
    X_6  : in    std_logic;  -- IA2
3933 
    X_7  : out   std_logic;  -- YB2
3934 
    X_8  : in    std_logic;  -- IA3
3935 
    X_9  : out   std_logic;  -- YB3
3936 
    X_10 : inout std_logic;  -- GND
3937 
    X_11 : in    std_logic;  -- IB3
3938 
    X_12 : out   std_logic;  -- YA3
3939 
    X_13 : in    std_logic;  -- IB2
3940 
    X_14 : out   std_logic;  -- YA2
3941 
    X_15 : in    std_logic;  -- IB1
3942 
    X_16 : out   std_logic;  -- YA1
3943 
    X_17 : in    std_logic;  -- IB0
3944 
    X_18 : out   std_logic;  -- YA0
3945 
    X_19 : in    std_logic;  -- OEB\
3946 
    X_20 : inout std_logic   -- Vcc
3947 
);
3948 
end component SN74LS244N;
3949 
 
3950 
-----------------------------------------------------------------------
3951 
-- SN74LS245N: Octal bus transceiver (3-state outputs)
3952 
-----------------------------------------------------------------------
3953 
component SN74LS245N is
3954 
generic(
3955 
    tPLH : time := 18 ns;
3956 
    tPHL : time := 18 ns;
3957 
    tPZH : time := 23 ns;
3958 
    tPZL : time := 30 ns;
3959 
    tPHZ : time := 25 ns;
3960 
    tPLZ : time := 18 ns
3961 
);
3962 
port(
3963 
    X_1  : in    std_logic;  -- A2B
3964 
    X_2  : inout std_logic;  -- A0
3965 
    X_3  : inout std_logic;  -- A1
3966 
    X_4  : inout std_logic;  -- A2
3967 
    X_5  : inout std_logic;  -- A3
3968 
    X_6  : inout std_logic;  -- A4
3969 
    X_7  : inout std_logic;  -- A5
3970 
    X_8  : inout std_logic;  -- A6
3971 
    X_9  : inout std_logic;  -- A7
3972 
    X_10 : inout std_logic;  -- GND
3973 
    X_11 : inout std_logic;  -- B7
3974 
    X_12 : inout std_logic;  -- B6
3975 
    X_13 : inout std_logic;  -- B5
3976 
    X_14 : inout std_logic;  -- B4
3977 
    X_15 : inout std_logic;  -- B3
3978 
    X_16 : inout std_logic;  -- B2
3979 
    X_17 : inout std_logic;  -- B1
3980 
    X_18 : inout std_logic;  -- B0
3981 
    X_19 : in    std_logic;  -- E\
3982 
    X_20 : inout std_logic   -- Vcc
3983 
);
3984 
end component SN74LS245N;
3985 
 
3986 
-- SN74LS247N: BCD to 7-segment decoder/driver (open collector)
3987 
-- SN74LS248N: BCD to 7-segment decoder/driver (2kR pullups)
3988 
-- SN74LS249N: BCD to 7-segment decoder (open collector)
3989 
 
3990 
-----------------------------------------------------------------------
3991 
-- SN74LS251N: 8-input multiplexer (3-state outputs)
3992 
-----------------------------------------------------------------------
3993 
component SN74LS251N is
3994 
generic(
3995 
    tQBLH  : time :=  18 ns;    -- Synthetic values, QB - Q delay
3996 
    tQBHL  : time :=  12 ns;
3997 
    tPS    : time :=  33 ns;
3998 
    tPI    : time :=  15 ns;
3999 
    tPZH   : time :=  20 ns;
4000 
    tPZL   : time :=  25 ns;
4001 
    tPHZ   : time :=  25 ns;
4002 
    tPLZ   : time :=  20 ns
4003 
);
4004 
port(
4005 
    X_1  : in    std_logic;  -- I3
4006 
    X_2  : in    std_logic;  -- I2
4007 
    X_3  : in    std_logic;  -- I1
4008 
    X_4  : in    std_logic;  -- I0
4009 
    X_5  : out   std_logic;  -- Z
4010 
    X_6  : out   std_logic;  -- Z\
4011 
    X_7  : in    std_logic;  -- OE\
4012 
    X_8  : inout std_logic;  -- GND
4013 
    X_9  : in    std_logic;  -- S2
4014 
    X_10 : in    std_logic;  -- S1
4015 
    X_11 : in    std_logic;  -- S0
4016 
    X_12 : in    std_logic;  -- I7
4017 
    X_13 : in    std_logic;  -- I6
4018 
    X_14 : in    std_logic;  -- I5
4019 
    X_15 : in    std_logic;  -- I4
4020 
    X_16 : inout std_logic   -- Vcc
4021 
);
4022 
end component SN74LS251N;
4023 
 
4024 
-----------------------------------------------------------------------
4025 
-- SN74LS253N: Dual 4-input multiplexer (3-state outputs)
4026 
-----------------------------------------------------------------------
4027 
component SN74LS253N is
4028 
generic(
4029 
    tPLH  : time := 29 ns;
4030 
    tPHL  : time := 24 ns;
4031 
    tPZX  : time := 22 ns;
4032 
    tPXZ  : time := 32 ns
4033 
);
4034 
port(
4035 
    X_1  : in    std_logic;  -- OEA\
4036 
    X_2  : in    std_logic;  -- S1
4037 
    X_3  : in    std_logic;  -- I3A
4038 
    X_4  : in    std_logic;  -- I2A
4039 
    X_5  : in    std_logic;  -- I1A
4040 
    X_6  : in    std_logic;  -- I0A
4041 
    X_7  : out   std_logic;  -- ZA
4042 
    X_8  : inout std_logic;  -- GND
4043 
    X_9  : out   std_logic;  -- ZB
4044 
    X_10 : in    std_logic;  -- I0B
4045 
    X_11 : in    std_logic;  -- I1B
4046 
    X_12 : in    std_logic;  -- I2B
4047 
    X_13 : in    std_logic;  -- I3B
4048 
    X_14 : in    std_logic;  -- S0
4049 
    X_15 : in    std_logic;  -- OEB\
4050 
    X_16 : inout std_logic   -- Vcc
4051 
);
4052 
end component SN74LS253N;
4053 
 
4054 
-----------------------------------------------------------------------
4055 
-- SN74LS256N: Dual 4-bit addressable latch
4056 
-----------------------------------------------------------------------
4057 
component SN74LS256N is
4058 
generic(
4059 
    tPXDA : time := 30 ns;
4060 
    tPHLC : time := 18 ns
4061 
);
4062 
port(
4063 
    X_1  : in    std_logic;  -- A0
4064 
    X_2  : in    std_logic;  -- A1
4065 
    X_3  : in    std_logic;  -- DA
4066 
    X_4  : out   std_logic;  -- O0A
4067 
    X_5  : out   std_logic;  -- O1A
4068 
    X_6  : out   std_logic;  -- O2A
4069 
    X_7  : out   std_logic;  -- O3A
4070 
    X_8  : inout std_logic;  -- GND
4071 
    X_9  : out   std_logic;  -- O0B
4072 
    X_10 : out   std_logic;  -- O1B
4073 
    X_11 : out   std_logic;  -- O2B
4074 
    X_12 : out   std_logic;  -- O3B
4075 
    X_13 : in    std_logic;  -- DB
4076 
    X_14 : in    std_logic;  -- E\
4077 
    X_15 : in    std_logic;  -- CL\
4078 
    X_16 : inout std_logic   -- Vcc
4079 
);
4080 
end component SN74LS256N;
4081 
 
4082 
-----------------------------------------------------------------------
4083 
-- SN74LS257N: Quad 2-input multiplexer (3-state outputs)
4084 
-----------------------------------------------------------------------
4085 
component SN74LS257N is
4086 
generic(
4087 
    tPI  : time := 18 ns;
4088 
    tPS  : time := 21 ns;
4089 
    tPE  : time := 30 ns
4090 
);
4091 
port(
4092 
    X_1  : in    std_logic;  -- S
4093 
    X_2  : in    std_logic;  -- I0A
4094 
    X_3  : in    std_logic;  -- I1A
4095 
    X_4  : out   std_logic;  -- ZA
4096 
    X_5  : in    std_logic;  -- I0B
4097 
    X_6  : in    std_logic;  -- I1B
4098 
    X_7  : out   std_logic;  -- ZB
4099 
    X_8  : inout std_logic;  -- GND
4100 
    X_9  : out   std_logic;  -- ZD
4101 
    X_10 : in    std_logic;  -- I1D
4102 
    X_11 : in    std_logic;  -- I0D
4103 
    X_12 : out   std_logic;  -- ZC
4104 
    X_13 : in    std_logic;  -- I1C
4105 
    X_14 : in    std_logic;  -- I0C
4106 
    X_15 : in    std_logic;  -- OE\
4107 
    X_16 : inout std_logic   -- Vcc
4108 
);
4109 
end component SN74LS257N;
4110 
 
4111 
-----------------------------------------------------------------------
4112 
-- SN74LS258N: Quad 2-input multiplexer (inverting 3-state outputs)
4113 
-----------------------------------------------------------------------
4114 
component SN74LS258N is
4115 
generic(
4116 
    tPI  : time := 18 ns;
4117 
    tPS  : time := 21 ns;
4118 
    tPE  : time := 30 ns
4119 
);
4120 
port(
4121 
    X_1  : in    std_logic;  -- S
4122 
    X_2  : in    std_logic;  -- I0A
4123 
    X_3  : in    std_logic;  -- I1A
4124 
    X_4  : out   std_logic;  -- ZA\
4125 
    X_5  : in    std_logic;  -- I0B
4126 
    X_6  : in    std_logic;  -- I1B
4127 
    X_7  : out   std_logic;  -- ZB\
4128 
    X_8  : inout std_logic;  -- GND
4129 
    X_9  : out   std_logic;  -- ZD\
4130 
    X_10 : in    std_logic;  -- I1D
4131 
    X_11 : in    std_logic;  -- I0D
4132 
    X_12 : out   std_logic;  -- ZC\
4133 
    X_13 : in    std_logic;  -- I1C
4134 
    X_14 : in    std_logic;  -- I0C
4135 
    X_15 : in    std_logic;  -- OE\
4136 
    X_16 : inout std_logic   -- Vcc
4137 
);
4138 
end component SN74LS258N;
4139 
 
4140 
-----------------------------------------------------------------------
4141 
-- SN74LS259N: 8-bit addressable latch
4142 
-----------------------------------------------------------------------
4143 
component SN74LS259N is
4144 
generic(
4145 
    tPXDA : time := 30 ns;
4146 
    tPHLC : time := 18 ns
4147 
);
4148 
port(
4149 
    X_1  : in    std_logic;  -- A0
4150 
    X_2  : in    std_logic;  -- A1
4151 
    X_3  : in    std_logic;  -- A2
4152 
    X_4  : out   std_logic;  -- Q0
4153 
    X_5  : out   std_logic;  -- Q1
4154 
    X_6  : out   std_logic;  -- Q2
4155 
    X_7  : out   std_logic;  -- Q3
4156 
    X_8  : inout std_logic;  -- GND
4157 
    X_9  : out   std_logic;  -- Q4
4158 
    X_10 : out   std_logic;  -- Q5
4159 
    X_11 : out   std_logic;  -- Q6
4160 
    X_12 : out   std_logic;  -- Q7
4161 
    X_13 : in    std_logic;  -- D
4162 
    X_14 : in    std_logic;  -- E\
4163 
    X_15 : in    std_logic;  -- CL\
4164 
    X_16 : inout std_logic   -- Vcc
4165 
);
4166 
end component SN74LS259N;
4167 
 
4168 
-----------------------------------------------------------------------
4169 
-- SN74LS260N: Dual 5-input NOR gate
4170 
-----------------------------------------------------------------------
4171 
component SN74LS260N is
4172 
generic(
4173 
    tPLH : time := 10 ns;
4174 
    tPHL : time := 12 ns
4175 
);
4176 
port(
4177 
    X_1  : in    std_logic;  -- I1A
4178 
    X_2  : in    std_logic;  -- I2A
4179 
    X_3  : in    std_logic;  -- I3A
4180 
    X_4  : in    std_logic;  -- I1B
4181 
    X_5  : out   std_logic;  -- ZA\
4182 
    X_6  : out   std_logic;  -- ZB\
4183 
    X_7  : inout std_logic;  -- GND
4184 
    X_8  : in    std_logic;  -- I2B
4185 
    X_9  : in    std_logic;  -- I3B
4186 
    X_10 : in    std_logic;  -- I4B
4187 
    X_11 : in    std_logic;  -- I5B
4188 
    X_12 : in    std_logic;  -- I4A
4189 
    X_13 : in    std_logic;  -- I5A
4190 
    X_14 : inout std_logic   -- Vcc
4191 
);
4192 
end component SN74LS260N;
4193 
 
4194 
-- SN74LS261N: 2-bit x 4-bit parallel binary multiplier
4195 
 
4196 
-----------------------------------------------------------------------
4197 
-- SN74LS266N: Quad 2-input XNOR gate (open collector)
4198 
-----------------------------------------------------------------------
4199 
component SN74LS266N is
4200 
generic(
4201 
    tPLH : time := 30 ns;
4202 
    tPHL : time := 30 ns
4203 
);
4204 
port(
4205 
    X_1  : in    std_logic;  -- 1A
4206 
    X_2  : in    std_logic;  -- 1B
4207 
    X_3  : out   std_logic;  -- 1Y\
4208 
    X_4  : out   std_logic;  -- 2Y\
4209 
    X_5  : in    std_logic;  -- 2A
4210 
    X_6  : in    std_logic;  -- 2B
4211 
    X_7  : inout std_logic;  -- GND
4212 
    X_8  : in    std_logic;  -- 3B
4213 
    X_9  : in    std_logic;  -- 3A
4214 
    X_10 : out   std_logic;  -- 3Y\
4215 
    X_11 : out   std_logic;  -- 4Y\
4216 
    X_12 : in    std_logic;  -- 4B
4217 
    X_13 : in    std_logic;  -- 4A
4218 
    X_14 : inout std_logic   -- Vcc
4219 
);
4220 
end component SN74LS266N;
4221 
 
4222 
-----------------------------------------------------------------------
4223 
-- SN74LS273N: 8-bit register, with Clear
4224 
-----------------------------------------------------------------------
4225 
component SN74LS273N is
4226 
generic(
4227 
    tPX  : time := 24 ns
4228 
);
4229 
port(
4230 
    X_1  : in    std_logic;  -- MR\
4231 
    X_2  : out   std_logic;  -- Q0
4232 
    X_3  : in    std_logic;  -- D0
4233 
    X_4  : in    std_logic;  -- D1
4234 
    X_5  : out   std_logic;  -- Q1
4235 
    X_6  : out   std_logic;  -- Q2
4236 
    X_7  : in    std_logic;  -- D2
4237 
    X_8  : in    std_logic;  -- D3
4238 
    X_9  : out   std_logic;  -- Q3
4239 
    X_10 : inout std_logic;  -- GND
4240 
    X_11 : in    std_logic;  -- CP
4241 
    X_12 : out   std_logic;  -- Q4
4242 
    X_13 : in    std_logic;  -- D4
4243 
    X_14 : in    std_logic;  -- D5
4244 
    X_15 : out   std_logic;  -- Q5
4245 
    X_16 : out   std_logic;  -- Q6
4246 
    X_17 : in    std_logic;  -- D6
4247 
    X_18 : in    std_logic;  -- D7
4248 
    X_19 : out   std_logic;  -- Q7
4249 
    X_20 : inout std_logic   -- Vcc
4250 
);
4251 
end component SN74LS273N;
4252 
 
4253 
-----------------------------------------------------------------------
4254 
-- SN74LS279N: Quad set/reset latch
4255 
-----------------------------------------------------------------------
4256 
component SN74LS279N is
4257 
generic(
4258 
    tPX  : time := 27 ns
4259 
);
4260 
port(
4261 
    X_1  : in    std_logic;  -- 1R\
4262 
    X_2  : in    std_logic;  -- 1S1\
4263 
    X_3  : in    std_logic;  -- 1S2\
4264 
    X_4  : out   std_logic;  -- 1Q
4265 
    X_5  : in    std_logic;  -- 2R\
4266 
    X_6  : in    std_logic;  -- 2S\
4267 
    X_7  : out   std_logic;  -- 2Q
4268 
    X_8  : inout std_logic;  -- GND
4269 
    X_9  : out   std_logic;  -- 3Q
4270 
    X_10 : in    std_logic;  -- 3S\
4271 
    X_11 : in    std_logic;  -- 3R1\
4272 
    X_12 : in    std_logic;  -- 3R2\
4273 
    X_13 : out   std_logic;  -- 4Q
4274 
    X_14 : in    std_logic;  -- 4S\
4275 
    X_15 : in    std_logic;  -- 4R\
4276 
    X_16 : inout std_logic   -- Vcc
4277 
);
4278 
end component SN74LS279N;
4279 
 
4280 
-----------------------------------------------------------------------
4281 
-- SN74LS280N: 9-bit parity generator/checker
4282 
-----------------------------------------------------------------------
4283 
component SN74LS280N is
4284 
generic(
4285 
    tPLH : time := 21 ns;
4286 
    tPHL : time := 18 ns
4287 
);
4288 
port(
4289 
    X_1  : in    std_logic;  -- I6
4290 
    X_2  : in    std_logic;  -- I7
4291 
                             --
4292 
    X_4  : in    std_logic;  -- I8
4293 
    X_5  : out   std_logic;  -- SE
4294 
    X_6  : out   std_logic;  -- SO
4295 
    X_7  : inout std_logic;  -- GND
4296 
    X_8  : in    std_logic;  -- I0
4297 
    X_9  : in    std_logic;  -- I1
4298 
    X_10 : in    std_logic;  -- I2
4299 
    X_11 : in    std_logic;  -- I3
4300 
    X_12 : in    std_logic;  -- I4
4301 
    X_13 : in    std_logic;  -- I5
4302 
    X_14 : inout std_logic   -- Vcc
4303 
);
4304 
end component SN74LS280N;
4305 
 
4306 
-----------------------------------------------------------------------
4307 
-- SN74LS283N: 4-bit binary full adder (with fast carry)
4308 
-----------------------------------------------------------------------
4309 
component SN74LS283N is
4310 
generic(
4311 
    tPLHS  : time := 24 ns;
4312 
    tPHLS  : time := 24 ns;
4313 
    tPLHC  : time := 17 ns;
4314 
    tPHLC  : time := 17 ns
4315 
);
4316 
port(
4317 
    X_1  : out   std_logic;  -- S1
4318 
    X_2  : in    std_logic;  -- B1
4319 
    X_3  : in    std_logic;  -- A1
4320 
    X_4  : out   std_logic;  -- S0
4321 
    X_5  : in    std_logic;  -- A0
4322 
    X_6  : in    std_logic;  -- B0
4323 
    X_7  : in    std_logic;  -- C0
4324 
    X_8  : inout std_logic;  -- GND
4325 
    X_9  : out   std_logic;  -- C4
4326 
    X_10 : out   std_logic;  -- S3
4327 
    X_11 : in    std_logic;  -- B3
4328 
    X_12 : in    std_logic;  -- A3
4329 
    X_13 : out   std_logic;  -- S2
4330 
    X_14 : in    std_logic;  -- A2
4331 
    X_15 : in    std_logic;  -- B2
4332 
    X_16 : inout std_logic   -- Vcc
4333 
);
4334 
end component SN74LS283N;
4335 
 
4336 
-----------------------------------------------------------------------
4337 
-- SN74LS289N: 64-bit random access memory (open collector)
4338 
-----------------------------------------------------------------------
4339 
component SN74LS289N is
4340 
generic(
4341 
    tPLC  : time     := 10 ns;
4342 
    tPLA  : time     := 37 ns;
4343 
    tSUD  : time     := 25 ns;
4344 
    tSUA  : time     := 10 ns
4345 
);
4346 
port(
4347 
    X_1   : in    std_logic;  -- A0
4348 
    X_2   : in    std_logic;  -- CS\
4349 
    X_3   : in    std_logic;  -- WE\
4350 
    X_4   : in    std_logic;  -- D1
4351 
    X_5   : out   std_logic;  -- Q1\
4352 
    X_6   : in    std_logic;  -- D2
4353 
    X_7   : out   std_logic;  -- Q2\
4354 
    X_8   : inout std_logic;  -- GND
4355 
    X_9   : out   std_logic;  -- Q3\
4356 
    X_10  : in    std_logic;  -- D3
4357 
    X_11  : out   std_logic;  -- Q4\
4358 
    X_12  : in    std_logic;  -- D4
4359 
    X_13  : in    std_logic;  -- A3
4360 
    X_14  : in    std_logic;  -- A2
4361 
    X_15  : in    std_logic;  -- A1
4362 
    X_16  : inout std_logic   -- Vcc
4363 
);
4364 
end component SN74LS289N;
4365 
 
4366 
-----------------------------------------------------------------------
4367 
-- SN74LS290N: BCD decade counter
4368 
-----------------------------------------------------------------------
4369 
component SN74LS290N is
4370 
generic(
4371 
    tPLH0 : time := 16 ns;
4372 
    tPHL0 : time := 18 ns;
4373 
    tPLH1 : time := 16 ns;
4374 
    tPHL1 : time := 21 ns;
4375 
    tPLH2 : time := 32 ns;
4376 
    tPHL2 : time := 35 ns;
4377 
    tPLH3 : time := 32 ns;
4378 
    tPHL3 : time := 35 ns
4379 
);
4380 
port(
4381 
    X_1  : in    std_logic;  -- MS1
4382 
                             --
4383 
    X_3  : in    std_logic;  -- MS2
4384 
    X_4  : out   std_logic;  -- Q2
4385 
    X_5  : out   std_logic;  -- Q1
4386 
                             --
4387 
    X_7  : inout std_logic;  -- GND
4388 
    X_8  : out   std_logic;  -- Q3
4389 
    X_9  : out   std_logic;  -- Q0
4390 
    X_10 : in    std_logic;  -- CP0\
4391 
    X_11 : in    std_logic;  -- CP1\
4392 
    X_12 : in    std_logic;  -- MR1
4393 
    X_13 : in    std_logic;  -- MR2
4394 
    X_14 : inout std_logic   -- Vcc
4395 
);
4396 
end component SN74LS290N;
4397 
 
4398 
-- SN74LS292N: Programmable frequency divider / digital timer
4399 
 
4400 
-----------------------------------------------------------------------
4401 
-- SN74LS293N: 4-bit binary counter
4402 
-----------------------------------------------------------------------
4403 
component SN74LS293N is
4404 
generic(
4405 
    tPLH0 : time := 16 ns;
4406 
    tPHL0 : time := 18 ns;
4407 
    tPLH1 : time := 16 ns;
4408 
    tPHL1 : time := 21 ns;
4409 
    tPLH2 : time := 32 ns;
4410 
    tPHL2 : time := 35 ns;
4411 
    tPLH3 : time := 32 ns;
4412 
    tPHL3 : time := 35 ns
4413 
);
4414 
port(
4415 
                             --
4416 
                             --
4417 
                             --
4418 
    X_4  : out   std_logic;  -- Q2
4419 
    X_5  : out   std_logic;  -- Q1
4420 
                             --
4421 
    X_7  : inout std_logic;  -- GND
4422 
    X_8  : out   std_logic;  -- Q3
4423 
    X_9  : out   std_logic;  -- Q0
4424 
    X_10 : in    std_logic;  -- CP0\
4425 
    X_11 : in    std_logic;  -- CP1\
4426 
    X_12 : in    std_logic;  -- MR1
4427 
    X_13 : in    std_logic;  -- MR2
4428 
    X_14 : inout std_logic   -- Vcc
4429 
);
4430 
end component SN74LS293N;
4431 
 
4432 
-- SN74LS294N: Programmable frequency divider / digital timer
4433 
 
4434 
-----------------------------------------------------------------------
4435 
-- SN74LS295AN: 4-bit shift register (3-state outputs)
4436 
-----------------------------------------------------------------------
4437 
component SN74LS295AN is
4438 
generic(
4439 
    tPLH : time := 30 ns;
4440 
    tPHL : time := 26 ns;
4441 
    tPZH : time := 18 ns;
4442 
    tPZL : time := 20 ns;
4443 
    tPHZ : time := 24 ns;
4444 
    tPLZ : time := 20 ns
4445 
);
4446 
port(
4447 
    X_1  : in    std_logic;  -- DS
4448 
    X_2  : in    std_logic;  -- P0
4449 
    X_3  : in    std_logic;  -- P1
4450 
    X_4  : in    std_logic;  -- P2
4451 
    X_5  : in    std_logic;  -- P3
4452 
    X_6  : in    std_logic;  -- PE
4453 
    X_7  : inout std_logic;  -- GND
4454 
    X_8  : in    std_logic;  -- OE
4455 
    X_9  : in    std_logic;  -- CP\
4456 
    X_10 : out   std_logic;  -- Q3
4457 
    X_11 : out   std_logic;  -- Q2
4458 
    X_12 : out   std_logic;  -- Q1
4459 
    X_13 : out   std_logic;  -- Q0
4460 
    X_14 : inout std_logic   -- Vcc
4461 
);
4462 
end component SN74LS295AN;
4463 
 
4464 
-----------------------------------------------------------------------
4465 
-- SN74LS298N: Quad 2-port register (multiplexer with storage)
4466 
-----------------------------------------------------------------------
4467 
component SN74LS298N is
4468 
generic(
4469 
    tPLH : time := 25 ns;
4470 
    tPHL : time := 25 ns
4471 
);
4472 
port(
4473 
    X_1  : in    std_logic;  -- I1B
4474 
    X_2  : in    std_logic;  -- I1A
4475 
    X_3  : in    std_logic;  -- I0A
4476 
    X_4  : in    std_logic;  -- I0B
4477 
    X_5  : in    std_logic;  -- I1C
4478 
    X_6  : in    std_logic;  -- I1D
4479 
    X_7  : in    std_logic;  -- I0D
4480 
    X_8  : inout std_logic;  -- GND
4481 
    X_9  : in    std_logic;  -- I0C
4482 
    X_10 : in    std_logic;  -- S
4483 
    X_11 : in    std_logic;  -- CP\
4484 
    X_12 : out   std_logic;  -- QD
4485 
    X_13 : out   std_logic;  -- QC
4486 
    X_14 : out   std_logic;  -- QB
4487 
    X_15 : out   std_logic;  -- QA
4488 
    X_16 : inout std_logic   -- Vcc
4489 
);
4490 
end component SN74LS298N;
4491 
 
4492 
-----------------------------------------------------------------------
4493 
-- SN74LS299N: 8-bit universal shift/storage register
4494 
-----------------------------------------------------------------------
4495 
component SN74LS299N is
4496 
generic(
4497 
    tPLH : time := 25 ns;
4498 
    tPHL : time := 29 ns;
4499 
    tPZH : time := 18 ns;
4500 
    tPZL : time := 23 ns;
4501 
    tPHZ : time := 15 ns;
4502 
    tPLZ : time := 15 ns;
4503 
    tRSD : time :=  3 ns     -- Extra delay after reset
4504 
);
4505 
port(
4506 
    X_1  : in    std_logic;  -- S0
4507 
    X_2  : in    std_logic;  -- OE1\
4508 
    X_3  : in    std_logic;  -- OE2\
4509 
    X_4  : inout std_logic;  -- IO6
4510 
    X_5  : inout std_logic;  -- IO4
4511 
    X_6  : inout std_logic;  -- IO2
4512 
    X_7  : inout std_logic;  -- IO0
4513 
    X_8  : out   std_logic;  -- Q0
4514 
    X_9  : in    std_logic;  -- MR\
4515 
    X_10 : inout std_logic;  -- GND
4516 
    X_11 : in    std_logic;  -- DS0
4517 
    X_12 : in    std_logic;  -- CP
4518 
    X_13 : inout std_logic;  -- IO1
4519 
    X_14 : inout std_logic;  -- IO3
4520 
    X_15 : inout std_logic;  -- IO5
4521 
    X_16 : inout std_logic;  -- IO7
4522 
    X_17 : out   std_logic;  -- Q7
4523 
    X_18 : in    std_logic;  -- DS7
4524 
    X_19 : in    std_logic;  -- S1
4525 
    X_20 : inout std_logic   -- Vcc
4526 
);
4527 
end component SN74LS299N;
4528 
 
4529 
-----------------------------------------------------------------------
4530 
-- SN74LS322N: 8-bit SIPO register (with sign extend)
4531 
-----------------------------------------------------------------------
4532 
component SN74LS322N is
4533 
generic(
4534 
    tPLH : time := 25 ns;
4535 
    tPHL : time := 30 ns;
4536 
    tPZH : time := 25 ns;
4537 
    tPZL : time := 30 ns;
4538 
    tPHZ : time := 23 ns;
4539 
    tPLZ : time := 23 ns;
4540 
    tRSD : time :=  3 ns     -- Extra delay after reset
4541 
);
4542 
port(
4543 
    X_1  : in    std_logic;  -- RE\
4544 
    X_2  : in    std_logic;  -- S/P\
4545 
    X_3  : in    std_logic;  -- D0
4546 
    X_4  : inout std_logic;  -- IO7
4547 
    X_5  : inout std_logic;  -- IO5
4548 
    X_6  : inout std_logic;  -- IO3
4549 
    X_7  : inout std_logic;  -- IO1
4550 
    X_8  : in    std_logic;  -- OE\
4551 
    X_9  : in    std_logic;  -- MR\
4552 
    X_10 : inout std_logic;  -- GND
4553 
    X_11 : in    std_logic;  -- CP
4554 
    X_12 : out   std_logic;  -- Q0
4555 
    X_13 : inout std_logic;  -- IO0
4556 
    X_14 : inout std_logic;  -- IO2
4557 
    X_15 : inout std_logic;  -- IO4
4558 
    X_16 : inout std_logic;  -- IO6
4559 
    X_17 : in    std_logic;  -- D1
4560 
    X_18 : in    std_logic;  -- SE\
4561 
    X_19 : in    std_logic;  -- S
4562 
    X_20 : inout std_logic   -- Vcc
4563 
);
4564 
end component SN74LS322N;
4565 
 
4566 
-----------------------------------------------------------------------
4567 
-- SN74LS323N: 8-bit universal shift/storage register
4568 
-----------------------------------------------------------------------
4569 
component SN74LS323N is
4570 
generic(
4571 
    tPLH : time := 25 ns;
4572 
    tPHL : time := 29 ns;
4573 
    tPZH : time := 18 ns;
4574 
    tPZL : time := 23 ns;
4575 
    tPHZ : time := 15 ns;
4576 
    tPLZ : time := 15 ns
4577 
);
4578 
port(
4579 
    X_1  : in    std_logic;  -- S0
4580 
    X_2  : in    std_logic;  -- OE1\
4581 
    X_3  : in    std_logic;  -- OE2\
4582 
    X_4  : inout std_logic;  -- IO6
4583 
    X_5  : inout std_logic;  -- IO4
4584 
    X_6  : inout std_logic;  -- IO2
4585 
    X_7  : inout std_logic;  -- IO0
4586 
    X_8  : out   std_logic;  -- Q0
4587 
    X_9  : in    std_logic;  -- SR\
4588 
    X_10 : inout std_logic;  -- GND
4589 
    X_11 : in    std_logic;  -- DSO
4590 
    X_12 : in    std_logic;  -- CP
4591 
    X_13 : inout std_logic;  -- IO1
4592 
    X_14 : inout std_logic;  -- IO3
4593 
    X_15 : inout std_logic;  -- IO5
4594 
    X_16 : inout std_logic;  -- IO7
4595 
    X_17 : out   std_logic;  -- Q7
4596 
    X_18 : in    std_logic;  -- DS7
4597 
    X_19 : in    std_logic;  -- S1
4598 
    X_20 : inout std_logic   -- Vcc
4599 
);
4600 
end component SN74LS323N;
4601 
 
4602 
-- SN74LS347N: BCD to 7-segment decoder/demultiplexer
4603 
-- SN74LS348N: 8-to-3 line priority encoder (3-state outputs)
4604 
 
4605 
-----------------------------------------------------------------------
4606 
-- SN74LS352N: Dual 4-input multiplexer
4607 
-----------------------------------------------------------------------
4608 
component SN74LS352N is
4609 
generic(
4610 
    tPLH : time := 22 ns;
4611 
    tPHL : time := 38 ns
4612 
);
4613 
port(
4614 
    X_1  : in    std_logic;  -- EA\
4615 
    X_2  : in    std_logic;  -- S1
4616 
    X_3  : in    std_logic;  -- I3A
4617 
    X_4  : in    std_logic;  -- I2A
4618 
    X_5  : in    std_logic;  -- I1A
4619 
    X_6  : in    std_logic;  -- I0A
4620 
    X_7  : out   std_logic;  -- ZA\
4621 
    X_8  : inout std_logic;  -- GND
4622 
    X_9  : out   std_logic;  -- ZB\
4623 
    X_10 : in    std_logic;  -- I0B
4624 
    X_11 : in    std_logic;  -- I1B
4625 
    X_12 : in    std_logic;  -- I2B
4626 
    X_13 : in    std_logic;  -- I3B
4627 
    X_14 : in    std_logic;  -- S0
4628 
    X_15 : in    std_logic;  -- EB\
4629 
    X_16 : inout std_logic   -- Vcc
4630 
);
4631 
end component SN74LS352N;
4632 
 
4633 
-----------------------------------------------------------------------
4634 
-- SN74LS353N: Dual 4-input multiplexer (3-state outputs)
4635 
-----------------------------------------------------------------------
4636 
component SN74LS353N is
4637 
generic(
4638 
    tPLH  : time := 24 ns;
4639 
    tPHL  : time := 32 ns;
4640 
    tPZX  : time := 18 ns;
4641 
    tPXZ  : time := 18 ns
4642 
);
4643 
port(
4644 
    X_1  : in    std_logic;  -- OEA\
4645 
    X_2  : in    std_logic;  -- S1
4646 
    X_3  : in    std_logic;  -- I3A
4647 
    X_4  : in    std_logic;  -- I2A
4648 
    X_5  : in    std_logic;  -- I1A
4649 
    X_6  : in    std_logic;  -- I0A
4650 
    X_7  : out   std_logic;  -- ZA\
4651 
    X_8  : inout std_logic;  -- GND
4652 
    X_9  : out   std_logic;  -- ZB\
4653 
    X_10 : in    std_logic;  -- I0B
4654 
    X_11 : in    std_logic;  -- I1B
4655 
    X_12 : in    std_logic;  -- I2B
4656 
    X_13 : in    std_logic;  -- I3B
4657 
    X_14 : in    std_logic;  -- S0
4658 
    X_15 : in    std_logic;  -- OEB\
4659 
    X_16 : inout std_logic   -- Vcc
4660 
);
4661 
end component SN74LS353N;
4662 
 
4663 
-- SN74LS354N: 8-to-1 line selector/multiplexer/register
4664 
-- SN74LS355N: 8-to-1 line selector/multiplexer/register
4665 
-- SN74LS356N: 8-to-1 line selector/multiplexer/register
4666 
 
4667 
-----------------------------------------------------------------------
4668 
-- SN74LS365AN: Hex 3-state buffer
4669 
-----------------------------------------------------------------------
4670 
component SN74LS365AN is
4671 
generic(
4672 
    tPLH : time := 16 ns;
4673 
    tPHL : time := 22 ns;
4674 
    tPZH : time := 24 ns;
4675 
    tPZL : time := 30 ns;
4676 
    tPHZ : time := 20 ns;
4677 
    tPLZ : time := 25 ns
4678 
);
4679 
port(
4680 
    X_1  : in    std_logic;  -- E1\
4681 
    X_2  : in    std_logic;  -- A1
4682 
    X_3  : out   std_logic;  -- Y1
4683 
    X_4  : in    std_logic;  -- A2
4684 
    X_5  : out   std_logic;  -- Y2
4685 
    X_6  : in    std_logic;  -- A3
4686 
    X_7  : out   std_logic;  -- Y3
4687 
    X_8  : inout std_logic;  -- GND
4688 
    X_9  : out   std_logic;  -- Y4
4689 
    X_10 : in    std_logic;  -- A4
4690 
    X_11 : out   std_logic;  -- Y5
4691 
    X_12 : in    std_logic;  -- A5
4692 
    X_13 : out   std_logic;  -- Y6
4693 
    X_14 : in    std_logic;  -- A6
4694 
    X_15 : in    std_logic;  -- E2\
4695 
    X_16 : inout std_logic   -- Vcc
4696 
);
4697 
end component SN74LS365AN;
4698 
 
4699 
-----------------------------------------------------------------------
4700 
-- SN74LS366AN: Hex 3-state inverter buffer
4701 
-----------------------------------------------------------------------
4702 
component SN74LS366AN is
4703 
generic(
4704 
    tPLH : time := 16 ns;
4705 
    tPHL : time := 22 ns;
4706 
    tPZH : time := 24 ns;
4707 
    tPZL : time := 30 ns;
4708 
    tPHZ : time := 20 ns;
4709 
    tPLZ : time := 25 ns
4710 
);
4711 
port(
4712 
    X_1  : in    std_logic;  -- E1\
4713 
    X_2  : in    std_logic;  -- A1
4714 
    X_3  : out   std_logic;  -- Y1\
4715 
    X_4  : in    std_logic;  -- A2
4716 
    X_5  : out   std_logic;  -- Y2\
4717 
    X_6  : in    std_logic;  -- A3
4718 
    X_7  : out   std_logic;  -- Y3\
4719 
    X_8  : inout std_logic;  -- GND
4720 
    X_9  : out   std_logic;  -- Y4\
4721 
    X_10 : in    std_logic;  -- A4
4722 
    X_11 : out   std_logic;  -- Y5\
4723 
    X_12 : in    std_logic;  -- A5
4724 
    X_13 : out   std_logic;  -- Y6\
4725 
    X_14 : in    std_logic;  -- A6
4726 
    X_15 : in    std_logic;  -- E2\
4727 
    X_16 : inout std_logic   -- Vcc
4728 
);
4729 
end component SN74LS366AN;
4730 
 
4731 
-----------------------------------------------------------------------
4732 
-- SN74LS367AN: Hex 3-state buffer (2 & 4-bit sections)
4733 
-----------------------------------------------------------------------
4734 
component SN74LS367AN is
4735 
generic(
4736 
    tPLH : time := 16 ns;
4737 
    tPHL : time := 22 ns;
4738 
    tPZH : time := 24 ns;
4739 
    tPZL : time := 30 ns;
4740 
    tPHZ : time := 20 ns;
4741 
    tPLZ : time := 25 ns
4742 
);
4743 
port(
4744 
    X_1  : in    std_logic;  -- E14\
4745 
    X_2  : in    std_logic;  -- A1
4746 
    X_3  : out   std_logic;  -- Y1
4747 
    X_4  : in    std_logic;  -- A2
4748 
    X_5  : out   std_logic;  -- Y2
4749 
    X_6  : in    std_logic;  -- A3
4750 
    X_7  : out   std_logic;  -- Y3
4751 
    X_8  : inout std_logic;  -- GND
4752 
    X_9  : out   std_logic;  -- Y4
4753 
    X_10 : in    std_logic;  -- A4
4754 
    X_11 : out   std_logic;  -- Y5
4755 
    X_12 : in    std_logic;  -- A5
4756 
    X_13 : out   std_logic;  -- Y6
4757 
    X_14 : in    std_logic;  -- A6
4758 
    X_15 : in    std_logic;  -- E56\
4759 
    X_16 : inout std_logic   -- Vcc
4760 
);
4761 
end component SN74LS367AN;
4762 
 
4763 
-----------------------------------------------------------------------
4764 
-- SN74LS368AN: Hex 3-state inverter/buffer (2 & 4-bit sections)
4765 
-----------------------------------------------------------------------
4766 
component SN74LS368AN is
4767 
generic(
4768 
    tPLH : time := 16 ns;
4769 
    tPHL : time := 22 ns;
4770 
    tPZH : time := 24 ns;
4771 
    tPZL : time := 30 ns;
4772 
    tPHZ : time := 20 ns;
4773 
    tPLZ : time := 25 ns
4774 
);
4775 
port(
4776 
    X_1  : in    std_logic;  -- E14\
4777 
    X_2  : in    std_logic;  -- A1
4778 
    X_3  : out   std_logic;  -- Y1\
4779 
    X_4  : in    std_logic;  -- A2
4780 
    X_5  : out   std_logic;  -- Y2\
4781 
    X_6  : in    std_logic;  -- A3
4782 
    X_7  : out   std_logic;  -- Y3\
4783 
    X_8  : inout std_logic;  -- GND
4784 
    X_9  : out   std_logic;  -- Y4\
4785 
    X_10 : in    std_logic;  -- A4
4786 
    X_11 : out   std_logic;  -- Y5\
4787 
    X_12 : in    std_logic;  -- A5
4788 
    X_13 : out   std_logic;  -- Y6\
4789 
    X_14 : in    std_logic;  -- A6
4790 
    X_15 : in    std_logic;  -- E56\
4791 
    X_16 : inout std_logic   -- Vcc
4792 
);
4793 
end component SN74LS368AN;
4794 
 
4795 
-----------------------------------------------------------------------
4796 
-- SN74LS373N: Octal transparent latch (3-state outputs)
4797 
-----------------------------------------------------------------------
4798 
component SN74LS373N is
4799 
generic(
4800 
    tPLH : time := 18 ns;
4801 
    tPHL : time := 20 ns;
4802 
    tPZH : time := 28 ns;
4803 
    tPZL : time := 36 ns;
4804 
    tPHZ : time := 20 ns;
4805 
    tPLZ : time := 25 ns
4806 
);
4807 
port(
4808 
    X_1  : in    std_logic;  -- OE\
4809 
    X_2  : out   std_logic;  -- Q0
4810 
    X_3  : in    std_logic;  -- D0
4811 
    X_4  : in    std_logic;  -- D1
4812 
    X_5  : out   std_logic;  -- Q1
4813 
    X_6  : out   std_logic;  -- Q2
4814 
    X_7  : in    std_logic;  -- D2
4815 
    X_8  : in    std_logic;  -- D3
4816 
    X_9  : out   std_logic;  -- Q3
4817 
    X_10 : inout std_logic;  -- GND
4818 
    X_11 : in    std_logic;  -- LE
4819 
    X_12 : out   std_logic;  -- Q4
4820 
    X_13 : in    std_logic;  -- D4
4821 
    X_14 : in    std_logic;  -- D5
4822 
    X_15 : out   std_logic;  -- Q5
4823 
    X_16 : out   std_logic;  -- Q6
4824 
    X_17 : in    std_logic;  -- D6
4825 
    X_18 : in    std_logic;  -- D7
4826 
    X_19 : out   std_logic;  -- Q7
4827 
    X_20 : inout std_logic   -- Vcc
4828 
);
4829 
end component SN74LS373N;
4830 
 
4831 
-----------------------------------------------------------------------
4832 
-- SN74LS374N: Octal D-flipflop (3-state outputs)
4833 
-----------------------------------------------------------------------
4834 
component SN74LS374N is
4835 
generic(
4836 
    tPLH : time := 18 ns;
4837 
    tPHL : time := 20 ns;
4838 
    tPZH : time := 28 ns;
4839 
    tPZL : time := 36 ns;
4840 
    tPHZ : time := 20 ns;
4841 
    tPLZ : time := 25 ns
4842 
);
4843 
port(
4844 
    X_1  : in    std_logic;  -- OE\
4845 
    X_2  : out   std_logic;  -- Q0
4846 
    X_3  : in    std_logic;  -- D0
4847 
    X_4  : in    std_logic;  -- D1
4848 
    X_5  : out   std_logic;  -- Q1
4849 
    X_6  : out   std_logic;  -- Q2
4850 
    X_7  : in    std_logic;  -- D2
4851 
    X_8  : in    std_logic;  -- D3
4852 
    X_9  : out   std_logic;  -- Q3
4853 
    X_10 : inout std_logic;  -- GND
4854 
    X_11 : in    std_logic;  -- CP
4855 
    X_12 : out   std_logic;  -- Q4
4856 
    X_13 : in    std_logic;  -- D4
4857 
    X_14 : in    std_logic;  -- D5
4858 
    X_15 : out   std_logic;  -- Q5
4859 
    X_16 : out   std_logic;  -- Q6
4860 
    X_17 : in    std_logic;  -- D6
4861 
    X_18 : in    std_logic;  -- D7
4862 
    X_19 : out   std_logic;  -- Q7
4863 
    X_20 : inout std_logic   -- Vcc
4864 
);
4865 
end component SN74LS374N;
4866 
 
4867 
-----------------------------------------------------------------------
4868 
-- SN74LS375N: 4-bit latch
4869 
-----------------------------------------------------------------------
4870 
component SN74LS375N is
4871 
generic(
4872 
    tSETUP : time := 20 ns;     -- Setup time before clock
4873 
    tPLHCP : time := 40 ns;     -- Rising
4874 
    tPHLCP : time := 25 ns      -- Ralling
4875 
);
4876 
port(
4877 
    X_1  : in    std_logic;  -- D1
4878 
    X_2  : out   std_logic;  -- Q1\
4879 
    X_3  : out   std_logic;  -- Q1
4880 
    X_4  : in    std_logic;  -- E12
4881 
    X_5  : out   std_logic;  -- Q2
4882 
    X_6  : out   std_logic;  -- Q2\
4883 
    X_7  : in    std_logic;  -- D2
4884 
    X_8  : inout std_logic;  -- GND
4885 
    X_9  : in    std_logic;  -- D3
4886 
    X_10 : out   std_logic;  -- Q3\
4887 
    X_11 : out   std_logic;  -- Q3
4888 
    X_12 : in    std_logic;  -- E34
4889 
    X_13 : out   std_logic;  -- Q4
4890 
    X_14 : out   std_logic;  -- Q4\
4891 
    X_15 : in    std_logic;  -- D4
4892 
    X_16 : inout std_logic   -- Vcc
4893 
);
4894 
end component SN74LS375N;
4895 
 
4896 
-----------------------------------------------------------------------
4897 
-- SN74LS377N: Octal D-flipflop
4898 
-----------------------------------------------------------------------
4899 
component SN74LS377N is
4900 
generic(
4901 
    tPXX : time := 25 ns
4902 
);
4903 
port(
4904 
    X_1  : in    std_logic;  -- E\
4905 
    X_2  : out   std_logic;  -- Q0
4906 
    X_3  : in    std_logic;  -- D0
4907 
    X_4  : in    std_logic;  -- D1
4908 
    X_5  : out   std_logic;  -- Q1
4909 
    X_6  : out   std_logic;  -- Q2
4910 
    X_7  : in    std_logic;  -- D2
4911 
    X_8  : in    std_logic;  -- D3
4912 
    X_9  : out   std_logic;  -- Q3
4913 
    X_10 : inout std_logic;  -- GND
4914 
    X_11 : in    std_logic;  -- CP
4915 
    X_12 : out   std_logic;  -- Q4
4916 
    X_13 : in    std_logic;  -- D4
4917 
    X_14 : in    std_logic;  -- D5
4918 
    X_15 : out   std_logic;  -- Q5
4919 
    X_16 : out   std_logic;  -- Q6
4920 
    X_17 : in    std_logic;  -- D6
4921 
    X_18 : in    std_logic;  -- D7
4922 
    X_19 : out   std_logic;  -- Q7
4923 
    X_20 : inout std_logic   -- Vcc
4924 
);
4925 
end component SN74LS377N;
4926 
 
4927 
-----------------------------------------------------------------------
4928 
-- SN74LS378N: 6-bit D register
4929 
-----------------------------------------------------------------------
4930 
component SN74LS378N is
4931 
generic(
4932 
    tPXX : time := 27 ns
4933 
);
4934 
port(
4935 
    X_1  : in    std_logic;  -- E\
4936 
    X_2  : out   std_logic;  -- Q0
4937 
    X_3  : in    std_logic;  -- D0
4938 
    X_4  : in    std_logic;  -- D1
4939 
    X_5  : out   std_logic;  -- Q1
4940 
    X_6  : in    std_logic;  -- D2
4941 
    X_7  : out   std_logic;  -- Q2
4942 
    X_8  : inout std_logic;  -- GND
4943 
    X_9  : in    std_logic;  -- CP
4944 
    X_10 : out   std_logic;  -- Q3
4945 
    X_11 : in    std_logic;  -- D3
4946 
    X_12 : out   std_logic;  -- Q4
4947 
    X_13 : in    std_logic;  -- D4
4948 
    X_14 : in    std_logic;  -- D5
4949 
    X_15 : out   std_logic;  -- Q5
4950 
    X_16 : inout std_logic   -- Vcc
4951 
);
4952 
end component SN74LS378N;
4953 
 
4954 
-----------------------------------------------------------------------
4955 
-- SN74LS379N: 4-bit D register
4956 
-----------------------------------------------------------------------
4957 
component SN74LS379N is
4958 
generic(
4959 
    tPXX : time := 27 ns
4960 
);
4961 
port(
4962 
    X_1  : in    std_logic;  -- E\
4963 
    X_2  : out   std_logic;  -- Q0
4964 
    X_3  : out   std_logic;  -- Q0\
4965 
    X_4  : in    std_logic;  -- D0
4966 
    X_5  : in    std_logic;  -- D1
4967 
    X_6  : out   std_logic;  -- Q1\
4968 
    X_7  : out   std_logic;  -- Q1
4969 
    X_8  : inout std_logic;  -- GND
4970 
    X_9  : in    std_logic;  -- CP
4971 
    X_10 : out   std_logic;  -- Q2
4972 
    X_11 : out   std_logic;  -- Q2\
4973 
    X_12 : in    std_logic;  -- D2
4974 
    X_13 : in    std_logic;  -- D3
4975 
    X_14 : out   std_logic;  -- Q3\
4976 
    X_15 : out   std_logic;  -- Q3
4977 
    X_16 : inout std_logic   -- Vcc
4978 
);
4979 
end component SN74LS379N;
4980 
 
4981 
-- SN74LS381AN: Arithmetic/logic unit / function generator
4982 
-- SN74LS382AN: Arithmetic/logic unit / function generator
4983 
-- SN74LS384N: 8-bit serial/parallel 2's complement multiplier
4984 
-- SN74LS385N: Quad serial adder/subtractor
4985 
 
4986 
-----------------------------------------------------------------------
4987 
-- SN74LS386N: Quad 2-input XOR gate
4988 
-----------------------------------------------------------------------
4989 
component SN74LS386N is
4990 
generic(
4991 
    tPLH : time := 30 ns;
4992 
    tPHL : time := 22 ns
4993 
);
4994 
port(
4995 
    X_1  : in    std_logic;  -- 1A
4996 
    X_2  : in    std_logic;  -- 1B
4997 
    X_3  : out   std_logic;  -- 1Y\
4998 
    X_4  : out   std_logic;  -- 2Y\
4999 
    X_5  : in    std_logic;  -- 2A
5000 
    X_6  : in    std_logic;  -- 2B
5001 
    X_7  : inout std_logic;  -- GND
5002 
    X_8  : in    std_logic;  -- 3B
5003 
    X_9  : in    std_logic;  -- 3A
5004 
    X_10 : out   std_logic;  -- 3Y\
5005 
    X_11 : out   std_logic;  -- 4Y\
5006 
    X_12 : in    std_logic;  -- 4B
5007 
    X_13 : in    std_logic;  -- 4A
5008 
    X_14 : inout std_logic   -- Vcc
5009 
);
5010 
end component SN74LS386N;
5011 
 
5012 
-----------------------------------------------------------------------
5013 
-- SN74LS390N: Dual decade counter
5014 
-----------------------------------------------------------------------
5015 
component SN74LS390N is
5016 
generic(
5017 
    tPLH0 : time := 15 ns;
5018 
    tPHL0 : time := 15 ns;
5019 
    tPLH1 : time := 21 ns;
5020 
    tPHL1 : time := 21 ns;
5021 
    tPLH2 : time := 30 ns;
5022 
    tPHL2 : time := 30 ns;
5023 
    tPLH3 : time := 21 ns;
5024 
    tPHL3 : time := 21 ns
5025 
);
5026 
port(
5027 
    X_1  : in    std_logic;  -- CPA0\
5028 
    X_2  : in    std_logic;  -- MRA
5029 
    X_3  : out   std_logic;  -- Q0A
5030 
    X_4  : in    std_logic;  -- CPA1\
5031 
    X_5  : out   std_logic;  -- Q1A
5032 
    X_6  : out   std_logic;  -- Q2A
5033 
    X_7  : out   std_logic;  -- Q3A
5034 
    X_8  : inout std_logic;  -- GND
5035 
    X_9  : out   std_logic;  -- Q3B
5036 
    X_10 : out   std_logic;  -- Q2B
5037 
    X_11 : out   std_logic;  -- Q1B
5038 
    X_12 : in    std_logic;  -- CPB1\
5039 
    X_13 : out   std_logic;  -- Q0B
5040 
    X_14 : in    std_logic;  -- MRB
5041 
    X_15 : in    std_logic;  -- CPB0\
5042 
    X_16 : inout std_logic   -- Vcc
5043 
);
5044 
end component SN74LS390N;
5045 
 
5046 
-----------------------------------------------------------------------
5047 
-- SN74LS393N: Dual 4-bit binary counter
5048 
-----------------------------------------------------------------------
5049 
component SN74LS393N is
5050 
generic(
5051 
    tPLH0 : time := 15 ns;
5052 
    tPHL0 : time := 15 ns;
5053 
    tPLH1 : time := 30 ns;
5054 
    tPHL1 : time := 30 ns;
5055 
    tPLH2 : time := 40 ns;
5056 
    tPHL2 : time := 40 ns;
5057 
    tPLH3 : time := 54 ns;
5058 
    tPHL3 : time := 54 ns
5059 
);
5060 
port(
5061 
    X_1  : in    std_logic;  -- CPA\
5062 
    X_2  : in    std_logic;  -- MRA
5063 
    X_3  : out   std_logic;  -- Q0A
5064 
    X_4  : out   std_logic;  -- Q1A
5065 
    X_5  : out   std_logic;  -- Q2A
5066 
    X_6  : out   std_logic;  -- Q3A
5067 
    X_7  : inout std_logic;  -- GND
5068 
    X_8  : out   std_logic;  -- Q3B
5069 
    X_9  : out   std_logic;  -- Q2B
5070 
    X_10 : out   std_logic;  -- Q1B
5071 
    X_11 : out   std_logic;  -- Q0B
5072 
    X_12 : in    std_logic;  -- MRB
5073 
    X_13 : in    std_logic;  -- CPB\
5074 
    X_14 : inout std_logic   -- Vcc
5075 
);
5076 
end component SN74LS393N;
5077 
 
5078 
-----------------------------------------------------------------------
5079 
-- SN74LS395N: 4-bit shift register (3-state outputs)
5080 
-----------------------------------------------------------------------
5081 
component SN74LS395N is
5082 
generic(
5083 
    tPLH : time := 35 ns;
5084 
    tPHL : time := 25 ns;
5085 
    tPZH : time := 20 ns;
5086 
    tPZL : time := 20 ns;
5087 
    tPHZ : time := 17 ns;
5088 
    tPLZ : time := 23 ns
5089 
);
5090 
port(
5091 
    X_1  : in    std_logic;  -- MR\
5092 
    X_2  : in    std_logic;  -- DS
5093 
    X_3  : in    std_logic;  -- P0
5094 
    X_4  : in    std_logic;  -- P1
5095 
    X_5  : in    std_logic;  -- P2
5096 
    X_6  : in    std_logic;  -- P3
5097 
    X_7  : in    std_logic;  -- S
5098 
    X_8  : inout std_logic;  -- GND
5099 
    X_9  : in    std_logic;  -- OE\
5100 
    X_10 : in    std_logic;  -- CP\
5101 
    X_11 : out   std_logic;  -- Q3
5102 
    X_12 : out   std_logic;  -- O3
5103 
    X_13 : out   std_logic;  -- O2
5104 
    X_14 : out   std_logic;  -- O1
5105 
    X_15 : out   std_logic;  -- O0
5106 
    X_16 : inout std_logic   -- Vcc
5107 
);
5108 
end component SN74LS395N;
5109 
 
5110 
-- SN74LS396N: Octal storage register
5111 
-- SN74LS398N: Quad 2-port register (registered multiplexer)
5112 
-- SN74LS399N: Quad 2-port register (registered multiplexer)
5113 
-- SN74LS422N: Retriggerable monostable multivibrator
5114 
-- SN74LS423N: Retriggerable monostable multivibrator
5115 
-- SN74LS445N: BCD-to-decimal decoder/driver
5116 
-- SN74LS447N: BCD to 7-segment decoder/driver
5117 
-- SN74LS465N: Octal buffer (3-state outputs)
5118 
-- SN74LS466N: Octal buffer (3-state outputs)
5119 
-- SN74LS467N: Octal buffer (3-state outputs)
5120 
-- SN74LS468N: Octal buffer (3-state outputs)
5121 
 
5122 
-----------------------------------------------------------------------
5123 
-- SN74LS490N: Dual decade counter
5124 
-----------------------------------------------------------------------
5125 
component SN74LS490N is
5126 
generic(
5127 
    tPLH0   : time := 15 ns;
5128 
    tPHL0   : time := 15 ns;
5129 
    tPLH1   : time := 30 ns;
5130 
    tPHL1   : time := 30 ns;
5131 
    tPLH2   : time := 45 ns;
5132 
    tPHL2   : time := 45 ns;
5133 
    tPLH3   : time := 35 ns;
5134 
    tPHL3   : time := 35 ns
5135 
);
5136 
port(
5137 
    X_1  : in    std_logic;  -- CPA\
5138 
    X_2  : in    std_logic;  -- MRA
5139 
    X_3  : out   std_logic;  -- Q0A
5140 
    X_4  : in    std_logic;  -- MSA
5141 
    X_5  : out   std_logic;  -- Q1A
5142 
    X_6  : out   std_logic;  -- Q2A
5143 
    X_7  : out   std_logic;  -- Q3A
5144 
    X_8  : inout std_logic;  -- GND
5145 
    X_9  : out   std_logic;  -- Q3B
5146 
    X_10 : out   std_logic;  -- Q2B
5147 
    X_11 : out   std_logic;  -- Q1B
5148 
    X_12 : in    std_logic;  -- MSB
5149 
    X_13 : out   std_logic;  -- Q0B
5150 
    X_14 : in    std_logic;  -- MRB
5151 
    X_15 : in    std_logic;  -- CPB\
5152 
    X_16 : inout std_logic   -- Vcc
5153 
);
5154 
end component SN74LS490N;
5155 
 
5156 
-- SN74LS502N: 8-bit successive approximation register
5157 
-- SN74LS503N: 8-bit successive approximation register
5158 
-- SN74LS504N: 12-bit successive approximation register
5159 
 
5160 
-----------------------------------------------------------------------
5161 
-- SN74LS533N: Octal transparent latch (3-state inverting outputs)
5162 
-----------------------------------------------------------------------
5163 
component SN74LS533N is
5164 
generic(
5165 
    tPLH : time := 23 ns;
5166 
    tPHL : time := 25 ns;
5167 
    tPZH : time := 28 ns;
5168 
    tPZL : time := 36 ns;
5169 
    tPHZ : time := 20 ns;
5170 
    tPLZ : time := 25 ns
5171 
);
5172 
port(
5173 
    X_1  : in    std_logic;  -- OE\
5174 
    X_2  : out   std_logic;  -- O0\
5175 
    X_3  : in    std_logic;  -- D0
5176 
    X_4  : in    std_logic;  -- D1
5177 
    X_5  : out   std_logic;  -- O1\
5178 
    X_6  : out   std_logic;  -- O2\
5179 
    X_7  : in    std_logic;  -- D2
5180 
    X_8  : in    std_logic;  -- D3
5181 
    X_9  : out   std_logic;  -- O3\
5182 
    X_10 : inout std_logic;  -- GND
5183 
    X_11 : in    std_logic;  -- LE
5184 
    X_12 : out   std_logic;  -- O4\
5185 
    X_13 : in    std_logic;  -- D4
5186 
    X_14 : in    std_logic;  -- D5
5187 
    X_15 : out   std_logic;  -- O5\
5188 
    X_16 : out   std_logic;  -- O6\
5189 
    X_17 : in    std_logic;  -- D6
5190 
    X_18 : in    std_logic;  -- D7
5191 
    X_19 : out   std_logic;  -- O7\
5192 
    X_20 : inout std_logic   -- Vcc
5193 
);
5194 
end component SN74LS533N;
5195 
 
5196 
-----------------------------------------------------------------------
5197 
-- SN74LS534N: Octal D-flipflop (3-state outputs)
5198 
-----------------------------------------------------------------------
5199 
component SN74LS534N is
5200 
generic(
5201 
    tPLH : time := 18 ns;
5202 
    tPHL : time := 20 ns;
5203 
    tPZH : time := 28 ns;
5204 
    tPZL : time := 36 ns;
5205 
    tPHZ : time := 20 ns;
5206 
    tPLZ : time := 25 ns
5207 
);
5208 
port(
5209 
    X_1  : in    std_logic;  -- OE\
5210 
    X_2  : out   std_logic;  -- O0\
5211 
    X_3  : in    std_logic;  -- D0
5212 
    X_4  : in    std_logic;  -- D1
5213 
    X_5  : out   std_logic;  -- O1\
5214 
    X_6  : out   std_logic;  -- O2\
5215 
    X_7  : in    std_logic;  -- D2
5216 
    X_8  : in    std_logic;  -- D3
5217 
    X_9  : out   std_logic;  -- O3\
5218 
    X_10 : inout std_logic;  -- GND
5219 
    X_11 : in    std_logic;  -- CP
5220 
    X_12 : out   std_logic;  -- O4\
5221 
    X_13 : in    std_logic;  -- D4
5222 
    X_14 : in    std_logic;  -- D5
5223 
    X_15 : out   std_logic;  -- O5\
5224 
    X_16 : out   std_logic;  -- O6\
5225 
    X_17 : in    std_logic;  -- D6
5226 
    X_18 : in    std_logic;  -- D7
5227 
    X_19 : out   std_logic;  -- O7\
5228 
    X_20 : inout std_logic   -- Vcc
5229 
);
5230 
end component SN74LS534N;
5231 
 
5232 
-----------------------------------------------------------------------
5233 
-- SN74LS540N: Octal buffer/line driver (inverting 3-state outputs)
5234 
-----------------------------------------------------------------------
5235 
component SN74LS540N is
5236 
generic(
5237 
    tPLH : time := 14 ns;
5238 
    tPHL : time := 18 ns;
5239 
    tPZH : time := 23 ns;
5240 
    tPZL : time := 30 ns;
5241 
    tPHZ : time := 25 ns;
5242 
    tPLZ : time := 18 ns
5243 
);
5244 
port(
5245 
    X_1  : in    std_logic;  -- E1\
5246 
    X_2  : in    std_logic;  -- A0
5247 
    X_3  : in    std_logic;  -- A1
5248 
    X_4  : in    std_logic;  -- A2
5249 
    X_5  : in    std_logic;  -- A3
5250 
    X_6  : in    std_logic;  -- A4
5251 
    X_7  : in    std_logic;  -- A5
5252 
    X_8  : in    std_logic;  -- A6
5253 
    X_9  : in    std_logic;  -- A7
5254 
    X_10 : inout std_logic;  -- GND
5255 
    X_11 : out   std_logic;  -- Y7\
5256 
    X_12 : out   std_logic;  -- Y6\
5257 
    X_13 : out   std_logic;  -- Y5\
5258 
    X_14 : out   std_logic;  -- Y4\
5259 
    X_15 : out   std_logic;  -- Y3\
5260 
    X_16 : out   std_logic;  -- Y2\
5261 
    X_17 : out   std_logic;  -- Y1\
5262 
    X_18 : out   std_logic;  -- Y0\
5263 
    X_19 : in    std_logic;  -- E2\
5264 
    X_20 : inout std_logic   -- Vcc
5265 
);
5266 
end component SN74LS540N;
5267 
 
5268 
-----------------------------------------------------------------------
5269 
-- SN74LS541N: Octal buffer/line driver (3-state outputs)
5270 
-----------------------------------------------------------------------
5271 
component SN74LS541N is
5272 
generic(
5273 
    tPLH : time := 14 ns;
5274 
    tPHL : time := 18 ns;
5275 
    tPZH : time := 23 ns;
5276 
    tPZL : time := 30 ns;
5277 
    tPHZ : time := 25 ns;
5278 
    tPLZ : time := 18 ns
5279 
);
5280 
port(
5281 
    X_1  : in    std_logic;  -- E1\
5282 
    X_2  : in    std_logic;  -- A0
5283 
    X_3  : in    std_logic;  -- A1
5284 
    X_4  : in    std_logic;  -- A2
5285 
    X_5  : in    std_logic;  -- A3
5286 
    X_6  : in    std_logic;  -- A4
5287 
    X_7  : in    std_logic;  -- A5
5288 
    X_8  : in    std_logic;  -- A6
5289 
    X_9  : in    std_logic;  -- A7
5290 
    X_10 : inout std_logic;  -- GND
5291 
    X_11 : out   std_logic;  -- Y7
5292 
    X_12 : out   std_logic;  -- Y6
5293 
    X_13 : out   std_logic;  -- Y5
5294 
    X_14 : out   std_logic;  -- Y4
5295 
    X_15 : out   std_logic;  -- Y3
5296 
    X_16 : out   std_logic;  -- Y2
5297 
    X_17 : out   std_logic;  -- Y1
5298 
    X_18 : out   std_logic;  -- Y0
5299 
    X_19 : in    std_logic;  -- E2\
5300 
    X_20 : inout std_logic   -- Vcc
5301 
);
5302 
end component SN74LS541N;
5303 
 
5304 
-----------------------------------------------------------------------
5305 
-- SN74LS563N: Octal D-type latch (3-state outputs)
5306 
-----------------------------------------------------------------------
5307 
component SN74LS563N is
5308 
generic(
5309 
    tPLH : time := 23 ns;
5310 
    tPHL : time := 25 ns;
5311 
    tPZH : time := 28 ns;
5312 
    tPZL : time := 36 ns;
5313 
    tPHZ : time := 20 ns;
5314 
    tPLZ : time := 25 ns
5315 
);
5316 
port(
5317 
    X_1  : in    std_logic;  -- OE\
5318 
    X_2  : in    std_logic;  -- D0
5319 
    X_3  : in    std_logic;  -- D1
5320 
    X_4  : in    std_logic;  -- D2
5321 
    X_5  : in    std_logic;  -- D3
5322 
    X_6  : in    std_logic;  -- D4
5323 
    X_7  : in    std_logic;  -- D5
5324 
    X_8  : in    std_logic;  -- D6
5325 
    X_9  : in    std_logic;  -- D7
5326 
    X_10 : inout std_logic;  -- GND
5327 
    X_11 : in    std_logic;  -- LE
5328 
    X_12 : out   std_logic;  -- O7\
5329 
    X_13 : out   std_logic;  -- O6\
5330 
    X_14 : out   std_logic;  -- O5\
5331 
    X_15 : out   std_logic;  -- O4\
5332 
    X_16 : out   std_logic;  -- O3\
5333 
    X_17 : out   std_logic;  -- O2\
5334 
    X_18 : out   std_logic;  -- O1\
5335 
    X_19 : out   std_logic;  -- O0\
5336 
    X_20 : inout std_logic   -- Vcc
5337 
);
5338 
end component SN74LS563N;
5339 
 
5340 
-----------------------------------------------------------------------
5341 
-- SN74LS564N: Octal D-flipflop (3-state outputs)
5342 
-----------------------------------------------------------------------
5343 
component SN74LS564N is
5344 
generic(
5345 
    tPLH : time := 18 ns;
5346 
    tPHL : time := 20 ns;
5347 
    tPZH : time := 28 ns;
5348 
    tPZL : time := 36 ns;
5349 
    tPHZ : time := 20 ns;
5350 
    tPLZ : time := 25 ns
5351 
);
5352 
port(
5353 
    X_1  : in    std_logic;  -- OE\
5354 
    X_2  : in    std_logic;  -- D0
5355 
    X_3  : in    std_logic;  -- D1
5356 
    X_4  : in    std_logic;  -- D2
5357 
    X_5  : in    std_logic;  -- D3
5358 
    X_6  : in    std_logic;  -- D4
5359 
    X_7  : in    std_logic;  -- D5
5360 
    X_8  : in    std_logic;  -- D6
5361 
    X_9  : in    std_logic;  -- D7
5362 
    X_10 : inout std_logic;  -- GND
5363 
    X_11 : in    std_logic;  -- CP
5364 
    X_12 : out   std_logic;  -- O7\
5365 
    X_13 : out   std_logic;  -- O6\
5366 
    X_14 : out   std_logic;  -- O5\
5367 
    X_15 : out   std_logic;  -- O4\
5368 
    X_16 : out   std_logic;  -- O3\
5369 
    X_17 : out   std_logic;  -- O2\
5370 
    X_18 : out   std_logic;  -- O1\
5371 
    X_19 : out   std_logic;  -- O0\
5372 
    X_20 : inout std_logic   -- Vcc
5373 
);
5374 
end component SN74LS564N;
5375 
 
5376 
-- SN74LS568N: BCD decade up/down counter (3-state outputs)
5377 
-- SN74LS569N: 4-bit binary up/down counter (3-state outputs)
5378 
 
5379 
-----------------------------------------------------------------------
5380 
-- SN74LS573N: Octal D-type latch (3-state outputs)
5381 
-----------------------------------------------------------------------
5382 
component SN74LS573N is
5383 
generic(
5384 
    tPLH : time := 18 ns;
5385 
    tPHL : time := 20 ns;
5386 
    tPZH : time := 28 ns;
5387 
    tPZL : time := 36 ns;
5388 
    tPHZ : time := 20 ns;
5389 
    tPLZ : time := 25 ns
5390 
);
5391 
port(
5392 
    X_1  : in    std_logic;  -- OE\
5393 
    X_2  : in    std_logic;  -- D0
5394 
    X_3  : in    std_logic;  -- D1
5395 
    X_4  : in    std_logic;  -- D2
5396 
    X_5  : in    std_logic;  -- D3
5397 
    X_6  : in    std_logic;  -- D4
5398 
    X_7  : in    std_logic;  -- D5
5399 
    X_8  : in    std_logic;  -- D6
5400 
    X_9  : in    std_logic;  -- D7
5401 
    X_10 : inout std_logic;  -- GND
5402 
    X_11 : in    std_logic;  -- LE
5403 
    X_12 : out   std_logic;  -- O7\
5404 
    X_13 : out   std_logic;  -- O6\
5405 
    X_14 : out   std_logic;  -- O5\
5406 
    X_15 : out   std_logic;  -- O4\
5407 
    X_16 : out   std_logic;  -- O3\
5408 
    X_17 : out   std_logic;  -- O2\
5409 
    X_18 : out   std_logic;  -- O1\
5410 
    X_19 : out   std_logic;  -- O0\
5411 
    X_20 : inout std_logic   -- Vcc
5412 
);
5413 
end component SN74LS573N;
5414 
 
5415 
-----------------------------------------------------------------------
5416 
-- SN74LS574N: Octal D-flipflop (3-state outputs)
5417 
-----------------------------------------------------------------------
5418 
component SN74LS574N is
5419 
generic(
5420 
    tPLH : time := 18 ns;
5421 
    tPHL : time := 20 ns;
5422 
    tPZH : time := 28 ns;
5423 
    tPZL : time := 36 ns;
5424 
    tPHZ : time := 20 ns;
5425 
    tPLZ : time := 25 ns
5426 
);
5427 
port(
5428 
    X_1  : in    std_logic;  -- OE\
5429 
    X_2  : in    std_logic;  -- D0
5430 
    X_3  : in    std_logic;  -- D1
5431 
    X_4  : in    std_logic;  -- D2
5432 
    X_5  : in    std_logic;  -- D3
5433 
    X_6  : in    std_logic;  -- D4
5434 
    X_7  : in    std_logic;  -- D5
5435 
    X_8  : in    std_logic;  -- D6
5436 
    X_9  : in    std_logic;  -- D7
5437 
    X_10 : inout std_logic;  -- GND
5438 
    X_11 : in    std_logic;  -- CP
5439 
    X_12 : out   std_logic;  -- O7\
5440 
    X_13 : out   std_logic;  -- O6\
5441 
    X_14 : out   std_logic;  -- O5\
5442 
    X_15 : out   std_logic;  -- O4\
5443 
    X_16 : out   std_logic;  -- O3\
5444 
    X_17 : out   std_logic;  -- O2\
5445 
    X_18 : out   std_logic;  -- O1\
5446 
    X_19 : out   std_logic;  -- O0\
5447 
    X_20 : inout std_logic   -- Vcc
5448 
);
5449 
end component SN74LS574N;
5450 
 
5451 
-- SN74LS590N: 8-bit binary counter with output registers
5452 
-- SN74LS591N: 8-bit binary counter with output registers
5453 
-- SN74LS592N: 8-bit binary counter with input registers
5454 
-- SN74LS593N: 8-bit binary counter with input registers
5455 
-- SN74LS595N: 8-bit shift register with output latch
5456 
-- SN74LS596N: 8-bit shift register with output latch
5457 
-- SN74LS597N: 8-bit shift register with input latch
5458 
-- SN74LS598N: 8-bit shift register with input latch
5459 
-- SN74LS599N: 8-bit shift register with output latches
5460 
-- SN74LS604N: Octal 2-input multiplexed latch
5461 
-- SN74LS606N: Octal 2-input multiplexed latch
5462 
-- SN74LS607N: Octal 2-input multiplexed latch
5463 
-- SN74LS646N: Octal bus transceivers & registers
5464 
-- SN74LS668N: Synchronous 4-bit up/down decade counter
5465 
-- SN74LS669N: Synchronous 4-bit up/down binary counter
5466 
 
5467 
-----------------------------------------------------------------------
5468 
-- SN74LS670N: 4 x 4 register file (3-state outputs)
5469 
-----------------------------------------------------------------------
5470 
component SN74LS670N is
5471 
generic(
5472 
    tPLC  : time     := 35 ns;
5473 
    tPLA  : time     := 35 ns;
5474 
    tSUD  : time     := 10 ns;
5475 
    tSUA  : time     := 10 ns
5476 
);
5477 
port(
5478 
    X_1   : in    std_logic;  -- D2
5479 
    X_2   : in    std_logic;  -- D3
5480 
    X_3   : in    std_logic;  -- D4
5481 
    X_4   : in    std_logic;  -- RA1
5482 
    X_5   : in    std_logic;  -- RA0
5483 
    X_6   : out   std_logic;  -- O4
5484 
    X_7   : out   std_logic;  -- O3
5485 
    X_8   : inout std_logic;  -- GND
5486 
    X_9   : out   std_logic;  -- O2
5487 
    X_10  : out   std_logic;  -- O1
5488 
    X_11  : in    std_logic;  -- OE\
5489 
    X_12  : in    std_logic;  -- WE\
5490 
    X_13  : in    std_logic;  -- WA1
5491 
    X_14  : in    std_logic;  -- WA0
5492 
    X_15  : in    std_logic;  -- D1
5493 
    X_16  : inout std_logic   -- Vcc
5494 
);
5495 
end component SN74LS670N;
5496 
 
5497 
-- SN74LS671N: 4-bit universal shift register/latch (3-state output)
5498 
-- SN74LS672N: 4-bit universal shift register/latch (3-state output)
5499 
-- SN74LS673N: 16-bit shift register
5500 
-- SN74LS674N: 16-bit shift register
5501 
-- SN74LS681N: 4-bit parallel binary accumulator
5502 
-- SN74LS682N: 8-bit magnitude/identity comparator
5503 
-- SN74LS684N: 8-bit magnitude/identity comparator
5504 
-- SN74LS685N: 8-bit magnitude/identity comparator
5505 
-- SN74LS686N: 8-bit magnitude/identity comparator
5506 
-- SN74LS687N: 8-bit magnitude/identity comparator
5507 
-- SN74LS688N: 8-bit magnitude/identity comparator
5508 
-- SN74LS690N: Synchronous counter with output registers & muliplexed 3-state outputs
5509 
-- SN74LS691N: Synchronous counter with output registers & muliplexed 3-state outputs
5510 
-- SN74LS693N: Synchronous counter with output registers & muliplexed 3-state outputs
5511 
-- SN74LS696N: Synchronous up/down counter with output registers & muliplexed 3-state outputs
5512 
-- SN74LS697N: Synchronous up/down counter with output registers & muliplexed 3-state outputs
5513 
-- SN74LS699N: Synchronous up/down counter with output registers & muliplexed 3-state outputs
5514 
 
5515 
end package LSTTL;

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