OpenCores
URL https://opencores.org/ocsvn/ttl_library/ttl_library/trunk

Subversion Repositories ttl_library

[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_101.vhd] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 david237
-----------------------------------------------------------------------
2
-- Bipolar TTL models (VHDL)                                         --
3
-- David R Brooks                                                    --
4
-- June, 2016.  Perth, Australia                                     --
5
-- Compliance: VHDL 2008                                             --
6
-- Testbench for SN74H101N: JK edge-triggered flipflop: AND-OR input --
7
-----------------------------------------------------------------------
8
 
9
library ieee;
10
    use ieee.std_logic_1164.all;
11
    use ieee.std_logic_misc.all;
12
    use ieee.numeric_std.all;
13
    use work.LSTTL.all;
14
    use work.TTLPrivate.all;
15
 
16
entity Testbench_101 is     -- Top-level bench
17
generic(
18
    StimClk  : std_logic      := '1';
19
    CheckClk : std_logic      := '1';
20
    Period   : time           := 120 ns;
21
    Finish   : time           :=  20 us;
22
    SevLevel : severity_level := failure
23
);
24
end entity;
25
 
26
architecture Test of Testbench_101 is
27
    signal PS, J, K : std_logic;
28
    signal CLK      : std_logic;
29
    signal JC, BC   : unsigned(7 downto 0);         -- Test stimuli
30
    signal D,  E    : std_logic_vector(1 downto 0); -- Expected & actual results
31
 
32
    begin
33
    -----------------------------------------------------------------------
34
    -- Standard testbench components
35
    -----------------------------------------------------------------------
36
    TB: TTLBench
37
    generic map(
38
        StimClk  => StimClk,
39
        CheckClk => CheckClk,
40
        Period   => Period,
41
        Finish   => Finish,
42
        SevLevel => SevLevel
43
    )
44
    port map(
45
        J    => JC,
46
        B    => BC,
47
        CLK  => CLK,
48
        RS   => PS,
49
        D    => D,
50
        E    => E
51
    );
52
 
53
    -----------------------------------------------------------------------
54
    -- Generate expected results (with zero delays)
55
    -----------------------------------------------------------------------
56
 
57
    SIM: process(CLK, PS) is
58
        variable JK : std_logic_vector(1 downto 0);
59
    begin
60
        if    PS = '0' then     -- Here, set
61
            D(0) <= '1';
62
        elsif falling_edge(CLK) then
63
            JK := J & K;
64
            case JK is
65
                when "00"   => null;
66
                when "01"   => D(0) <= '0';
67
                when "10"   => D(0) <= '1';
68
                when "11"   => D(0) <= not D(0);
69
                when others => null;
70
            end case;
71
        end if;
72
    end process;
73
 
74
    D(1) <= not D(0);
75
 
76
    J <= (BC(0) and BC(1)) or (BC(2) and BC(3));
77
    K <= (BC(4) and BC(5)) or (BC(6) and BC(7));
78
 
79
    -----------------------------------------------------------------------
80
    -- Device Under Test...                        
81
    -----------------------------------------------------------------------
82
    DUT: SN74H101N
83
    port map(
84
    X_1  => BC(0),   -- J1A
85
    X_2  => BC(1),   -- J1B
86
    X_3  => BC(2),   -- J2A
87
    X_4  => BC(3),   -- J2B
88
    X_5  => PS,      -- SD\
89
    X_6  => E(0),    -- Q
90
    X_7  => open,    -- GND
91
    X_8  => E(1),    -- Q\
92
    X_9  => BC(4),   -- K1A
93
    X_10 => BC(5),   -- K1B
94
    X_11 => BC(6),   -- K2A
95
    X_12 => BC(7),   -- K2B
96
    X_13 => CLK,     -- CP
97
    X_14 => open     -- Vcc
98
);
99
end architecture Test;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.