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david237 |
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL) --
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-- David R Brooks --
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-- June, 2016. Perth, Australia --
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-- Compliance: VHDL 2008 --
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-- Testbench for SN74122N: Retriggerable resettable monostable --
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.numeric_std.all;
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use work.LSTTL.all;
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use work.TTLPrivate.all;
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entity Testbench_122 is -- Top-level bench
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end entity;
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architecture Test of Testbench_122 is
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signal S, Q : std_logic; -- Trigger & output
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signal W, N : std_logic; -- Wide & narrow windows
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begin
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S <= '0',
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'1' after 250 ns, '0' after 350 ns, -- Trigger, let it time out
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'1' after 15000 ns, '0' after 15100 ns, -- Trigger again
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'1' after 16000 ns, '0' after 16100 ns; -- This should retrigger
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-----------------------------------------------------------------------
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-- Generate expected results (with zero delays)
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-----------------------------------------------------------------------
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W <= '0',
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'1' after 220 ns, '0' after 10330 ns,
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'1' after 15020 ns, '0' after 26080 ns;
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N <= '0',
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'1' after 350 ns, '0' after 10250 ns,
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'1' after 15090 ns, '0' after 26000 ns;
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-----------------------------------------------------------------------
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-- Validate the results
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-----------------------------------------------------------------------
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process(W, N, Q) is
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begin
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if (rising_edge(W) and Q = '1') or -- W must rise before Q
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(rising_edge(N) and Q = '0') or -- Q must rise before N
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(falling_edge(N) and Q = '0') or -- N must fall before Q
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(falling_edge(W) and Q = '1') then -- Q must fall before W
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assert false
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report "Bad monostable pulse"
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severity failure;
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end if;
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end process;
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-----------------------------------------------------------------------
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-- Device Under Test...
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-----------------------------------------------------------------------
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DUT: SN74122N
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generic map(
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W => 10 us -- Pulse width
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)
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port map(
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X_1 => '0', -- A1\
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X_2 => '0', -- A2\
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X_3 => S, -- B1
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X_4 => '1', -- B2
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X_5 => '1', -- CD\
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X_6 => open, -- Q\
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X_7 => open, -- GND
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X_8 => Q, -- Q
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X_9 => open, -- Rint
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--
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X_11 => open, -- Cx
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--
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X_13 => open, -- RxCx
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X_14 => open -- Vcc
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);
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end architecture Test;
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