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david237 |
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL) --
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-- David R Brooks --
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-- June, 2016. Perth, Australia --
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-- Compliance: VHDL 2008 --
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-- Testbench for SN74123N: Dual retriggerable resettable monostable --
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.numeric_std.all;
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use work.LSTTL.all;
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use work.TTLPrivate.all;
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entity Testbench_123 is -- Top-level bench
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end entity;
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architecture Test of Testbench_123 is
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signal S, Q : std_logic_vector(1 downto 0); -- Triggers & outputs
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signal W, N : std_logic_vector(1 downto 0); -- Wide & narrow windows
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begin
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S(0) <= '0',
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'1' after 250 ns, '0' after 350 ns, -- Trigger, let it time out
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'1' after 15000 ns, '0' after 15100 ns, -- Trigger again
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'1' after 16000 ns, '0' after 16100 ns; -- This should retrigger
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S(1) <= '0',
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'1' after 250 ns, '0' after 350 ns, -- Trigger, let it time out
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'1' after 15000 ns, '0' after 15100 ns, -- Trigger again
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'1' after 16000 ns, '0' after 16100 ns; -- This should retrigger
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-----------------------------------------------------------------------
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-- Generate expected results (with zero delays)
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-----------------------------------------------------------------------
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W(0) <= '0',
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'1' after 220 ns, '0' after 9330 ns,
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'1' after 15020 ns, '0' after 25080 ns;
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N(0) <= '0',
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'1' after 350 ns, '0' after 9250 ns,
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'1' after 15090 ns, '0' after 25000 ns;
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W(1) <= '0',
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'1' after 220 ns, '0' after 10330 ns,
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'1' after 15020 ns, '0' after 26080 ns;
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N(1) <= '0',
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'1' after 350 ns, '0' after 10250 ns,
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'1' after 15090 ns, '0' after 26000 ns;
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-----------------------------------------------------------------------
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-- Validate the results
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-----------------------------------------------------------------------
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G: for i in Q'range generate
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begin
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process(W(i), N(i), Q(i)) is
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begin
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if (rising_edge(W(i)) and Q(i) = '1') or -- W must rise before Q
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(rising_edge(N(i)) and Q(i) = '0') or -- Q must rise before N
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(falling_edge(N(i)) and Q(i) = '0') or -- N must fall before Q
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(falling_edge(W(i)) and Q(i) = '1') then -- Q must fall before W
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assert false
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report "Bad monostable pulse"
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severity warning;
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end if;
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end process;
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end generate;
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-----------------------------------------------------------------------
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-- Device Under Test...
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-----------------------------------------------------------------------
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DUT: SN74123N
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generic map(
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W1 => 10 us, -- Pulse widths
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W2 => 9 us
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)
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port map(
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X_1 => '0', -- A1\
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X_2 => S(0), -- B1
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X_3 => '1', -- CD1\
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X_4 => open, -- Q1\
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X_5 => Q(1), -- Q2
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X_6 => open, -- Cx2
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X_7 => open, -- Rx2Cx2
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X_8 => open, -- GND
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X_9 => '0', -- A2\
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X_10 => S(1), -- B2
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X_11 => '1', -- CD2\
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X_12 => open, -- Q2\
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X_13 => Q(0), -- Q1
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X_14 => open, -- Cx1
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X_15 => open, -- Rx1Cx1
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X_16 => open -- Vcc
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);
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end architecture Test;
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