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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_126.vhd] - Blame information for rev 3

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1 3 david237
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL)                                         --
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-- David R Brooks                                                    --
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-- June, 2016.  Perth, Australia                                     --
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-- Compliance: VHDL 2008                                             --
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-- Testbench for SN74LS126N: Quad bus buffer (3-state outputs)       --
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-----------------------------------------------------------------------
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library ieee;
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    use ieee.std_logic_1164.all;
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    use ieee.std_logic_misc.all;
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    use ieee.numeric_std.all;
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    use work.LSTTL.all;
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    use work.TTLPrivate.all;
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entity Testbench_126 is     -- Top-level bench
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generic(
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    StimClk  : std_logic      := '1';
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    CheckClk : std_logic      := '0';
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    Period   : time           := 150 ns;
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    Finish   : time           :=  20 us;
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    SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_126 is
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    signal RS     : std_logic;
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    signal CLK    : std_logic;
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    signal JC, BC : unsigned(7 downto 0);           -- Test stimuli
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    signal D,  E  : std_logic_vector(3 downto 0);   -- Expected & actual results
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    subtype quad is std_logic_vector(3 downto 0);
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    signal  I, G : quad;
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begin
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    I <= quad(BC(7 downto 4));
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    G <= quad(BC(3 downto 0));
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    -----------------------------------------------------------------------
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    -- Standard testbench components
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    -----------------------------------------------------------------------
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    TB: TTLBench
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    generic map(
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        StimClk  => StimClk,
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        CheckClk => CheckClk,
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        Period   => Period,
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        Finish   => Finish,
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        SevLevel => SevLevel
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    )
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    port map(
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        J    => JC,
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        B    => BC,
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        CLK  => CLK,
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        RS   => RS,
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        D    => D,
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        E    => E
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    );
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    -----------------------------------------------------------------------
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    -- Generate expected results (with zero delays)
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    -----------------------------------------------------------------------
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    GG: for j in G'range generate
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    begin
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        D(j) <= I(j) when G(j) = '1' else 'Z';
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    end generate;
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    -----------------------------------------------------------------------
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    -- Device Under Test...                        
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    -----------------------------------------------------------------------
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    DUT: SN74LS126N
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    port map(
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    X_1  => G(0),  -- E1\
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    X_2  => I(0),  -- D1
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    X_3  => E(0),  -- Q1
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    X_4  => G(1),  -- E2\
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    X_5  => I(1),  -- D2
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    X_6  => E(1),  -- Q2
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    X_7  => open,  -- GND
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    X_8  => E(2),  -- Q3
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    X_9  => I(2),  -- D3
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    X_10 => G(2),  -- E3\
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    X_11 => E(3),  -- Q4
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    X_12 => I(3),  -- D4
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    X_13 => G(3),  -- E4\
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    X_14 => open   -- Vcc
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    );
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end architecture Test;

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