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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_14.vhd] - Blame information for rev 5
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david237 |
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL) --
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-- David R Brooks --
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-- June, 2016. Perth, Australia --
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-- Compliance: VHDL 2008 --
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-- Testbench for SN74LS14N: Hex Schmitt trigger inverter --
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.numeric_std.all;
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use work.LSTTL.all;
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use work.TTLPrivate.all;
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entity Testbench_14 is -- Top-level bench
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generic(
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StimClk : std_logic := '1';
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CheckClk : std_logic := '0';
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Period : time := 50 ns;
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Finish : time := 20 us;
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SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_14 is
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signal J, B : unsigned(5 downto 0); -- Test stimuli
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signal D, E : std_logic_vector(5 downto 0); -- Expected & actual results
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begin
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-----------------------------------------------------------------------
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-- Standard testbench components
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-----------------------------------------------------------------------
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TB: TTLBench
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generic map(
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StimClk => StimClk,
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CheckClk => CheckClk,
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Period => Period,
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Finish => Finish,
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SevLevel => SevLevel
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)
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port map(
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J => J,
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B => B,
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CLK => open,
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RS => open,
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D => D,
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E => E
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);
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-----------------------------------------------------------------------
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-- Generate expected results (with zero delays)
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-----------------------------------------------------------------------
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D(0) <= not J(0);
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D(1) <= not J(1);
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D(2) <= not J(2);
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D(3) <= not J(3);
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D(4) <= not J(4);
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D(5) <= not J(5);
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-----------------------------------------------------------------------
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-- Device Under Test...
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-----------------------------------------------------------------------
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DUT: SN74LS14N
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port map(
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X_1 => J(0), -- 1A
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X_2 => E(0), -- 1Y\
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X_3 => J(1), -- 2A
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X_4 => E(1), -- 2Y\
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X_5 => J(2), -- 3A
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X_6 => E(2), -- 3Y\
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X_7 => open, -- GND
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X_8 => E(3), -- 4Y\
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X_9 => J(3), -- 4A
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X_10 => E(4), -- 5Y\
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X_11 => J(4), -- 5A
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X_12 => E(5), -- 6Y\
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X_13 => J(5), -- 6A
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X_14 => open -- Vcc
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);
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end architecture Test;
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