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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_145.vhd] - Blame information for rev 3

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1 3 david237
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL)                                         --
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-- David R Brooks                                                    --
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-- June, 2016.  Perth, Australia                                     --
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-- Compliance: VHDL 2008                                             --
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-- Testbench for SN74145N: 1-of-10 decoder/driver (open collector)   --
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-----------------------------------------------------------------------
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library ieee;
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    use ieee.std_logic_1164.all;
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    use ieee.std_logic_misc.all;
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    use ieee.numeric_std.all;
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    use work.LSTTL.all;
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    use work.TTLPrivate.all;
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entity Testbench_145 is     -- Top-level bench
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generic(
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    StimClk  : std_logic      := '1';
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    CheckClk : std_logic      := '0';
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    Period   : time           := 120 ns;
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    Finish   : time           :=  20 us;
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    SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_145 is
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    signal J, B : unsigned(3 downto 0);         -- Test stimuli
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    signal D, E : std_logic_vector(9 downto 0); -- Expected & actual results
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    begin
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    -----------------------------------------------------------------------
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    -- Standard testbench components
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    -----------------------------------------------------------------------
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    TB: TTLBench
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    generic map(
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        StimClk  => StimClk,
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        CheckClk => CheckClk,
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        Period   => Period,
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        Finish   => Finish,
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        SevLevel => SevLevel
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    )
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    port map(
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        J   => J,
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        B   => B,
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        CLK => open,
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        RS  => open,
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        D   => D,
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        E   => E
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    );
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    -----------------------------------------------------------------------
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    -- Generate expected results (with zero delays)
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    -----------------------------------------------------------------------
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    process(J) is
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        variable N : natural;
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    begin
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        D <= (others => 'Z');       -- Default
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        N := TTL_to_integer(J(3 downto 0));
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        if N < 10 then
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            D(N) <= '0';
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        end if;
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    end process;
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    -----------------------------------------------------------------------
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    -- Device Under Test...                        
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    -----------------------------------------------------------------------
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    DUT: SN74145N
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    port map(
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    X_1  => E(0),  -- Q0\
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    X_2  => E(1),  -- Q1\
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    X_3  => E(2),  -- Q2\
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    X_4  => E(3),  -- Q3\
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    X_5  => E(4),  -- Q4\
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    X_6  => E(5),  -- Q5\
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    X_7  => E(6),  -- Q6\
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    X_8  => open,  -- GND
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    X_9  => E(7),  -- Q7\
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    X_10 => E(8),  -- Q8\
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    X_11 => E(9),  -- Q9\
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    X_12 => J(3),  -- A3
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    X_13 => J(2),  -- A2
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    X_14 => J(1),  -- A1
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    X_15 => J(0),  -- A0
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    X_16 => open   -- Vcc
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);
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end architecture Test;

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