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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_154.vhd] - Blame information for rev 3
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david237 |
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL) --
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-- David R Brooks --
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-- June, 2016. Perth, Australia --
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-- Compliance: VHDL 2008 --
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-- Testbench for SN74154N: 1-of-16 decoder/demultiplexer --
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.numeric_std.all;
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use work.LSTTL.all;
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use work.TTLPrivate.all;
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entity Testbench_154 is -- Top-level bench
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generic(
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StimClk : std_logic := '1';
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CheckClk : std_logic := '0';
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Period : time := 100 ns;
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Finish : time := 20 us;
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SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_154 is
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signal J, B : unsigned(5 downto 0); -- Test stimuli
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signal D, E : std_logic_vector(15 downto 0); -- Expected & actual results
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begin
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-----------------------------------------------------------------------
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-- Standard testbench components
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-----------------------------------------------------------------------
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TB: TTLBench
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generic map(
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StimClk => StimClk,
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CheckClk => CheckClk,
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Period => Period,
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Finish => Finish,
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SevLevel => SevLevel
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)
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port map(
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J => J,
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B => B,
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CLK => open,
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RS => open,
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D => D,
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E => E
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);
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-----------------------------------------------------------------------
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-- Generate expected results (with zero delays)
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-----------------------------------------------------------------------
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process(B) is
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variable chn : natural range 15 downto 0;
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variable EN : std_logic;
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begin
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chn := TTL_to_integer(B(5 downto 2));
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EN := B(1) or B(0);
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E <= (others => '1');
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E(chn) <= EN;
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end process;
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-----------------------------------------------------------------------
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-- Device Under Test...
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-----------------------------------------------------------------------
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DUT: SN74154N
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port map(
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X_1 => D(0), -- O0\
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X_2 => D(1), -- O1\
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X_3 => D(2), -- O2\
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X_4 => D(3), -- O3\
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X_5 => D(4), -- O4\
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X_6 => D(5), -- O5\
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X_7 => D(6), -- O6\
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X_8 => D(7), -- O7\
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X_9 => D(8), -- O8\
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X_10 => D(9), -- O9\
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X_11 => D(10), -- O10\
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X_12 => open, -- GND
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X_13 => D(11), -- O11\
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X_14 => D(12), -- O12\
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X_15 => D(13), -- O13\
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X_16 => D(14), -- O14\
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X_17 => D(15), -- O15\
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X_18 => B(0), -- E0\
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X_19 => B(1), -- E1\
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X_20 => B(5), -- A3
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X_21 => B(4), -- A2
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X_22 => B(3), -- A1
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X_23 => B(2), -- A0
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X_24 => open -- Vcc
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);
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end architecture Test;
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