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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_155.vhd] - Blame information for rev 5
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david237 |
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL) --
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-- David R Brooks --
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-- June, 2016. Perth, Australia --
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-- Compliance: VHDL 2008 --
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-- Testbench for SN74LS155N: Dual 1-of-4 decoder/demultiplexer --
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.numeric_std.all;
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use work.LSTTL.all;
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use work.TTLPrivate.all;
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entity Testbench_155 is -- Top-level bench
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generic(
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StimClk : std_logic := '1';
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CheckClk : std_logic := '1';
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Period : time := 50 ns;
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Finish : time := 20 us;
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SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_155 is
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signal J, B : unsigned(5 downto 0); -- Test stimuli
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signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
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begin
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-----------------------------------------------------------------------
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-- Standard testbench components
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-----------------------------------------------------------------------
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TB: TTLBench
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generic map(
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StimClk => StimClk,
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CheckClk => CheckClk,
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Period => Period,
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Finish => Finish,
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SevLevel => SevLevel
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)
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port map(
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J => J,
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B => B,
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CLK => open,
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RS => open,
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D => D,
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E => E
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);
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-----------------------------------------------------------------------
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-- Generate expected results (with zero delays)
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-----------------------------------------------------------------------
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process(B) is
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variable N : natural range 3 downto 0;
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variable EA, EB : std_logic;
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begin
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N := TTL_to_integer(B(5 downto 4));
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EA := B(0) and not B(1);
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EB := not(B(2) or B(3));
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D <= (others => '1');
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D(N+4) <= not EB;
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D(N) <= not EA;
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end process;
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-----------------------------------------------------------------------
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-- Device Under Test...
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-----------------------------------------------------------------------
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DUT: SN74LS155N
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port map(
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X_1 => B(0), -- EA
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X_2 => B(1), -- EA\
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X_3 => B(5), -- A1
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X_4 => E(3), -- O3A\
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X_5 => E(2), -- O2A\
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X_6 => E(1), -- O1A\
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X_7 => E(0), -- O0A\
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X_8 => open, -- GND
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X_9 => E(4), -- O0B\
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X_10 => E(5), -- O1B\
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X_11 => E(6), -- O2B\
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X_12 => E(7), -- O3B\
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X_13 => B(4), -- A0
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X_14 => B(3), -- EB2\
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X_15 => B(2), -- EB1\
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X_16 => open -- Vcc
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);
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end architecture Test;
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