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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_166.vhd] - Blame information for rev 3

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1 3 david237 
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL)                                         --
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-- David R Brooks                                                    --
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-- June, 2016.  Perth, Australia                                     --
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-- Compliance: VHDL 2008                                             --
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-- Testbench for SN74LS166N: 8-bit PISO shift register               --
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-----------------------------------------------------------------------
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library ieee;
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    use ieee.std_logic_1164.all;
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    use ieee.std_logic_misc.all;
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    use ieee.numeric_std.all;
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    use work.LSTTL.all;
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    use work.TTLPrivate.all;
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entity Testbench_166 is     -- Top-level bench
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generic(
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    StimClk  : std_logic      := '1';
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    CheckClk : std_logic      := '1';
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    Period   : time           := 100 ns;
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    Finish   : time           :=  20 us;
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    SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_166 is
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    signal CLK, ICLK  : std_logic;
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    signal JC, BC     : unsigned(9 downto 0);           -- Test stimuli
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    signal D,  E      : std_logic_vector(0 downto 0);   -- Expected & actual results
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    signal PL, RS     : std_logic;
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    signal CP1, CP2   : std_logic;
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    signal P1         : std_logic_vector(7 downto 0) := (others => '0');
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    signal SR         : std_logic_vector(7 downto 0);
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    alias DS : std_logic is BC(1);
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    begin
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    P1   <= std_logic_vector(BC(9 downto 2));
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    ICLK <= CP1 or CP2;
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    D(0) <= SR(7);
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    process(CLK, RS) is
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        variable X : unsigned(5 downto 0);
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    begin
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        if    RS = '0' then
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            CP1 <= '0';
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            CP2 <= '0';
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            PL  <= '0';
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        elsif rising_edge(CLK) then
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            CP1 <= BC(0);
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            CP2 <= not BC(0);
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            X := BC(X'range);
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            case X is
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                when "000000" => PL <= '0';
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                when others   => PL <= '1';
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            end case;
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        elsif falling_edge(CLK) then
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            CP1 <= '0';
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            CP2 <= '0';
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        end if;
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    end process;
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    -----------------------------------------------------------------------
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    -- Standard testbench components
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    -----------------------------------------------------------------------
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    TB: TTLBench
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    generic map(
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        StimClk  => StimClk,
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        CheckClk => CheckClk,
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        Period   => Period,
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        Finish   => Finish,
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        SevLevel => SevLevel
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    )
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    port map(
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        J    => JC,
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        B    => BC,
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        CLK  => CLK,
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        RS   => RS,
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        D    => D,
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        E    => E
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    );
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    -----------------------------------------------------------------------
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    -- Generate expected results (with zero delays)
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    -----------------------------------------------------------------------
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    process(ICLK, RS) is
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    begin
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        if RS = '0' then           -- Asynchronous reset
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            SR <= (others => '0');
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        elsif rising_edge(ICLK) then
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            if PL = '0' then
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                SR <= P1;
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            else
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                SR <= SR(6 downto 0) & DS;
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            end if;
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        end if;
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    end process;
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    -----------------------------------------------------------------------
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    -- Device Under Test...
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    -----------------------------------------------------------------------
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    DUT: SN74LS166N
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    port map(
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    X_1  => DS,     -- DS
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    X_2  => P1(0),  -- P0
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    X_3  => P1(1),  -- P1
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    X_4  => P1(2),  -- P2
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    X_5  => P1(3),  -- P3
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    X_6  => CP2,    -- CP2
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    X_7  => CP1,    -- CP1
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    X_8  => open,   -- GND
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    X_9  => RS,     -- MR\
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    X_10 => P1(4),  -- P4
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    X_11 => P1(5),  -- P5
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    X_12 => P1(6),  -- P6
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    X_13 => E(0),   -- Q7
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    X_14 => P1(7),  -- P7
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    X_15 => PL,     -- PE\
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    X_16 => open    -- Vcc
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    );
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end architecture Test;

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