| 1 |
3 |
david237 |
-----------------------------------------------------------------------
|
| 2 |
|
|
-- Bipolar TTL models (VHDL) --
|
| 3 |
|
|
-- David R Brooks --
|
| 4 |
|
|
-- June, 2016. Perth, Australia --
|
| 5 |
|
|
-- Compliance: VHDL 2008 --
|
| 6 |
|
|
-- Testbench for SN74LS170N: 4 X 4 register file (open collector) --
|
| 7 |
|
|
-----------------------------------------------------------------------
|
| 8 |
|
|
|
| 9 |
|
|
library ieee;
|
| 10 |
|
|
use ieee.std_logic_1164.all;
|
| 11 |
|
|
use ieee.std_logic_misc.all;
|
| 12 |
|
|
use ieee.numeric_std.all;
|
| 13 |
|
|
use work.LSTTL.all;
|
| 14 |
|
|
use work.TTLPrivate.all;
|
| 15 |
|
|
|
| 16 |
|
|
entity Testbench_170 is -- Top-level bench
|
| 17 |
|
|
generic(
|
| 18 |
|
|
OC : boolean := true;
|
| 19 |
|
|
StimClk : std_logic := '1';
|
| 20 |
|
|
CheckClk : std_logic := '1';
|
| 21 |
|
|
Period : time := 100 ns;
|
| 22 |
|
|
Finish : time := 20 us;
|
| 23 |
|
|
SevLevel : severity_level := failure
|
| 24 |
|
|
);
|
| 25 |
|
|
end entity;
|
| 26 |
|
|
|
| 27 |
|
|
architecture Test of Testbench_170 is
|
| 28 |
|
|
subtype T_quad is std_logic_vector(4 downto 1);
|
| 29 |
|
|
type T_mem is array(3 downto 0) of T_quad;
|
| 30 |
|
|
subtype T_addr is natural range 3 downto 0;
|
| 31 |
|
|
|
| 32 |
|
|
signal J, B : unsigned(5 downto 0); -- Unused
|
| 33 |
|
|
signal D, E : T_quad; -- Expected & actual results
|
| 34 |
|
|
signal CLK, RS : std_logic;
|
| 35 |
|
|
signal RA, WA : unsigned(1 downto 0) := (others => '0');
|
| 36 |
|
|
signal DI : unsigned(4 downto 0);
|
| 37 |
|
|
signal RE, WE : std_logic := '1';
|
| 38 |
|
|
signal Phase : natural;
|
| 39 |
|
|
|
| 40 |
|
|
begin
|
| 41 |
|
|
RA <= J(1 downto 0);
|
| 42 |
|
|
WA <= B(1 downto 0);
|
| 43 |
|
|
|
| 44 |
|
|
-----------------------------------------------------------------------
|
| 45 |
|
|
-- Standard testbench components
|
| 46 |
|
|
-----------------------------------------------------------------------
|
| 47 |
|
|
TB: TTLBench
|
| 48 |
|
|
generic map(
|
| 49 |
|
|
StimClk => StimClk,
|
| 50 |
|
|
CheckClk => CheckClk,
|
| 51 |
|
|
Period => Period,
|
| 52 |
|
|
Finish => Finish,
|
| 53 |
|
|
SevLevel => SevLevel
|
| 54 |
|
|
)
|
| 55 |
|
|
port map(
|
| 56 |
|
|
J => J,
|
| 57 |
|
|
B => B,
|
| 58 |
|
|
CLK => CLK,
|
| 59 |
|
|
RS => RS,
|
| 60 |
|
|
D => D,
|
| 61 |
|
|
E => E
|
| 62 |
|
|
);
|
| 63 |
|
|
|
| 64 |
|
|
-----------------------------------------------------------------------
|
| 65 |
|
|
-- Generate RAM-specific stimuli
|
| 66 |
|
|
-----------------------------------------------------------------------
|
| 67 |
|
|
CLKX: process(CLK, RS) is
|
| 68 |
|
|
variable ER : std_logic;
|
| 69 |
|
|
begin
|
| 70 |
|
|
ER := '1';
|
| 71 |
|
|
WE <= '1';
|
| 72 |
|
|
if RS = '0' then
|
| 73 |
|
|
DI <= (others => '0');
|
| 74 |
|
|
elsif rising_edge(CLK) then
|
| 75 |
|
|
DI <= DI + 1;
|
| 76 |
|
|
case to_integer(DI) is
|
| 77 |
|
|
when 5 | 6 | 7 | 8 => WE <= '0' after 15 ns;
|
| 78 |
|
|
when 9 |10 | 11 | 12 => ER := '0';
|
| 79 |
|
|
when 16 => DI <= (others => '0');
|
| 80 |
|
|
when others => null;
|
| 81 |
|
|
end case;
|
| 82 |
|
|
RE <= ER;
|
| 83 |
|
|
end if;
|
| 84 |
|
|
end process;
|
| 85 |
|
|
|
| 86 |
|
|
-----------------------------------------------------------------------
|
| 87 |
|
|
-- Generate expected results (with zero delays)
|
| 88 |
|
|
-----------------------------------------------------------------------
|
| 89 |
|
|
process(all) is
|
| 90 |
|
|
variable mem : T_mem; -- Testbench memory
|
| 91 |
|
|
variable AR, AW : natural;
|
| 92 |
|
|
variable QI : T_quad;
|
| 93 |
|
|
begin
|
| 94 |
|
|
AR := TTL_to_integer(RA);
|
| 95 |
|
|
AW := TTL_to_integer(WA);
|
| 96 |
|
|
D <= (others => 'Z');
|
| 97 |
|
|
|
| 98 |
|
|
if WE = '0' then
|
| 99 |
|
|
mem(AW) := std_logic_vector(DI(3 downto 0));
|
| 100 |
|
|
end if;
|
| 101 |
|
|
|
| 102 |
|
|
if RE = '0' then
|
| 103 |
|
|
QI := mem(AR);
|
| 104 |
|
|
for i in D'range loop
|
| 105 |
|
|
D(i) <= TTL_OC(QI(i));
|
| 106 |
|
|
end loop;
|
| 107 |
|
|
end if;
|
| 108 |
|
|
end process;
|
| 109 |
|
|
|
| 110 |
|
|
-----------------------------------------------------------------------
|
| 111 |
|
|
-- Device Under Test...
|
| 112 |
|
|
-----------------------------------------------------------------------
|
| 113 |
|
|
DUT: SN74LS170N
|
| 114 |
|
|
port map(
|
| 115 |
|
|
X_1 => DI(1), -- D2
|
| 116 |
|
|
X_2 => DI(2), -- D3
|
| 117 |
|
|
X_3 => DI(3), -- D4
|
| 118 |
|
|
X_4 => RA(1), -- RA1
|
| 119 |
|
|
X_5 => RA(0), -- RA0
|
| 120 |
|
|
X_6 => E(4), -- Q4
|
| 121 |
|
|
X_7 => E(3), -- Q3
|
| 122 |
|
|
X_8 => open, -- GND
|
| 123 |
|
|
X_9 => E(2), -- Q2
|
| 124 |
|
|
X_10 => E(1), -- Q1
|
| 125 |
|
|
X_11 => RE, -- RE\
|
| 126 |
|
|
X_12 => WE, -- WE\
|
| 127 |
|
|
X_13 => WA(1), -- WA1
|
| 128 |
|
|
X_14 => WA(0), -- WA0
|
| 129 |
|
|
X_15 => DI(0), -- D1
|
| 130 |
|
|
X_16 => open -- Vcc
|
| 131 |
|
|
);
|
| 132 |
|
|
end architecture Test;
|
