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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_176.vhd] - Blame information for rev 5

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1 3 david237 
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL)                                         --
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-- David R Brooks                                                    --
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-- June, 2016.  Perth, Australia                                     --
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-- Compliance: VHDL 2008                                             --
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-- Testbench for SN74176N: Presettable decade counter                --
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-----------------------------------------------------------------------
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library ieee;
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    use ieee.std_logic_1164.all;
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    use ieee.std_logic_misc.all;
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    use ieee.numeric_std.all;
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    use work.LSTTL.all;
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    use work.TTLPrivate.all;
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entity Testbench_176 is     -- Top-level bench
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generic(
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    StimClk  : std_logic      := '0';
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    CheckClk : std_logic      := '1';
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    Period   : time           := 120 ns;
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    Finish   : time           :=  20 us;
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    SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_176 is
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    signal RS,  PL     : std_logic;
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    signal CLK, C0, C1 : std_logic;
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    signal J,  B       : unsigned(3 downto 0);          -- Test stimuli
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    signal D,  E,  R   : std_logic_vector(3 downto 0);  -- Expected & actual results
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    begin
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    C0 <= CLK;
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    R  <= std_logic_vector(J);
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    C1 <= D(0);
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    -----------------------------------------------------------------------
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    -- Standard testbench components
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    -----------------------------------------------------------------------
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    TB: TTLBench
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    generic map(
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        StimClk  => StimClk,
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        CheckClk => CheckClk,
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        Period   => Period,
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        Finish   => Finish,
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        SevLevel => SevLevel
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    )
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    port map(
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        J    => J,
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        B    => B,
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        CLK  => CLK,
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        RS   => RS,
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        D    => D,
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        E    => E
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    );
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    -----------------------------------------------------------------------
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    -- Generate irregular LD signal
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    -----------------------------------------------------------------------
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    process(RS, CLK) is
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        variable N : natural;
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    begin
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        if RS = '0' then
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            N  := 1;
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            PL <= '1';
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        elsif rising_edge(CLK) then
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            if N >= 23 then
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                N := 1;
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                PL <= '0', '1' after 30 ns;
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            else
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                N := N + 1;
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            end if;
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        end if;
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    end process;
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    -----------------------------------------------------------------------
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    -- Generate expected results (with zero delays)
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    -----------------------------------------------------------------------
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    process(C0, PL, RS, R) is
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        variable Q0 : std_logic;
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    begin
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        if    RS = '0' then
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            Q0 := '0';
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        elsif PL = '0' then
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            Q0 := R(0);
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        elsif falling_edge(C0) then
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            Q0 := not Q0;
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        end if;
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        D(0) <= Q0;
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    end process;
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    process(C1, PL, RS, R) is
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        variable Q31 : unsigned(2 downto 0);
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    begin
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        if    RS = '0' then
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            Q31 := (others => '0');
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        elsif PL = '0' then
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            Q31 := unsigned(R(3 downto 1));
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        elsif falling_edge(C1) then
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            case TTL_to_integer(Q31) is
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                when 4 to 7 => Q31 := Q31 - 4;
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                when others => Q31 := Q31 + 1;
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            end case;
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        end if;
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        D(3 downto 1) <= std_logic_vector(Q31);
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    end process;
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    -----------------------------------------------------------------------
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    -- Device Under Test...
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    -----------------------------------------------------------------------
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    DUT: SN74176N
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    port map(
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        X_1  => PL,   -- PL\
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        X_2  => E(2), -- Q2
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        X_3  => R(2), -- P2
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        X_4  => R(0), -- P0
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        X_5  => E(0), -- Q0
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        X_6  => C1,   -- CP1\
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        X_7  => open, -- GND
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        X_8  => C0,   -- CP0\
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        X_9  => E(1), -- Q1
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        X_10 => R(1), -- P1
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        X_11 => R(3), -- P3
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        X_12 => E(3), -- Q3
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        X_13 => RS,   -- MR\
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        X_14 => open  -- Vcc
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    );
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end architecture Test;

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