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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_178.vhd] - Blame information for rev 11

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1 3 david237
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL)                                         --
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-- David R Brooks                                                    --
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-- June, 2016.  Perth, Australia                                     --
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-- Compliance: VHDL 2008                                             --
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-- Testbench for SN74178N: 4-bit shift register                      --
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-- Note: 74178 is 74179 without MR\ & Q3\ pins                       --
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-----------------------------------------------------------------------
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library ieee;
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    use ieee.std_logic_1164.all;
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    use ieee.std_logic_misc.all;
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    use ieee.numeric_std.all;
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    use work.LSTTL.all;
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    use work.TTLPrivate.all;
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entity Testbench_178 is     -- Top-level bench
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generic(
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    StimClk  : std_logic      := '1';
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    CheckClk : std_logic      := '1';
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    Period   : time           := 100 ns;
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    Finish   : time           :=  20 us;
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    SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_178 is
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    signal RS, PE, SE : std_logic;
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    signal CLK,DS     : std_logic;
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    signal JC, BC     : unsigned(7 downto 0);           -- Test stimuli
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    signal D,  E      : std_logic_vector(3 downto 0);   -- Expected & actual results
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    signal P, REG     : std_logic_vector(3 downto 0);
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    begin
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        D(3 downto 0) <= REG;
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        P             <= std_logic_vector(JC(3 downto 0));
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        DS            <= JC(4);
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    process(CLK, RS) is
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        variable N : natural := 1;
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    begin
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        if    RS = '0' then
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            N  :=  1;
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            PE <= '0';
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            SE <= '0';
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        elsif falling_edge(CLK) then
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            PE <= '0';
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            SE <= '0';
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            N  := N - 1;
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            case N is
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                when 1                 => PE <= '1';
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                when 2 | 4 | 6 | 8 | 9 => SE <= '1';
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                when 0                 => N  := 16;
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                when others            => null;
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            end case;
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        end if;
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    end process;
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    -----------------------------------------------------------------------
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    -- Standard testbench components
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    -----------------------------------------------------------------------
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    TB: TTLBench
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    generic map(
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        StimClk  => StimClk,
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        CheckClk => CheckClk,
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        Period   => Period,
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        Finish   => Finish,
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        SevLevel => SevLevel
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    )
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    port map(
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        J    => JC,
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        B    => BC,
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        CLK  => CLK,
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        RS   => RS,
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        D    => D,
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        E    => E
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    );
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    -----------------------------------------------------------------------
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    -- Generate expected results (with zero delays)
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    -----------------------------------------------------------------------
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    process(CLK) is
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    begin
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        if falling_edge(CLK) then
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            if SE    = '1' then
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                REG <= REG(2 downto 0) & DS;
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            elsif PE = '1' then
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                REG <= P;
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            end if;
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        end if;
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    end process;
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    -----------------------------------------------------------------------
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    -- Device Under Test...                        
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    -----------------------------------------------------------------------
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    DUT: SN74178N
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    port map(
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        X_1  => P(1),  -- P1
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        X_2  => P(0),  -- P0
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        X_3  => DS,    -- DS
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        X_4  => E(0),  -- Q0
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        X_5  => CLK,    -- CP\
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        X_6  => E(1),  -- Q1
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        X_7  => open,  -- GND
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        X_8  => E(2),  -- Q2
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        X_9  => PE,    -- PE
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        X_10 => E(3),  -- Q3
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        X_11 => SE,    -- SE
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        X_12 => P(3),  -- P3
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        X_13 => P(2),  -- P2
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        X_14 => open   -- Vcc
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    );
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end architecture Test;

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