OpenCores
URL https://opencores.org/ocsvn/ttl_library/ttl_library/trunk

Subversion Repositories ttl_library

[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_189.vhd] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 david237 
-----------------------------------------------------------------------
2 
-- Bipolar TTL models (VHDL)                                         --
3 
-- David R Brooks                                                    --
4 
-- July, 2016.  Perth, Australia                                     --
5 
-- Compliance: VHDL 2008                                             --
6 
-- Testbench for SN74LS189N: 64-bit RAM (3-state outputs)            --
7 
-----------------------------------------------------------------------
8 
 
9 
library ieee;
10 
    use ieee.std_logic_1164.all;
11 
    use ieee.std_logic_misc.all;
12 
    use ieee.numeric_std.all;
13 
    use work.LSTTL.all;
14 
    use work.TTLPrivate.all;
15 
 
16 
entity Testbench_189 is     -- Top-level bench
17 
generic(
18 
    OC       : boolean        := false;
19 
    StimClk  : std_logic      := '1';
20 
    CheckClk : std_logic      := '1';
21 
    Period   : time           := 100 ns;
22 
    Finish   : time           :=  20 us;
23 
    SevLevel : severity_level := failure
24 
);
25 
end entity;
26 
 
27 
architecture Test of Testbench_189 is
28 
    signal J, B      : unsigned(5 downto 0);         -- Unused
29 
    signal D, E      : std_logic_vector(3 downto 0); -- Expected & actual results
30 
    signal CLK, RS   : std_logic;
31 
    signal CS,  WR   : std_logic := '1';
32 
    signal AD        : TTLword   := (others => '0');
33 
    signal DI, Q, QQ : TTLquad;
34 
    signal CE, WE    : std_logic;
35 
 
36 
    signal W         : std_logic;
37 
    signal Phase     : natural;
38 
 
39 
    begin
40 
    -----------------------------------------------------------------------
41 
    -- Standard testbench components
42 
    -----------------------------------------------------------------------
43 
    TB: TTLBench
44 
    generic map(
45 
        StimClk  => StimClk,
46 
        CheckClk => CheckClk,
47 
        Period   => Period,
48 
        Finish   => Finish,
49 
        SevLevel => SevLevel
50 
    )
51 
    port map(
52 
        J    => J,
53 
        B    => B,
54 
        CLK  => CLK,
55 
        RS   => RS,
56 
        D    => D,
57 
        E    => E
58 
    );
59 
 
60 
    -----------------------------------------------------------------------
61 
    -- Generate RAM-specific stimuli
62 
    -----------------------------------------------------------------------
63 
    CLKX: process(CLK, RS) is
64 
    begin
65 
        if RS = '0' then
66 
            Phase <=  0;
67 
            CS    <= '1';
68 
            WR    <= '1';
69 
        elsif rising_edge(CLK) then
70 
            case Phase is
71 
                when 0      => CS <= '0';             Phase <= 1;
72 
                when 1      =>             WR <=  W;  Phase <= 2;
73 
                when 2      =>             WR <= '1'; Phase <= 3;
74 
                when others => CS <= '1';  WR <= '1'; Phase <= 0;
75 
            end case;
76 
        end if;
77 
    end process;
78 
 
79 
    UPDATE: process(CLK, RS) is
80 
        variable TD : unsigned(3 downto 0);
81 
    begin
82 
        if RS = '0' then
83 
            W  <= '0';
84 
            AD <= (others => '0');
85 
            TD := "0110";
86 
        elsif rising_edge(CLK) and Phase = 3 then
87 
            if AD = "1111" then
88 
                W <= not W;         -- Alternate read/write cycles
89 
            end if;
90 
            AD <= AD + 1;
91 
            TD := TD + 1;
92 
        end if;
93 
        for i in TD'range loop
94 
            DI(i+1) <= TD(i);
95 
        end loop;
96 
    end process;
97 
 
98 
    -----------------------------------------------------------------------
99 
    -- Generate expected results (with zero delays)
100 
    -----------------------------------------------------------------------
101 
    CE <= WR and not CS;
102 
    WE <= not(WR or CS);
103 
 
104 
    process(CE, WE, AD, DI) is
105 
        variable mem : TTLmem;      -- Testbench memory
106 
        variable adr : TTLaddr;
107 
        variable QI  : TTLquad;
108 
    begin
109 
        adr := TTL_to_integer(AD);
110 
        if WE'event and WE = '1' then
111 
            mem(adr) := not DI;     -- Data is output inverted
112 
        end if;
113 
 
114 
        if CE = '1' then
115 
            QI := mem(adr);
116 
        else
117 
            QI := (others => 'Z');
118 
        end if;
119 
        if OC then
120 
            for i in Q'range loop
121 
                Q(i) <= TTL_OC(QI(i));
122 
            end loop;
123 
        else
124 
            Q <= QI;
125 
        end if;
126 
    end process;
127 
 
128 
    D <= Q;
129 
    E <= QQ;
130 
 
131 
    -----------------------------------------------------------------------
132 
    -- Device Under Test...
133 
    -----------------------------------------------------------------------
134 
    DUT: SN74LS189N
135 
    port map(
136 
    X_1  => AD(0),  -- A0
137 
    X_2  => CS,     -- CS\
138 
    X_3  => WR,     -- WE\
139 
    X_4  => DI(1),  -- D1
140 
    X_5  => QQ(1),  -- Q1\
141 
    X_6  => DI(2),  -- D2
142 
    X_7  => QQ(2),  -- Q2\
143 
    X_8  => open,   -- GND
144 
    X_9  => QQ(3),  -- Q3\
145 
    X_10 => DI(3),  -- D3
146 
    X_11 => QQ(4),  -- Q4\
147 
    X_12 => DI(4),  -- D4
148 
    X_13 => AD(3),  -- A3
149 
    X_14 => AD(2),  -- A2
150 
    X_15 => AD(1),  -- A1
151 
    X_16 => open    -- Vcc
152 
);
153 
end architecture Test;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.