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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_190.vhd] - Blame information for rev 5

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1 3 david237 
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL)                                         --
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-- David R Brooks                                                    --
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-- August, 2016.  Perth, Australia                                   --
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-- Compliance: VHDL 2008                                             --
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-- Testbench for SN74LS190N: Up/down decade counter                  --
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-----------------------------------------------------------------------
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library ieee;
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    use ieee.std_logic_1164.all;
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    use ieee.std_logic_misc.all;
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    use ieee.numeric_std.all;
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    use work.LSTTL.all;
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    use work.TTLPrivate.all;
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entity Testbench_190 is     -- Top-level bench
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generic(
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    StimClk  : std_logic      := '1';
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    CheckClk : std_logic      := '1';
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    Period   : time           := 100 ns;
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    Finish   : time           :=  15 us;
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    SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_190 is
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    signal JC, BC : unsigned(6 downto 0);           -- Test stimuli
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    signal D, E   : std_logic_vector(5 downto 0);   -- Expected & actual results
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    signal P      : unsigned(3 downto 0);
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    signal CP     : std_logic;
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    signal RS, PL : std_logic;
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    signal CE, UD : std_logic;
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    signal T1,  T2,  T3,  T4,  T5,
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           T6,  T7,  T8,  T9,  T10,
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           T11, T12, T13, T14, T15,
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           T16      : std_logic;
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    signal Q, QB, X : unsigned(3 downto 0);
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    begin
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    P  <= JC(6 downto 3);
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    CE <= BC(6);
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    process(CP) is
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    begin
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        if rising_edge(CP) then
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            PL <= RS and nand_reduce(std_logic_vector(BC(4 downto 0))) after 10 ns, '1' after 80 ns;
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            UD <= BC(5);
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        end if;
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    end process;
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    -----------------------------------------------------------------------
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    -- Standard testbench components
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    -----------------------------------------------------------------------
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    TB: TTLBench
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    generic map(
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        StimClk  => StimClk,
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        CheckClk => CheckClk,
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        Period   => Period,
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        Finish   => Finish,
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        SevLevel => SevLevel
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   )
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    port map(
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        J    => JC,
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        B    => BC,
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        CLK  => CP,
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        RS   => RS,
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        D    => D,
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        E    => E
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   );
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    -----------------------------------------------------------------------
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    -- Generate expected results (with zero delays)
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    -----------------------------------------------------------------------
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    T1   <= not (UD);
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    T2   <= not (UD or CE);
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    T3   <= not (CE or T1);
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    T4   <= not (QB(1) and QB(2) and QB(3));
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    T5   <= T3 and QB(0) and T4;
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    T6   <= Q(0) and QB(3) and T2;
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    T7   <= T4 and T3 and QB(0) and QB(1);
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    T8   <= Q(0) and Q(1) and T2;
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    T9   <= T3 and QB(0) and QB(1) and QB(2);
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    T10  <= Q(0) and Q(3) and T2;
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    T11  <= Q(0) and Q(1) and Q(2) and T2;
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    X(0) <= not (CE);
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    X(1) <= T5 or T6;
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    X(2) <= T7 or T8;
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    X(3) <= T9 or T10 or T11;
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    process(CP, PL) is
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    begin
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        if PL = '0' then
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            Q <= P;
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        elsif rising_edge(CP) and (CE = '0') then
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            Q <= Q xor X;       -- 'T' flipflops
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        end if;
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    end process;
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    QB  <= not Q;
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    T15  <= (T1 and Q(0) and Q(3));   -- True for count = 9, 11, 13, 15
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    T16  <= (UD and QB(0) and QB(1) and QB(2) and QB(3));
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    T12  <= (T15 or T16);
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    T13  <= not (CP);
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    T14  <= not (CE);
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    D(3 downto 0) <= std_logic_vector(Q);
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    D(4) <=  T12;
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    D(5) <= not (T13 and T14 and T12);
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    -----------------------------------------------------------------------
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    -- Device Under Test...
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    -----------------------------------------------------------------------
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    DUT: SN74LS190N
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    port map(
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        X_1  => P(1), --  P1
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        X_2  => E(1), --  Q1
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        X_3  => E(0), --  Q0
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        X_4  => CE,   --  CE\
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        X_5  => UD,   --  U\/D
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        X_6  => E(2), --  Q2
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        X_7  => E(3), --  Q3
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        X_8  => open, --  GND
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        X_9  => P(3), --  P3
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        X_10 => P(2), --  P2
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        X_11 => PL,   --  PL\
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        X_12 => E(4), --  TC
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        X_13 => E(5), --  RC\
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        X_14 => CP,   --  CP
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        X_15 => P(0), --  P0
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        X_16 => open  --  Vcc
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   );
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end architecture Test;

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