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david237 |
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL) --
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-- David R Brooks --
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-- August, 2016. Perth, Australia --
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-- Compliance: VHDL 2008 --
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-- Testbench for SN74LS192N: Up/down decade counter --
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.numeric_std.all;
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use work.LSTTL.all;
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use work.TTLPrivate.all;
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entity Testbench_192 is -- Top-level bench
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generic(
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StimClk : std_logic := '1';
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CheckClk : std_logic := '1';
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Period : time := 100 ns;
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Finish : time := 15 us;
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SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_192 is
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signal JC, BC : unsigned(6 downto 0); -- Test stimuli
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signal D, E : std_logic_vector(5 downto 0); -- Expected & actual results
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signal P : unsigned(3 downto 0);
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signal CLK, CPU, CPD : std_logic;
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signal MR, RS, PL : std_logic;
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signal Q, QB : unsigned(3 downto 0);
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signal T1, T2, T3, T4, T5,
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T6, T7, T8, T9, T10,
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T11, T12 : std_logic;
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signal CX, CL, PR, CC : std_logic_vector(3 downto 0);
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begin
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P <= JC(6 downto 3);
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MR <= not RS; -- Active high
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process(CLK) is
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begin
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if rising_edge(CLK) then
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PL <= nand_reduce(std_logic_vector(BC(4 downto 0))) after 10 ns, '1' after 80 ns;
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CPU <= BC(5);
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CPD <= not BC(5);
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elsif falling_edge(CLK) then -- NB Inactive clock should be high
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CPU <= '1';
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CPD <= '1';
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end if;
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end process;
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-----------------------------------------------------------------------
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-- Standard testbench components
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-----------------------------------------------------------------------
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TB: TTLBench
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generic map(
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StimClk => StimClk,
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CheckClk => CheckClk,
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Period => Period,
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Finish => Finish,
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SevLevel => SevLevel
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)
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port map(
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J => JC,
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B => BC,
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CLK => CLK,
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RS => RS,
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D => D,
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E => E
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);
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-----------------------------------------------------------------------
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-- Generate expected results (with zero delays)
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-----------------------------------------------------------------------
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T1 <= not (CPD);
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T2 <= not (CPU);
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T3 <= not (QB(1) and QB(2) and QB(3));
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T4 <= T1 and QB(0) and T3;
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T5 <= Q(0) and QB(3) and T2;
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T6 <= T3 and T1 and QB(0) and QB(1);
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T7 <= Q(0) and Q(1) and T2;
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T8 <= T1 and QB(0) and QB(1) and QB(2);
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T9 <= Q(0) and Q(3) and T2;
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T10 <= Q(0) and Q(1) and Q(2) and T2;
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T11 <= not (MR);
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T12 <= not (PL);
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CX(0) <= not (T1 or T2);
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CX(1) <= not (T4 or T5);
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CX(2) <= not (T6 or T7);
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CX(3) <= not (T8 or T9 or T10);
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G: for i in CX'range generate
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begin
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PR(i) <= not (P(i) and T12 and T11);
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CC(i) <= not (PR(i) and T12);
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CL(i) <= (T11 and CC(i));
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process(CX, PR, CL) is -- A 'T' flipflop
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begin
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if CL(i) = '0' then
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Q(i) <= '0';
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elsif PR(i) = '0' then
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Q(i) <= '1';
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elsif rising_edge(CX(i)) then
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Q(i) <= not Q(i);
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end if;
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end process;
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end generate;
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QB <= not Q;
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D(3 downto 0) <= std_logic_vector(Q);
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D(4) <= not (Q(0) and Q(3) and T2);
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D(5) <= not (T1 and QB(0) and QB(1) and QB(2) and QB(3));
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-----------------------------------------------------------------------
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-- Device Under Test...
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-----------------------------------------------------------------------
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DUT: SN74LS192N
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port map(
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X_1 => P(1), -- P1
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X_2 => E(1), -- Q1
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X_3 => E(0), -- Q0
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X_4 => CPD, -- CPD
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X_5 => CPU, -- CPU
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X_6 => E(2), -- Q2
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X_7 => E(3), -- Q3
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X_8 => open, -- GND
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X_9 => P(3), -- P3
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X_10 => P(2), -- P2
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X_11 => PL, -- PL\
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X_12 => E(4), -- TCU\
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X_13 => E(5), -- TCD\
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X_14 => MR, -- MR
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X_15 => P(0), -- P0
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X_16 => open -- Vcc
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);
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end architecture Test;
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