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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_198.vhd] - Blame information for rev 3

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1 3 david237 
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL)                                         --
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-- David R Brooks                                                    --
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-- December, 2016.  Perth, Australia                                 --
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-- Compliance: VHDL 2008                                             --
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-- Testbench for SN74LS198N: 8-bit right/left shift register         --
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-----------------------------------------------------------------------
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library ieee;
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    use ieee.std_logic_1164.all;
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    use ieee.std_logic_misc.all;
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    use ieee.numeric_std.all;
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    use work.LSTTL.all;
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    use work.TTLPrivate.all;
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entity Testbench_198 is     -- Top-level bench
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generic(
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    StimClk  : std_logic      := '1';
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    CheckClk : std_logic      := '1';
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    Period   : time           := 50 ns;
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    Finish   : time           := 50 us;
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    SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_198 is
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    signal CLK, RS  : std_logic;
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    signal JC,  BC  : unsigned(9 downto 0);       -- Test stimuli
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    signal D,   E   : std_logic_vector(0 to 7);   -- Expected & actual results
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    signal S        : std_logic_vector(1 downto 0);
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    signal P,   Q   : std_logic_vector(0 to 7);
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    signal DSR, DSL : std_logic;
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    signal L1 : std_logic;
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    signal L2 : std_logic;
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    signal L3 : std_logic;
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    signal L4 : std_logic;
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    signal N0 : std_logic;
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    signal T1, T2, T3, T4 : std_logic_vector(0 to 7);
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    begin
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    P    <= std_logic_vector(JC(7 downto 0));
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    DSR  <= JC(8);
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    DSL  <= JC(9);
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    S    <= std_logic_vector(BC(5 downto 4));
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    -----------------------------------------------------------------------
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    -- Standard testbench components
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    -----------------------------------------------------------------------
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    TB: TTLBench
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    generic map(
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        StimClk  => StimClk,
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        CheckClk => CheckClk,
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        Period   => Period,
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        Finish   => Finish,
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        SevLevel => SevLevel
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   )
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    port map(
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        J    => JC,
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        B    => BC,
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        CLK  => CLK,
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        RS   => RS,
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        D    => D,
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        E    => E
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   );
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    -----------------------------------------------------------------------
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    -- Generate expected results (with zero delays)
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    -----------------------------------------------------------------------
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    L1 <= not S(1);
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    L2 <= not S(0);
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    L3 <= L1 and L2;
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    L4 <= not(L1 or L2);
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    N0 <= CLK or L3;
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    T1(0) <= DSR and L1;
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    T3(7) <= L2 and DSL;
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    G1: for i in 1 to 7 generate
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    begin
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        T1(i) <=  (Q(i-1) and L1);
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    end generate;
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    G2: for i in 0 to 6 generate
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    begin
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        T3(i) <= L2 and Q(i+1);
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    end generate;
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    G3: for i in 0 to 7 generate
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    begin
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        T2(i) <= L4 and P(i);
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        T4(i) <= T1(i) or T2(i) or T3(i);
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        DQ : TTL_FF port map(q=>Q(i), d=>T4(i), clk=>N0, cl=>RS);
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    end generate;
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    D <= Q;
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    -----------------------------------------------------------------------
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    -- Device Under Test...
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    -----------------------------------------------------------------------
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    DUT: SN74LS198N
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    port map(
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        X_1  => S(0),  --  S(0)
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        X_2  => DSR,   --  DSR
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        X_3  => P(0),  --  P0
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        X_4  => E(0),  --  Q0
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        X_5  => P(1),  --  P1
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        X_6  => E(1),  --  Q1
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        X_7  => P(2),  --  P2
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        X_8  => E(2),  --  Q2
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        X_9  => P(3),  --  P3
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        X_10 => E(3),  --  Q3
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        X_11 => CLK,   --  CP
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        X_12 => open,  --  GND
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        X_13 => RS,    --  MR\
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        X_14 => E(4),  --  Q4
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        X_15 => P(4),  --  P4
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        X_16 => E(5),  --  Q5
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        X_17 => P(5),  --  P5
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        X_18 => E(6),  --  Q6
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        X_19 => P(6),  --  P6
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        X_20 => E(7),  --  Q7
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        X_21 => P(7),  --  P7
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        X_22 => DSL,   --  DSL
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        X_23 => S(1),  --  S(1)
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        X_24 => open   --  Vcc
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   );
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end architecture Test;

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