OpenCores
URL https://opencores.org/ocsvn/ttl_library/ttl_library/trunk

Subversion Repositories ttl_library

[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_198.vhd] - Blame information for rev 4

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 david237 
-----------------------------------------------------------------------
2 
-- Bipolar TTL models (VHDL)                                         --
3 
-- David R Brooks                                                    --
4 
-- December, 2016.  Perth, Australia                                 --
5 
-- Compliance: VHDL 2008                                             --
6 
-- Testbench for SN74LS198N: 8-bit right/left shift register         --
7 
-----------------------------------------------------------------------
8 
 
9 
library ieee;
10 
    use ieee.std_logic_1164.all;
11 
    use ieee.std_logic_misc.all;
12 
    use ieee.numeric_std.all;
13 
    use work.LSTTL.all;
14 
    use work.TTLPrivate.all;
15 
 
16 
entity Testbench_198 is     -- Top-level bench
17 
generic(
18 
    StimClk  : std_logic      := '1';
19 
    CheckClk : std_logic      := '1';
20 
    Period   : time           := 50 ns;
21 
    Finish   : time           := 50 us;
22 
    SevLevel : severity_level := failure
23 
);
24 
end entity;
25 
 
26 
architecture Test of Testbench_198 is
27 
    signal CLK, RS  : std_logic;
28 
    signal JC,  BC  : unsigned(9 downto 0);       -- Test stimuli
29 
    signal D,   E   : std_logic_vector(0 to 7);   -- Expected & actual results
30 
    signal S        : std_logic_vector(1 downto 0);
31 
    signal P,   Q   : std_logic_vector(0 to 7);
32 
    signal DSR, DSL : std_logic;
33 
 
34 
    signal L1 : std_logic;
35 
    signal L2 : std_logic;
36 
    signal L3 : std_logic;
37 
    signal L4 : std_logic;
38 
    signal N0 : std_logic;
39 
 
40 
    signal T1, T2, T3, T4 : std_logic_vector(0 to 7);
41 
 
42 
 
43 
    begin
44 
    P    <= std_logic_vector(JC(7 downto 0));
45 
    DSR  <= JC(8);
46 
    DSL  <= JC(9);
47 
    S    <= std_logic_vector(BC(5 downto 4));
48 
 
49 
    -----------------------------------------------------------------------
50 
    -- Standard testbench components
51 
    -----------------------------------------------------------------------
52 
    TB: TTLBench
53 
    generic map(
54 
        StimClk  => StimClk,
55 
        CheckClk => CheckClk,
56 
        Period   => Period,
57 
        Finish   => Finish,
58 
        SevLevel => SevLevel
59 
   )
60 
    port map(
61 
        J    => JC,
62 
        B    => BC,
63 
        CLK  => CLK,
64 
        RS   => RS,
65 
        D    => D,
66 
        E    => E
67 
   );
68 
 
69 
    -----------------------------------------------------------------------
70 
    -- Generate expected results (with zero delays)
71 
    -----------------------------------------------------------------------
72 
    L1 <= not S(1);
73 
    L2 <= not S(0);
74 
    L3 <= L1 and L2;
75 
    L4 <= not(L1 or L2);
76 
    N0 <= CLK or L3;
77 
 
78 
    T1(0) <= DSR and L1;
79 
    T3(7) <= L2 and DSL;
80 
 
81 
    G1: for i in 1 to 7 generate
82 
    begin
83 
        T1(i) <=  (Q(i-1) and L1);
84 
    end generate;
85 
 
86 
    G2: for i in 0 to 6 generate
87 
    begin
88 
        T3(i) <= L2 and Q(i+1);
89 
    end generate;
90 
 
91 
    G3: for i in 0 to 7 generate
92 
    begin
93 
        T2(i) <= L4 and P(i);
94 
        T4(i) <= T1(i) or T2(i) or T3(i);
95 
        DQ : TTL_FF port map(q=>Q(i), d=>T4(i), clk=>N0, cl=>RS);
96 
    end generate;
97 
 
98 
    D <= Q;
99 
 
100 
    -----------------------------------------------------------------------
101 
    -- Device Under Test...
102 
    -----------------------------------------------------------------------
103 
    DUT: SN74LS198N
104 
    port map(
105 
        X_1  => S(0),  --  S(0)
106 
        X_2  => DSR,   --  DSR
107 
        X_3  => P(0),  --  P0
108 
        X_4  => E(0),  --  Q0
109 
        X_5  => P(1),  --  P1
110 
        X_6  => E(1),  --  Q1
111 
        X_7  => P(2),  --  P2
112 
        X_8  => E(2),  --  Q2
113 
        X_9  => P(3),  --  P3
114 
        X_10 => E(3),  --  Q3
115 
        X_11 => CLK,   --  CP
116 
        X_12 => open,  --  GND
117 
        X_13 => RS,    --  MR\
118 
        X_14 => E(4),  --  Q4
119 
        X_15 => P(4),  --  P4
120 
        X_16 => E(5),  --  Q5
121 
        X_17 => P(5),  --  P5
122 
        X_18 => E(6),  --  Q6
123 
        X_19 => P(6),  --  P6
124 
        X_20 => E(7),  --  Q7
125 
        X_21 => P(7),  --  P7
126 
        X_22 => DSL,   --  DSL
127 
        X_23 => S(1),  --  S(1)
128 
        X_24 => open   --  Vcc
129 
   );
130 
end architecture Test;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.